Elec 24: Digital System Design Laboratory ELEC 24 Digital System Design LABORATORY MANUAL : 4-bit hexadecimal Decoder & 4-bit Increment by N Circuit College of Engineering Koç University Important Note: In order to effectively utilize the laboratory sessions, you should read the manual and prepare the experiments before the sessions.
Elec 24: Digital System Design Laboratory 1. Objectives: To design and simulate a 4-bit hexadecimal decoder To design and simulate a 4-bit increment by N circuit. To implement the both circuits on FPGA To test the decoder and increment circuits 2. Equipments: Digilent Basys2 board Pentium PC 3. Procedure: i. Read the Background parts ii. Perform preliminary work before coming to lab Derive the truth table of 4-bit decoder-result is to be displayed on 7-segment Designing the 4-bit decoder Designing the 4-bit increment by N circuit iii. Perform the experimental work during the lab Implement your circuits on Foundation Software Simulate the circuits Verify the correctness of your circiuts Implemente one of the circuit in the FPGA Test the circuit 4. Part1 - Designing a 4 7 decoder Background display. In this part, we want to display each hexadecimal digit (,1,...1,A,b,C,d,E) on the 7-segment Pin numbers So in order to display, for example, the hexadecimal digit A (1 in decimal), the LEDs with labels S, S, S, S, S, S should be ON, and the other LED S should be OFF. This means that the 2 5 6 4 1 3 corresponding pins [ P, P, P, P, P, P ] should have logic-1 (5Volts). 24 18 19 23 26 2 Since we can represent each hexadecimal digit by means of 4 bits, we ll implement a 4 7 decoder.
Elec 24: Digital System Design Laboratory (LSB) (MSB) D D1 D2 D3 4 7 decoder P19 P18 P23 P2 P24 P26 P25 7-SEGMENT DISPLAY Preliminary Work - 1: Design a decoder that maps each 4-bit hexadecimal digit (,1,...,A,..,E) into appropriate pins (which control the LEDs of 7-segment display) in a way that we can view the digit on the 7-segment display. To do this, first you have to learn about how the leds of 7-segment display becomes ON and OFF. Our Basys2 board has cathodes for controlling the LEDs of 7-segment display: As it can be seen from the figure LEDs turn ON only when the corresponding cathode signals are LOW. We will derive the truth table according to this fact as seen in below figure for 1 and 2. Derive the truth table of the decoder (which will be a 16 11 table)
Elec 24: Digital System Design Laboratory Considering the truth table, design an optimum circuit truth table with LOW signals meaning ON 7- segment display of PEGASUS 5. Part2 - Designing a 4-bit Increment by N Circuit Background: The Half Adder adds two bits and generates a sum and a carry-out output. However, to be useful for adding binary words, one needs a Full Adder which has three inputs: the augend, the addend, and a carry-in. The following example illustrates the addition of two 4-bit words A=[ A A A A ] and 3 2 1 B=[ B B B B ] where A is the MSB of the 4-bit-word A and A is the the LSB of the 4-bit-word A. 3 2 1 3 In the same way, B and B are the MSB and LSB bits of the 4-bit-word B, respectively. 3 the carry-in bit below. Figure 1: Addition of binary numbers The addition can be split-up in bit slices. Each slice performs the addition of the bits A, i B and i C (i.e. carry-out bit of the previous slice). Each slice consists of a full adder, illustrated i Figure 2: Block diagram of a full adder (FA) A circuit that implements a full adder is given in Figure 3 below.
Elec 24: Digital System Design Laboratory Figure 3: Logic diagram of a Full Adder The circuit consists of two XOR gates, two AND gates and one OR gate. Preliminary Work - 2: Starting with a 4-bit full adder circuit use contraction method, that is removal of redundancy from circuit to which input fixing has been applied, to design a 4-bit increment by N circuit. The 4-bit increment value N will be d 2 8 if d N d 2 d 8 if where d is the least significant hexadecimal digit of your student ID. For example, if your student ID is 26222 = x132183e, then d = e, and N = e-2 = c = 11. Experimental Work - 1: Implement your 7-segment decoder circuit using VHDL. Simulate the circuit Verify the correctness of your circuit. If testing on the FPGA, download your *.bit file into Basys2 board and test it. While testing use 4 logic-switches SW3, SW2, SW1 and SW as inputs and the pins L14, H12, N14, N11, P12, L13, M12 that control the 7-LEDs as output. Then, try all the possible 16 combinations and see the result on the 7-segment display. Experimental Work - 2: Create a new VHDL module called Lab3. In this schematic you will be using buses. A bus is an array of signals, and is displayed as a thicker line than a regular wire. When using a bus, the naming convention is to give the bus a name in the form of bus_name[x:y], where bus_name is the variable name and X is the most significant bit and Y is the least significant bit. Individual signals in the bus are named bus_namen where N is between X and Y. Individual signals can be accessed by wiring a regular wire from a bus to a terminal and giving the internal node the name corresponding to the desired signal(or by using the Draw Bus Taps tool, try it to see what it does). After creating the IncN schematic that implements your 4-bit increment by N design in the preliminary work, simulate the increment by N for a few different inputs using both hexadecimal and decimal notation (functional mode simulation). Again, only 1 schematic should be listed in the main project window. At this point, Lab2.sch is the main top-level schematic and thus should be the only schematic file listed. In the Foundation Logic Simulator, the state of a bus signal can be set to a hexadecimal number using the Bus button within the states selection window. To change the base the number is displayed in, select the bus you want to change then go to Signal:Bus and select the desired base. If testing your circuit, use the logic switches of the Basys2 board as input to the increment by N circuit. Your inputs will be a 4-bit number. You should display the 4-bit result of the increment by N on 7-segment display by using the 4x7 decoder implemented in Part-1, the carry out bit C 4 and overflow flag can be displayed using two leds on your Basys2 board.
Elec 24: Digital System Design Laboratory 6. Assessment (Lab Report) 1. Brief description of the lab experiment including the goals and discussion on the theory of operation. 2. Design and schematics of your experiment circuit. 3. Present simulation waveforms. 4. Review of the results indicating that the circuit functions properly. You can for instance give a truth table and indicate that for each entry the logic simulator give the right results. Feel free to label the waveforms to indicate the proper operation. 5. Conclusions and discussions.