Lab #11: Register Files ECE/COE 0501 Date of Experiment: 3/20/2017 Report Written: 3/22/2017 Submission Date: 3/27/2017 Nicholas Haver nicholas.haver@pitt.edu 1 H a v e r
PURPOSE The purpose of this lab was to design, simulate, build, and test a 4 address, 4-bit register file. The circuit allowed a user to select an address to write to, write a 4-bit (hexadecimal) value to each address, and read a 4-bit value from each address. The circuit used a 74670 4x4 register and two 74193 binary counters with user-controlled clock signals to cycle through each address to read and write. The usercontrolled write enable, write up, and read up signals were inputted using de-bounced switches constructed with 7400 NAND integrated circuits. Input and output values were displayed for ease of use utilizing two 7-segment LED displays, each driven by a 74247 BCD-to-7 segment decoder. PROCEDURE 1) Using Altera Quartus II, a 4x4 user controlled register was designed with a 74670 register and two 74193 counters. For the 4x4 register, an active low write enable signal must be included and set low to write to the register. Write up and read up signals allowed the user to control the counter clock signals, cycling through the four addresses to read and write. In preparation for circuit construction, two 74247 decoders were also added to the design in Figure 1. 2) A 4-bit input for D, as well as inputs for write enable, write up, and read up were entered into the vector waveform file shown in Figure 2, and the circuit was simulated to perform the following tasks: a. Write 7 to register 0 b. Write 9 to register 1 c. Read value from register 0 d. Write 3 to register 3 e. Write 10 to register 2 f. Read value from register 2 g. Read value from register 1 h. Write 5 to register 0 i. Read value from register 3 j. Read value from register 0 3) After verifying the list of tasks above were completed correctly, the circuit was constructed on the breadboard. 4) The circuit was constructed based on the schematic in Figure 1, and the D, write enable, write up, and read up inputs were connected to a logic analyzer along with the write counter, read counter, and Q outputs. 5) Using the logic analyzer, circuit functionality was confirmed by performing the following tasks: a. Write 7 to register 1 b. Write 9 to register 2 c. Write 10 to register 3 d. Write 3 to register 0 e. Read registers 0, 1, 2, and 3 2 H a v e r
RESULTS Figure 1: Schematic that was built and simulated in Altera Quartus II prior to real circuit construction Using Altera Quartus II, the schematic in Figure 1 was created utilizing: 1) 1 74670 4x4 register file 2) 2 74193 4-bit synchronous up/down counters 3) 2 74247 7-segment display decoders Figure 2 shows the input/output waveform generated from simulating the Altera Quartus schematic. In addition to the binary-coded decimal input (D) and output (Q), the outputs of the two 7-segment display decoders were also included in the simulation. Figure 2: Altera Quartus II simulation input and output waveform 3 H a v e r
For each input/output value, the output of the BCD to 7-segment decoder was recorded and verified using the diagram in Figure 7. Table 1 shows each decimal value and its corresponding 7-segment decoder output. DECIMAL DECODER OUTPUT RBON OA OB OC OD OE OF OG 7 1 0 0 0 1 1 1 1 9 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 10 1 1 1 1 0 0 1 0 3 1 0 0 0 0 1 1 0 5 1 0 1 0 0 1 0 0 Table 1: Decimal input and decoder output for 74247 decoder Figure 3: Pin configuration for 74670 4x4 register file Figure 4: Pin configuration for 74193 binary counter Figure 3 shows the pin configuration for the 74670 4x4 register file. The inputs and outputs for the 4x4 register are shown in Table 2. The register can store four 4-bit words, each through inputs D0 D3 and outputs Q0 Q3. The write address is determined through inputs WA and WB while the read address is determined through inputs RA and RB. For the register to write to an address, the write enable (WE ) must be set to low (0 V). Unlike a memory, a register has two separate read enable and write enable inputs, meaning that both read and write can be enabled simultaneously. Because of this capability, the read enable (RE ) input was set to low for the duration of the experiment. Figure 4 shows the pin configuration for the 74193 4-bit synchronous counter. While the counter has a 4- bit capacity, only the lower 2 bits (Q0 Q1) were used to cycle through the 4 addresses in the register. Due to the symmetry of the binary number system, this unused capacity had no effect on counter functionality. The inputs and outputs for the 4-bit synchronous counter are shown in Table 3. 4 H a v e r
Table 2: Input and output table for 74670 4x4 register file Table 3: Input and output table for 74193 binary counter Figure 5: Connection diagrams for 74247 BCD to 7-segment decoder Figure 5 shows the connection diagrams for the 74247 binary coded decimal-to-seven segment display decoder. This decoder was implemented to drive two seven-segment displays, one for the input D0-D3 and one for the output Q0-Q3. A 4-bit binary coded decimal input is attached to pins A0-A3, and pins a - g correspond to the 7-segment LED display inputs shown in Figure 7. 5 H a v e r
For the write enable, write up, and read up inputs, de-bounced switches were constructed using a single-pole double-throw (SPDT) switch and a set-reset latch. The latches were implemented using quad NAND integrated circuits, shown in Figure 6. Figure 6: Pin configuration and logic diagram for 7400 NAND integrated circuit Figure 7: Wiring diagram and hex character key for 7-segment display Figures 8, 9, and 10 show the results of the functionality testing described in Step 5 of the procedure. The circuit was evaluated using an Intronix LogicPort logic analyzer. LogicPort sampling was configured in a state mode, using a single acquisition and immediate trigger. 6 H a v e r
Figure 8: Write values 7 and 9 to registers 1 and 2 First, the D-input was set to a decimal value of 7, and the write register count set to 1. When write enable was set low, the value 7 was written to register 1. The D-input was then set to 9, and the register count set to 2. Again, write enable was set low, and the value 9 was written to register 2. This can be seen in the LogicPort display shown in Figure 8. Figure 9: Write values 10 (A) and 3 to registers 3 and 0 The D-input was then set to 10, denoted as hexadecimal character A in Figure 9. Register count was set to 3, write enable was set low, and the value 10 was written to register 3. Lastly, the D-input was set to 3, and the register count set to 0. The write enable was set low, and the value 3 was written to register 0. This can be seen in the LogicPort display shown in Figure 9. 7 H a v e r
Figure 10: Read values from registers 0, 1, 2, and 3 The final step in verifying circuit functionality was reading values from each of the four registers. As can be seen in Figure 10, the read up input was triggered three times, cycling through each of the registers. First, a 7 was read from register 1. The read up was triggered, and a 9 was read from register 2. The read up was triggered again, and a 10 (hexadecimal character A ) was read from register 3. Lastly, read up was triggered once more, and a 3 was read from register 0. This read/write sequence confirmed that the circuit functioned properly. CONCLUSION The purpose of this lab was to construct a 4-bit by 4 address register file. The design allowed a user to input a 4-bit value, write the value to one of four registers, and read a value from any register. This lab served as a small-scale demonstration of the way in which a computer reads and writes values to various addresses in a register file. In Lab 12, an arithmetic logic circuit will be added to the 4x4 register circuit, allowing a user to read a value, perform an arithmetic operation, and write the result back to a register. REFERENCES Dr. Alex Jones s laboratory instructions ECE/COE 0501 Lab Manual Data sheets for 74670, 74193, 74247, and 7400 integrated circuits 7-Segment LED display wiring diagram Lab Partner: Jenn Gingerich 8 H a v e r