Question Bank Unit 1 Digital Principles, Digital Logic 1. Using Karnaugh Map,simplify the following boolean expression and give the implementation of the same using i)nand gates only(sop) ii) NOR gates only (POS ) a. F(w,x,y,z)= m(0,1,2,4,5,12,14)+dc(8,10) F(w,x,y,z)= m(0,1,2,4,5,12,14)+dc(8,10) (Dec 13/ Jan14) 8 Marks 2. Explain Duality Theorem? (Dec 13/ Jan14) 4 Marks 3. What are Universal gates? Implement the basic gates using Universal gates only. (Dec 12/Jan 13) (Dec 13/ Jan14) 8 Marks 4. Name universal gates. Realize basic gates using NAND Gates. (July 13) 10 Marks 5. Explain positive and negative logic (July 13) 10 Marks 6. Explain different models for writing Verilog modules. Give an example for each. (Dec 12/Jan 13) 12 Marks 7. Define Logic. Explain different types of logic. ( July 12) 10 Marks 8. Differentiate between Analog and Digital Signals. ( July 12) 10 Marks 9. Using Karnaugh Map,simplify the following boolean expression and give the implementation of the same using i)nand gates only(sop) ii) NOR gates only (POS ) a. F(w,x,y,z)= m(0,1,2,4,5,12,14)+dc(8,10) F(w,x,y,z)= m(0,1,2,4,5,12,14)+dc(8,10) (Dec 11 / Jan 12) 10 Marks 10. Mention the Universal gates? Implement with respect to the basic gates. (Dec 11 / Jan 12) 10 Marks Dept. of CSE, SJBIT Page 1
Unit-2 Combinational Logic Circuits 1. Implement the following SOP function F = XZ + Y Z + X YZ Compare TTL and CMOS families and the integration level of ICs (Dec 13/ Jan14) 10 Marks 2. Prove that ABC + ABC' + AB'C + A'BC = AB + AC + BC. (Dec 13/ Jan14) 10 Marks 3. Find the prime implicant with the help of Qunie-Mc Clusky Method. F(W,X,Y,Z) = m(1,3,6,7,8,9,10,12,13,14) (Dec 12/Jan 13)(July 13) 10 Marks 4. Define impliant. Explain prime and essential prime implicants with example. (July 13)10 Marks 5. Simplify the following expression using Quine-Mc Clusky Method ( Dec 12/Jan 13) 10 Marks 6. What is a karnaugh map? State the limitations of karnaugh map. (July 12) 10 Marks 7. Prove that ABC + ABC' + AB'C + A'BC = AB + AC + BC. (July 12) 10 Marks 8. Does circuit in below figure experience hazard? If so, verify the same with timing diagram Explain the significance of Demorgan s theorem (Dec 11 / Jan 12) 10 Marks Unit 3 Data-Processing Circuits 1. Show that using a 3-to-8 decoder and multi input OR gate. The following Boolean expression can be realized.f1(a,b,c) = Σm(1,2,4,5), F2(A,B,C) = Σm(1,5,7) 2. Implementation of F(A,B,C,D)= (m(1,3,5,7,8,10,12,13,14), d( 4,6,15)) By using a 16- to-1 multiplexer. 3. Design 16 to 1 multiplexer using two 8 to 1 multiplexer and one 2 to 1 multiplexer. (July 13) 6 Marks. Dept. of CSE, SJBIT Page 2
4. Explain n bit magnitude comparator (July 13) 8 Marks. 5. Design 7 segment decoder using PLA (July 13) 6 Marks 6. Implement 4:1 mux using 2:1 mux (Dec 12 /Jan 13) 10 Marks 7. What is a Multiplexer. Design a 4:1 multiplexer using gate. (Dec 12 /Jan 13) 10 Marks 8. Explain the 8 word X 4 bit ROM with the help of block diagram. (July 12) 8 Marks 9. Explain the Implementation of Full adder using PLA (July 12) 6 Marks 10. Differentiate between PROM, PAL, PLA (July 12) 8 Marks 11. Implement 16:1 Mux using 4:1 (Dec 11 / Jan 12) 10 Marks. 12. Implement 4:16 decoder using 2:4 decoders (Dec 11 / Jan 12) 10 Marks Unit 4 Clocks, Flip-Flops 1. With the help of block diagram, explain the working of a JK Master-Slave flip flop. 2. Differentiate between combinational circuit and sequential circuit. 3. Explain Schmitt trigger (July 13) 6 Marks 4. Give transition diagram of JK and T Flip flops. (July 13) 8 Marks 5. Show how a D flip flop converted into JK flipflop (July 13) 6 Marks 6. Show how SR flip flop can be converted to a JK flip flop. (Dec 12 /Jan 13) 10 Marks 7. Write HDL design of D-Flip flop (Dec 12 /Jan 13) 10 Marks 8. With the help of a neat diagram explain the working of a Master Slave JK flip flop (July 12) 10 Marks 9. What do you mean by characteristic equation of a flip-flop? Derive characteristic equation for SR flip flop (July 12) 10 Marks 10. Write HDL design for JK flip-flop (Dec 11/Jan 12) 10 Marks 11. Implement T flip flop using JK flipflop (Dec 12 /Jan 12) 10 Marks Dept. of CSE, SJBIT Page 3
Unit-5 Registers 1. Explain a 4 bit universal shift register in detail and give its timing diagram. 2. With neat timing diagram, explain the working of a 4-bit SISO register. 3. Design a 3 bit PISO(DFlip flop) (July 13)6 marks 4. Design two 4 bit serial adder. (July 13) 6marks 5. Design a 4 bit Johnson counter with sate table. (July 13)8 marks 6. Explain Johnson Counter with neat diagram and timing diagram (Dec12 / Jan 13) 10 Marks 7. Write verilog code for Shift Register. (July12) 10 Marks 8. Give applications of J-K flip-flops. (July12) 10 Marks 9. Draw the general block diagram of multivibrator. (Dec11 / Jan 12) 10 Marks Unit-6 Counters 1. Design a 3 bit synchronous counter with the help of D flip flop. 2. Design Mod 4 ring counter. 3. Design a synchronous mod 6 up counter using JKflip flop. (July 13 ) 10 Marks. 4. Explain Digital clock with block Diagram. (July 13) 10 Marks 5. Design Mod 8 Johnson Counter. (Dec12 / Jan 13) 10 Marks 6. Difference between Asynchronous and Synchronous Counter. (Dec12 / Jan 13) 10 Marks 7. Draw logic circuit diagram for 3-bit synchronous up-down counter with clear input, start input and done output. The counter should produce done output after completion of counter in either direction. (July 2012.) 10 Marks 8. Draw the logic circuits and the excitation tables for the T, JK flip-flops. (Dec11 / Jan 12) 10 Marks Dept. of CSE, SJBIT Page 4
9. What is the difference between level and edge triggering? Explain the working of master slave J-K flip flop. (Dec11 / Jan 12) 10 Marks. Unit-7 Design of Synchronous and Asynchronous Sequential Circuits 1.Difference between Mealy Model and Moore Model of Synchronous Sequential Circuit. 2.Explain about all the notation of state machine. (July 13 ) 10 Marks. 3. Analyses the following circuit. (July 13 ) 10 Marks. 4. For the given state diagram, draw the state reduction diagram. (Dec12 / Jan 13) 10 Marks 5. Difference between Circuit. Mealy Model and Moore Model of Synchronous Sequential (July 12) 10 Marks Dept. of CSE, SJBIT Page 5
6. Analyses the following circuit. (Dec11 / Jan 12) 10 Marks. Unit -8 D/A Conversion and A/D Conversion 1. Give performance parameters of DAC or D/A converters. 2. An 4 bit DIA converter has an output range of 0 to 1.5 V. Define its resolution. 3. Explain with logic diagram 3 bit simultaneous A/D converters. (July 13) 10 Marks 4. Explain with logic diagram Single-slope A/D converters ( July 13) 10 Marks 5. Comment on the parameters which serve to describe the quality of performance of a D/A converter. (Dec12 / Jan 13) 10 Marks 6. With the help of a neat diagram explain parallel A/D converter. (Dec12 / Jan 13) 10 Marks 7. Explain the operation of successive approximation type of ADC (July 12 ) 10 Marks 8. An 8-bit successive approximation converter (SAC) has a resolution of 15 mv What will its, digital output be for an analog input of 2.65 V? (July 12 ) 10 Marks 9. Define linearity, settling time, sensitivity and accuracy of A/D and D/A converters. (Dec11 / Jan 12) 8 Marks 10. Write note on the following Binary ladder D/A. converter. 11. Explain the operation of dual-slope A/D converter. (Dec12 / Jan 13) 6 Marks (Dec12 / Jan 13) 8 Marks Dept. of CSE, SJBIT Page 6
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