Lecture 7: Sequential Networks

Similar documents
(CSC-3501) Lecture 7 (07 Feb 2008) Seung-Jong Park (Jay) CSC S.J. Park. Announcement

Sequential Logic Circuits

Latches, Flip-Flops, and Registers. Dr. Ouiem Bchir

Digital Logic Design Sequential Circuits. Dr. Basem ElHalawany

Lecture 8: Sequential Logic

Chapter 11 Latches and Flip-Flops

Clocks. Sequential Logic. A clock is a free-running signal with a cycle time.

CSE Latches and Flip-flops Dr. Izadi. NOR gate property: A B Z Cross coupled NOR gates: S M S R Q M

Sequential Circuits: Latches & Flip-Flops

Sequential Design Basics

A clock is a free-running signal with a cycle time. A clock may be either high or low, and alternates between the two states.

YEDITEPE UNIVERSITY DEPARTMENT OF COMPUTER ENGINEERING. EXPERIMENT VIII: FLIP-FLOPS, COUNTERS 2014 Fall

ENGR 303 Introduction to Logic Design Lecture 10. Dr. Chuck Brown Engineering and Computer Information Science Folsom Lake College

EMT 125 Digital Electronic Principles I CHAPTER 6 : FLIP-FLOP

Flip-Flops and Sequential Circuit Design

Engr354: Digital Logic Circuits

Experiment 8 Introduction to Latches and Flip-Flops and registers

Chapter 6. Flip-Flops and Simple Flip-Flop Applications

MUX AND FLIPFLOPS/LATCHES

Chapter. Synchronous Sequential Circuits

Unit 9 Latches and Flip-Flops. Dept. of Electrical and Computer Eng., NCTU 1

DIGITAL CIRCUIT LOGIC UNIT 11: SEQUENTIAL CIRCUITS (LATCHES AND FLIP-FLOPS)

COE 202: Digital Logic Design Sequential Circuits Part 1. Dr. Ahmad Almulhem ahmadsm AT kfupm Phone: Office:

CSE115: Digital Design Lecture 23: Latches & Flip-Flops

ECE 341. Lecture # 2

Combinational / Sequential Logic

DIGITAL SYSTEM FUNDAMENTALS (ECE421) DIGITAL ELECTRONICS FUNDAMENTAL (ECE422) LATCHES and FLIP-FLOPS

Flip-Flops. Because of this the state of the latch may keep changing in circuits with feedback as long as the clock pulse remains active.

ELCT201: DIGITAL LOGIC DESIGN

DIGITAL CIRCUIT COMBINATORIAL LOGIC

Chapter. Sequential Circuits

Switching Circuits & Logic Design

2 Sequential Circuits

Spring 2017 EE 3613: Computer Organization Chapter 5: The Processor: Datapath & Control - 1

EEC 118 Lecture #9: Sequential Logic. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

CH 11 Latches and Flip-Flops

Rangkaian Sekuensial. Flip-flop

LATCHES & FLIP-FLOP. Chapter 7

CHAPTER 11 LATCHES AND FLIP-FLOPS

Final Exam review: chapter 4 and 5. Supplement 3 and 4

Introduction to Sequential Circuits

Multiplexor (aka MUX) An example, yet VERY useful circuit!

Other Flip-Flops. Lecture 27 1

CHAPTER 4: Logic Circuits

CS 261 Fall Mike Lam, Professor. Sequential Circuits

AIM: To study and verify the truth table of logic gates

Chapter 1: Switching Algebra Chapter 2: Logical Levels, Timing & Delays. Introduction to latches Chapter 9: Binary Arithmetic

CHAPTER 4: Logic Circuits

CSE140: Components and Design Techniques for Digital Systems. More D-Flip-Flops. Tajana Simunic Rosing. Sources: TSR, Katz, Boriello & Vahid

Logic and Computer Design Fundamentals. Chapter 7. Registers and Counters

Sequential Digital Design. Laboratory Manual. Experiment #3. Flip Flop Storage Elements

Review of Flip-Flop. Divya Aggarwal. Student, Department of Physics and Astro-Physics, University of Delhi, New Delhi. their state.

Logic Design. Flip Flops, Registers and Counters

Sequential Logic. E&CE 223 Digital Circuits and Systems (A. Kennings) Page 1

Introduction to Microprocessor & Digital Logic

Department of Electrical and Computer Engineering Mid-Term Examination Winter 2012

Digital Logic Design I

Chapter 5 Synchronous Sequential Logic

Synchronous Sequential Logic. Chapter 5

CMSC 313 Preview Slides

CMOS Latches and Flip-Flops

INTRODUCTION TO SEQUENTIAL CIRCUITS

Chapter 8 Sequential Circuits

To design a sequential logic circuit using D-Flip-flop. To implement the designed circuit.

Digital Circuit And Logic Design I. Lecture 8

Digital Circuit And Logic Design I

Introduction. NAND Gate Latch. Digital Logic Design 1 FLIP-FLOP. Digital Logic Design 1

D Latch (Transparent Latch)

Digital Logic & Computer Design CS Professor Dan Moldovan Spring Chapter 3 :: Sequential Logic Design

COSC 243. Sequential Logic. COSC 243 (Computer Architecture) Lecture 5 - Sequential Logic 1

Synchronous Sequential Logic

Sequential Circuits. Output depends only and immediately on the inputs Have no memory (dependence on past values of the inputs)

Chapter 5 Sequential Circuits

LAB #4 SEQUENTIAL LOGIC CIRCUIT

Digital Design, Kyung Hee Univ. Chapter 5. Synchronous Sequential Logic

Memory elements. Topics. Memory element terminology. Variations in memory elements. Clock terminology. Memory element parameters. clock.

6. Sequential Logic Flip-Flops

ELE2120 Digital Circuits and Systems. Tutorial Note 7

Combinational vs Sequential

Unit 11. Latches and Flip-Flops

EE292: Fundamentals of ECE

Advanced Digital Logic Design EECS 303

CHAPTER1: Digital Logic Circuits

Course Administration

Sequential Logic and Clocked Circuits

Chapter 6 Digital Circuit 6-5 Department of Mechanical Engineering

ELCT201: DIGITAL LOGIC DESIGN

10.1 Sequential logic circuits are a type of logic circuit where the output of the circuit depends not only on

L4: Sequential Building Blocks (Flip-flops, Latches and Registers)

ESE 570 STATIC SEQUENTIAL CMOS LOGIC CELLS. Kenneth R. Laker, University of Pennsylvania, updated 25Mar15

Chapter 5: Synchronous Sequential Logic

Name Of The Experiment: Sequential circuit design Latch, Flip-flop and Registers

Topic 8. Sequential Circuits 1

Digital Integrated Circuits EECS 312

cascading flip-flops for proper operation clock skew Hardware description languages and sequential logic

Switching Circuits & Logic Design

RS flip-flop using NOR gate

NH 67, Karur Trichy Highways, Puliyur C.F, Karur District UNIT-III SEQUENTIAL CIRCUITS

Part 4: Introduction to Sequential Logic. Basic Sequential structure. Positive-edge-triggered D flip-flop. Flip-flops classified by inputs

Last time, we saw how latches can be used as memory in a circuit

Transcription:

Lecture 7: Sequential Networks CSE 14: Components and Design Techniques for Digital Systems Spring 214 CK Cheng, Diba Mirza Dept. of Computer Science and Engineering University of California, San Diego 1

Sequential Networks Memory Components Hierarchy of Memory Basic Mechanism of Memory Types of Flip-Flops Implementation Finite State Machine 2

Part II. Sequential Networks (Ch. 3) Memory / Time steps x i s i y i Clock Memory: Flip flops Specification: Finite State Machines Implementation: Excitation Tables y i =f i (S t,x) s i t+1 =g i (S t,x) 3

What is a sequential circuit? A circuit whose output depends on current inputs and past outputs A circuit with memory 4

Why do we need circuits with memory? A. Complex systems often consist of circuits that perform a sequence of tasks B. Circuits with memory can be used to store data C. Both A and B 5

The connection between sequences and memory What differentiates a musical piece from a cacophony? What is the role of memory in playing a musical piece (essentially a sequence of notes)? 6

Sequential Network vs. Combinational Logic: : Which of the following is FALSE? A. Combinational logic can replace any sequential network to realize the same function. B. Sequential networks use the same set of logic gates as combinational logic. C. Sequential networks can implement a CPU. D. Sequential networks require a precise clock for timing. 7

Hierarchy of Memory Devices Memory Bank (Farms of memory cells) Register (Vector of memory cells) Flip-Flop (Single memory cell) SR, D, T, JK flip-flops (Different types of memory cells) State Tables (Truth table of sequential machine) Characteristic Expressions (Switching algebraic expression of sequential machine) 8

Fundamental Memory Mechanism I2 I1 I1 I2 9

Memory Mechanism: Capacitive Load Fundamental building block of sequential circuits Two outputs:, There is a feedback loop! In a typical combinational logic, there is no feedback loop. No inputs I2 I1 I1 I2 1

Capacitive Loads Consider the two possible cases: = : then = 1 and = (consistent) 1 I1 I2 1 = 1: then = and = 1 (consistent) I1 1 1 I2 Bistable circuit stores 1 bit of state in the state variable, (or ) But there are no inputs to control the state 11

iclicker. Given a memory component made out of a loop of inverters, the number of inverters has to be A. Even B. Odd 12

SR (Set/Reset) Latch SR Latch R N1 S N2 Consider the four possible cases: S = 1, R = S =, R = 1 S =, R = S = 1, R = 1 13

SR Latch Analysis S = 1, R = : R N1 S 1 N2 S =, R = 1: R 1 N1 S N2 14

SR Latch Analysis S = 1, R = : then = 1 and = R N1 S 1 N2 S =, R = 1: then = and = 1 R 1 N1 S N2 15

SR Latch Analysis S = 1, R = 1: R 1 N1 S 1 N2 16

SR Latch Analysis S =, R = : R N1 S N2 17

SR Latch Analysis S =, R = : then = prev prev = prev = 1 R N1 R N1 S N2 S N2 S = 1, R = 1: then = and = R 1 N1 S 1 N2 18

S y y = (S+) R = (R+y) 19

Flip-flop Components SR F-F (Set-Reset) S R y Inputs: S, R State: (, y) 2

Id (t) y(t) S R (t 1 ) y(t 1 ) (t 2 )y(t 2 ) (t 3 ) y(t 3 ) 1 1 1 1 1 1 1 1 1 2 1 1 1 1 3 1 1 4 1 1 1 1 5 1 1 1 1 1 6 1 1 1 1 7 1 1 1 8 1 1 1 1 9 1 1 1 1 1 1 1 1 1 1 11 1 1 1 12 1 1 1 1 13 1 1 1 1 1 14 1 1 1 1 1 15 1 1 1 1 1 1 1 1 11 SR 11 State y State Diagram 11 11 1 Transition 1 1 1 1 11 1 SR 21

CASES: SR=1, (,y) = (,1) SR=1, (,y) = (1,) SR=11, (,y) = (,) SR = => if (,y) = (,) or (1,1), the output keeps changing. To avoid the SR latch output from toggling or behaving in an undefined way which input combinations should be avoided: A. (S, R) = (, ) B. (S, R) = (1, 1) 22

SR Latch Analysis S =, R = : then = prev and = prev (memory!) prev = prev = 1 R 1 N1 R N1 1 S N2 1 S 1 N2 S = 1, R = 1: then = and = (invalid state: NOT ) 1 R N1 S 1 N2 23

CASES: SR=1, (,y) = (,1) SR=1, (,y) = (1,) SR=11, (,y) = (,) SR = => if (,y) = (,) or (1,1), the output keeps changing Solutions: 1) SR = (,), or 2) SR = (1,1). inputs PS (t) State table SR 1 1 11 1-1 1 1 - Characteristic Expression (t+1) = S(t)+R (t)(t) (t+1) NS (next state) 24

SR Latch Symbol SR stands for Set/Reset Latch Stores one bit of state () Control what value is being stored with S, R inputs Set: Make the output 1 (S = 1, R =, = 1) Reset: Make the output (S =, R = 1, = ) Must do something to avoid invalid state (when S = R = 1) SR Latch Symbol R S 25

D Latch Two inputs:, D : controls when the output changes D (the data input): controls what the output changes to Function When = 1, D passes through to (the latch is transparent) When =, holds its previous value (the latch is opaque) Avoids invalid case when NOT D Latch Symbol D 26

D Latch Internal Circuit SR Latch Symbol R S D 27

D Latch Internal Circuit D D R S R S D D X 1 1 1 D S R 28

D Latch Internal Circuit D R R D D S S D X 1 1 1 D X 1 S R prev 1 1 1 1 prev 29

D Flip-Flop Two inputs:, D Function The flip-flop samples D on the rising edge of When rises from to 1, D passes through to Otherwise, holds its previous value changes only on the rising edge of A flip-flop is called an edge-triggered device because it is activated on the clock edge D D Flip-Flop Symbols 3

D Flip-Flop Internal Circuit D D N1 D L1 L2 31

D Flip-Flop Internal Circuit Two back-to-back latches (L1 and L2) controlled by complementary clocks When = L1 is transparent, L2 is opaque D passes through to N1 When = 1 L2 is transparent, L1 is opaque N1 passes through to D D L1 Thus, on the edge of the clock (when rises from 1) D passes through to N1 D L2 32

D Flip-Flop vs. D Latch D D D (latch) (flop) 33

D Flip-Flop vs. D Latch D D D (latch) (flop) 34

Latch and Flip-flop (two latches) A latch can be considered as a door =, door is shut = 1, door is unlocked A flip-flop is a two door entrance = 1 = = 1 35

D Flip-Flop (Delay) D D D L1 N1 D L2 Id D (t) (t+1) 1 1 2 1 1 3 1 1 1 State table PS D 1 1 1 1 NS= (t+1) Characteristic Expression: (t+1) = D(t) 36

iclicker Can D flip-flip serve as a memory component? A. Yes B. No 37

JK F-F J K State table PS JK 1 1 11 1? 1 1 1? (t+1) 38

JK F-F J K State table PS JK 1 1 11 1 1 1 1 1 (t+1) Characteristic Expression (t+1) = (t)k (t)+ (t)j(t) 39

T Flip-Flop (Toggle) T State table PS T 1 1 1 1 (t+1) Characteristic Expression (t+1) = (t)t(t) + (t)t (t) 4

Using a JK F-F to implement a D and T F-F x J K iclicker What is the function of the above circuit? A. D F-F B. T F-F C. None of the above 41

Using a JK F-F to implement a D and T F-F T J K T flip flop 42

Reading [Harris] Chapter 3: 3.3, 3.4.1, 3.4.2 43

2024 © artsdocbox.com Privacy Policy | Terms of Service | Feedback