Synchronous igital Logic Systems Review of igital Logic Prof. Stephen. Edwards Raw materials: MOS transistors and wires on Is Wires are excellent conveyors of voltage Little leakage Fast, but not instantaneous propagation Many orders of magnitude more conductive than glass MOS transistors are reasonable switches Finite, mostly-predictable switching times Nonlinear transfer characteristics Voltage gain is in the 100s Philosophy Have to deal with unpredictable voltages and unpredictable delays ombinational Logic igital: discretize values to avoid voltage noise Only use two values Voltages near these two are snapped to remove noise Synchronous: discretize time to avoid time noise Use a global, periodic clock Values that become valid before the clock are ignored until the clock arrives ombinational Logic oolean Logic Gates Full dder Typical example of building a more complex function Inverter Y 0 1 1 0 N Y 01 0 10 0 11 1 OR Y 01 1 10 1 11 1 XOR Y 01 1 10 1 11 0 in out S 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 in S out 1
Most asic omputational Model Every gate is continuously looking at its inputs and instantaneously setting its outputs accordingly Values are communicated instantly from gate outputs to inputs ll three switch at exactly the same time elays Real implementations are not quite so perfect omputation actually takes some time ommunication actually takes some time elays elays are often partially unpredictable Usually modeled with a minimum and maximum usses Wires sometimes used as shared communication medium Think party-line telephone us drivers may elect to set the value on a wire or let some other driver set that value Electrically disastrous if two drivers fight over the value on the bus Implementing usses asic trick is to use a tri-state driver ata input and output enable OE Q Shared bus When driver wants to send values on the bus, OE = 1 and contains the data When driver wants to listen and let some other driver set the value, OE = 0 and Q returns the value Four-Valued Simulation Wires in digital logic often modeled with four values 0, 1, X, Z X represents an unknown state State of a latch or flip-flop when circuit powers up Result of two gates trying to drive wire to 0 and 1 simultaneously Output of flip-flop when setup or hold time violated Output of a gate reading an X or Z Z represents an undriven state Value on a shared bus when no driver is outputenabled 2
Sequential Logic Sequential Logic and Timing Simply computing functions usually not enough Want more time-varying behavior ommon model: combinational logic with stateholding elements Inputs ombinational logic Outputs lock Input State-holding elements State Machines ommon use of state-holding elements Idea: machine may go to a new state in each cycle Output and next state dependent on present state E.g., a four-counter / 0 / 1 / 1 / 0 / 2 / 3 / 3 / 2 Latches & Flip-Flops Two common types of state-holding elements Latch Level-sensitive Transparent when clock is high Holds last value when clock is low heap to implement Somewhat unwieldy to design with Flip-flop Edge-sensitive lways holds value New value sampled when clock transitions from 0 to 1 More costly to implement Much easier to design with Latches & Flip-Flops Timing diagrams for the two common types: Q Latch lk lk RMs nother type of state-holding element ddressable memory Good for storing data like a von Neumann program ata In ata Out ddress Flip- Flop Q Read Write 3
RMs Write cycle Present ddress, data to be written Raise and lower write input Read cycle Present ddress Raise read ontents of address appears on data out ata In ddress Read Write ata Out Setup & Hold Times Flip-flops and latches have two types of timing requirements: Setup time input must be stable some time before the clock arrives Hold time input must remain stable some time after the clock has arrived Setup & Hold Times For a flip-flop (edge-sensitive) Synchronous System Timing udgeting time in a typical synchronous design Setup time: must not change here Hold time: must not change here lock period lk lock skew lk to delay Slowest logical path Setup Time lock skew Typical System rchitecture igital Systems Most large digital systems consist of atapath rithmetic units (adders, multipliers) ata-steering (multiplexers) Memory Places to store data across clock cycles Memories, register files, etc. ontrol Interacting finite state machines irect how the data moves through the datapath 4
Typical System rchitecture Implementing igital Logic Primitive datapath plus controller ontroller Operation Result Latch Latch ddr. Registers Reg. Shared us Memory Read/Write iscrete logic chips NN gates four to a chip and wire them up (e.g., TTL) Programmable Logic rrays (PLs) Program a chip containing Ns feeding big OR gates Field-Programmable Gate rrays (FPGs) Program lookup tables and wiring routes pplication-specific Integrated ircuit (SIs) Feed a logic netlist to a synthesis system Generate masks and hire someone to build the chip Full-custom esign raw every single wire and transistor yourself Hire someone to fabricate the chip or be Intel Implementing igital Logic iscrete logic is dead Too many chips needed compared to other solutions PLs Nice predicable timing, but small and limited FPGs High levels of integration, very convenient Higher power and per-unit cost than SIs and custom SIs Very high levels of integration, costly to design Low power, low per-unit cost, but huge initial cost Full ustom Only cost-effective for very high-volume parts E.g., Intel microprocessors igital Logic in Embedded Systems Low-volume products (1000s or less) typically use FPGs High-volume products usually use SIs Non-custom logic usually implemented using application-specific standard parts hipsets Graphics controllers PI bus controllers US controllers Ethernet interfaces 5