Chapter 6. sequential logic design This is the beginning of the second part of this course, sequential logic. 1
equential logic equential circuits simple circuits with feedback latches edge-triggered flip-flops Timing methodologies cascading flip-flops for proper operation clock skew Asynchronous inputs metastability and synchronization Basic registers shift registers simple counters Hardware description languages and sequential logic Again, sequential logic circuits are quite different from combinational logic. In general, sequential systems are more difficult to design. We will discuss some basic issues in the sequential logic systems in this chapter. 2
equential logic circuits (LCs) Circuits with feedback outputs = f(inputs, past inputs, past outputs) basis for building "memory" into logic circuits door combination lock is an example of a sequential circuit state is memory state is an "output" and an "input" to combinational logic combination storage elements are also memory value comparator C1 C2 C3 multiplexer mux control new equal comb. logic state reset clock equal open/closed In most sequential logic circuits (LCs), there are storage parts or memory elements. Recall that in the door lock system, three numbers should be stored and compared. What is the key element here? 3
Circuits with feedback How to control feedback? what stops values from cycling around endlessly X1 X2 Xn switching network Z1 Z2 Zn One popular feature of LCs is to have a feedback loop from the outputs. In this slide, this diagram shows one output goes back to the input. Then how can we control the feedback mechanism by which Zn becomes Xn? That is, with this feedback, timing is even more important. We will discuss this issue from now on. 4
implest circuits with feedback Two inverters form a static memory cell will hold value as long as it has power applied "1" "0" "stored value" How to get a new value into the memory cell? selectively break feedback path load new value into cell "remember" "data" "load" "stored value" Let s consider a simple memory element first. What if we place two inverters before a stored value and suppose the stored value is 1. Note that there is a feedback from the stored value to the first inverter. Another more sophisticated option is to have a selection function between a stored value and a new value. If load is enabled, the new data will be put into the stored value. 5
Memory with cross-coupled gates Cross-coupled NOR gates similar to inverter pair, with capability to force output to 0 (reset=1) or 1 (set=1) R ' R' Cross-coupled NAND gates similar to inverter pair, with capability to force output to 0 (R =0) or 1 ( =0) Let s consider this feedback in the cases of cross-connectivity between other gate types. With Nor or Nand gates, we can have more control inputs. R and denote reset and set inputs, respectively. is the output value of interest and its inverse is denoted by. For a NOR gate, think of a case when a single input can determine the output of the gate. VI - equential Logic Copyright 2004, Gaetano Borriello and Randy H. Katz 6 uppose R is 1, which makes 0. Basically, we assume R and are opposite for update. ' ' R ' R' ' '
Timing behavior R ' Reset Hold et Reset et 100 Race R \ If R=1 and =0, is 0 and is 1 (recall the meaning of reset R). If R=0 and =1, is 1. What if R==0, then and will remain with the previous values. The problem happens when R==1. Are and just 0s? The more significant problem arises when R==1 and then R==0, which will yield an oscillation as follows. and will be 1 together. But then and should be changed to 0 again. Then this cycle continues. 7
tate behavior or R- latch Truth table of R- latch behavior R ' ' 0 1 ' 1 0 R 0 0 hold 0 1 0 1 0 1 1 1 unstable ' 0 0 This slide shows a state diagram. It describes how and will change as varying values of and R stimulate the system. That is, and R are inputs and and are outputs. A latch is a memory element that stores one bit. And this is called an R- latch. If is high, 1 will be stored into ; if R is high, 0 will be stored. Depending on the values of and, we can think of 4 states. 8 ' 1 1
R Theoretical R- latch behavior tate diagram ' states: possible values transitions: changes based on inputs R=00 R=01 ' 0 1 R=01 R=01 R=11 R=00 R=10 R=01 R=11 ' 0 0 R=10 R=00 R=11 R=11 ' 1 0 R=10 R=00 R=10 possible oscillation between states 00 and 11 ' 1 1 uppose the R- latch holds initially 01 ( ). As long as R is 01 or 00, the system will remain in the same state. If R=10, will be 1. When R is 11, the state will be 00 ( ). Then the problem happens when R becomes 00 from that state. 9
Observed R- latch behavior Very difficult to observe R- latch in the 1-1 state one of R or usually changes first Ambiguously returns to state 0-1 or 1-0 a so-called "race condition" or non-deterministic transition R=00 R=01 ' 0 1 R=01 R=10 R=01 R=10 ' 1 0 R R=00 R=10 ' R=00 R=11 R=11 ' 0 0 R=11 R=00 In real systems, when R changes from 11 to 00, normally both and R may not change at the exactly same time. Hence, R will be either 01 or 10 before changing from 11 into 00. o we cannot guess which will be changed first. In summary, we should not allow R to be 11. 10
R- latch analysis Break feedback path R (t) ' R (t+) R (t) (t+) 0 0 1 1 0 1 0 1 0 0 0 0 0 0 1 X 0 0 1 1 0 1 0 1 1 1 1 1 1 0 1 X hold reset set not allowed 0 0 1 0 X 1 X 1 characteristic equation (t+) = + R (t) To analyze the timing, let s assume the feedback loop is cut off. That is, consider (t) and (t+ ) separately. Here is the delay incurred by the latch. When you look at the truth table, you can notice something different. What is it? (t) R 11
Activity: R- latch using NAND gates * draw truth table and circuit, where R and should not be 1 together R ' (t) R R R (t) (t+) 0 0 1 1 0 0 0 0 1 1 1 1 0 1 1 0 0 0 0 1 1 0 1 0 1 0 0 1 0 1 1 0 0 1 1 1 1 1 0 0 0 X 1 1 0 0 1 X hold reset set not allowed (t) 0 0 1 0 R X 1 X 1 characteristic equation (t+) = + R (t) 12
Gated R- latch Control when R and inputs matter otherwise, the slightest glitch on R or while enable is low could cause change in value stored R' enable' ' R ' et 100 Reset ' R' enable' ' The next version is a gated R- latch. In the gated (level-sensitive) R- latch, the R- values are handled cautiously. When enable is low, then R and are always zeroes (there is no glitch or fluctuation in R and ). o R and are meaningful only when enable is high. This waveform shows when enable is high and is set (or is low), will 13 become true.
Clocks Used to keep time wait long enough for inputs (R' and ') to settle then allow to have effect on value stored Clocks are regular periodic signals period (time between ticks) duty-cycle (time clock is high between ticks - expressed as % of period) duty cycle (in this case, 50%) period A clock is an important element in sequential circuits. The enable signal in the previous slide serves as kind of a clock. Once enable is asserted, it should remain high until the input stimulates the output fully. Normally, a clock is periodically alternating between high and low. The beginning of each period is called a clock tick. And the duty cycle is defined as the ratio of High voltage interval to the period. 14
Clocks (cont d) Controlling an R- latch with a clock can't let R and change while clock is 0 (allowing R and to pass) only have half of clock period for signal changes to propagate signals (R, ) must be stable for the other half of clock period R R clock R and stable changing stable changing stable clock Let s control the gated (or level-sensitive) R- latch with a clock. While clock is 0, R and should sustain their values which will update and during that interval. While clock is high, R and can be changed to a new value (for next operation); in the meantime, and will not change since R and are 00. 15
Cascading latches Connect output of one latch to input of another How to stop changes from racing through chain? need to be able to control flow of data from one latch to the next move one latch per clock period have to worry about logic between latches (arrows) that is too fast R ' R R R clock What if we connect multiple latches in a series? In this case, the output of the first latch becomes the input for the second latch. For a single ON interval of the clock signal, we can assure that and if the first latch will be stabilized after update. But the concern is if signal propagation is too fast, even the second R- latch may be affected like a domino effect in the same ON interval. How can we make it sure that only the first latch is updated? 16
Master-slave structure Break flow by alternating clocks use positive clock to latch inputs into one R- latch use negative clock to change outputs with another R- latch View pair as one basic unit master-slave flip-flop twice as much logic output changes a few gate delays after the falling edge of clock but does not affect any cascaded flip-flops master stage slave stage R R P R P CLK The solution is to use different polarities of clock signals for a pair of R- latches. o it requires twice logic gates. Notice that there is an inverter between two clock signals. o when the clock is high, the master latch will be updated and when the clock is low, the VI - equential Logic Copyright 2004, Gaetano Borriello and Randy H. Katz 17 slave latch will be changed.
The 1s catching problem In first R- stage of master-slave FF R CLK P P 0-1-0 glitch on R or while clock is high is "caught" by master stage leads to constraints on logic to be hazard-free et Reset 1s catch CLK Master Outputs lave Outputs R master stage R P slave stage P R What would be the problem of the inverted clock signals for the pair of R- latches? While the clock is high, suppose there is a glitch is in the very first (0-1-0), P and P will change, which in turn will affect the slave latch when the clock becomes low. This is called the 1s catching problem. 18
D flip-flop Make and R complements of each other eliminates 1s catching problem can't just hold previous value (must have new value ready every clock period) value of D just before clock goes low is what is stored in flip-flop negative edge-triggered master stage R slave stage P R D P CLK 10 gates To eliminate the 1s catching problem, we have to make and R have opposite values; so we use the complementary values from the same input, which is called D flip-flop. D is an abbreviation for data. o R and can be either 01 and 10 only. Now we cannot use 00 to maintain the same value in the latch. How many gates here? Each R- latch has two NOR gates. 19
(Negative) Edge-triggered D flip-flops (FFs) More efficient solution: only 6 gates D sensitive to inputs only near edge of clock signal (not while high) D 0 holds D when clock goes low negative edge-triggered D flip-flop (D-FF) Clk=1 R 4-5 gate delays must respect setup and hold time constraints to successfully capture input 0 D D holds D when clock goes low characteristic equation (t+1) = D The other realization to solve the 1s catching problem is to use a clock edge to trigger the change of the flip-flop s value. While the clock is high, the second top NOR and the second bottom NOR gates will be 0, which keeps the old values of and 20
Negative Edge-triggered D flip-flops (cont d) tep-by-step analysis D D 1 D D 1 D 0 -> 0 D 0 R R Clk=0 Clk=0 D 0 -> 1 D 1 D 1 D when clock goes high-to-low data is latched 0 new D new D old D when clock is low data is held If clock goes from 1 to 0, initially and R are 0. Then, depending on D s value, or R will be changed, which in turn will set or reset. The numbers in blue shows the case when D is 1. After that, D s change makes no effect. E.g. new D is 0 now, D (second 21 0 D 0
How edge-triggered? D D D D R D 0 R D 1 Clk= Clk=0 D 0 D 1 D D new D D One of two gates is 1 Right after the clock goes from 1 to 0, the second top and second bottom NOR gates are open to the D input. As soon as the input is latched to the, either of these NOR gates will be 1, which blocks the new input from entering. 22
Edge-triggered D flip-flops (cont d) Positive edge-triggered inputs sampled on rising edge; outputs change after rising edge Negative edge-triggered flip-flops inputs sampled on falling edge; outputs change after falling edge 100 D CLK pos pos neg neg positive edge-triggered FF negative edge-triggered FF There are two kinds of flip-flops which are triggered by the two edges of the signals: rising edge and falling edge. The previous slide shows a negative edge-triggered FF. If we add an inverter to the clock, that FF is turned into a positive edge-triggered FF. Typically, latches are level triggered and simpler. FFs are mostly edge triggered and more complicated. 23
Timing methodologies Rules for interconnecting components and clocks guarantee proper operation of system when strictly followed Approach depends on building blocks used for memory elements we'll focus on systems with edge-triggered flip-flops found in programmable logic devices many custom integrated circuits focus on level-sensitive latches Basic rules for correct timing: (1) correct inputs, with respect to time, are provided to the flipflops (2) no flip-flop changes state more than once per clocking event As the same input can produce different outputs over time in sequential logic, timing is extremely important. Especially, memory elements like flip-flops should be handled with precise timing. o a clock determines when the circuit can change the current state to a new state. For each memory element, only one state transition is allowed in a single clock period. 24
Timing methodologies (cont d) Definition of terms clock: periodic event, causes state of memory element to change can be rising edge or falling edge or high level or low level input setup time: minimum time before the clocking event by which the input must be stable (Tsu) hold time: minimum time after the clocking event until which the input must remain stable (Th) T su T h data D D clock clock there is a timing "window" around the clocking event during which the input must remain stable and unchanged in order to be recognized data clock stable changing Let s go over terminologies first. We already know what is a clock. For each edge of a clock signal, there are some timing constraints. uppose the positive edge of a clock signal triggers a circuit. Then the data input should be stable for an interval which is Tsu+Th, which are dependent on transistor circuit delay. 25
Comparison of latches and flip-flops (FFs) D CLK positive edge-triggered flip-flop D CLK D C CLK edge latch transparent (level-sensitive) latch behavior is the same unless input changes while the clock is high Again, in FFs, the data value only at the rising edge (or falling edge) is critical (see blue dots). Meanwhile, most latches are sensitive to D value changes as long as the clock is high. Typically, the clock input of a FF is depicted by a triangle. 26
Comparison of latches and flip-flops (cont d) Type When inputs are sampled When output is valid unclocked always propagation delay from input change latch level-sensitive clock high propagation delay from input change latch (Tsu/Th around falling or clock edge (whichever is later) edge of clock) master-slave clock high propagation delay from falling edge flip-flop (Tsu/Th around falling of clock (P.17) edge of clock) negative clock hi-to-lo transition propagation delay from falling edge edge-triggered (Tsu/Th around falling of clock flip-flop edge of clock) In unclocked latches, a stored value will always be affected by data at any time. In levelsensitive latches, the D value affects the latch as long as the clock stays high. And the D value at the falling edge will be maintained while the clock is low. o around the falling edge, we should keep data stable for Tsu+Th. In a positive edge-triggered FF, the Tsu/Th for the rising clock edge should be guaranteed. 27
Typical timing specifications Positive edge-triggered D flip-flop setup and hold times minimum clock width (Tw) propagation delays (low to high, high to low, max and typical) D T su 1.8 ns T h 0.5 ns T su 1.8 ns T h 0.5 ns Clk T w 3.3 ns T w 3.3 ns T pd T 3.6 ns pd 1.1 ns 3.6 ns 1.1 ns all measurements are made from the clocking event (the rising edge of the clock) This slide illustrates the timing where the rising edge of the clock signal is the reference. Tpd is the propagation delay between the rising edge of the clock (event trigger) and the change in the output. Tw should be long enough to ensure that D will change 28
Cascading edge-triggered flip-flops hift register IN new value goes into first stage while previous value of first stage goes into second stage consider setup/hold/propagation delays (prop must be > hold) 0 1 D D OUT CLK IN 0 1 CLK 100 This slide shows the waveform of a two bit shift register made up of two cascaded positive edge triggered D FFs. A shift register refers to a circuit that moves a stored bit among storage elements. At the first positive edge, IN is 0, which will store 0 at 0. at the next clock tick, 0 will be propagated to 1 and 0 will be updated to the IN s value VI - equential Logic Copyright 2004, Gaetano Borriello and Randy H. Katz 29 at that moment. But we have to be careful about timing relationships among signals.
Cascading edge-triggered flip-flops (cont d) Why this works propagation delays (Tp or Tpd) exceed hold times (Th) clock width constraint exceeds setup time this guarantees following stage will latch current value before it changes to new value In 0 1 T su 1.8ns T p 1.1-3.6ns T su 1.8ns T p 1.1-3.6ns timing constraints guarantee proper operation of cascaded components CLK T period assumes infinitely fast distribution of the clock T h 0.5ns T h 0.5ns The first condition for the proper operation is Tp > Th. Otherwise, the changed 0 may also affect the second stage FF (i.e. changing 1 as well). Also, the interval between the successive clock rising edges, Tperiod > Tp+Tsu. Otherwise 0 is not ready to change VI - equential Logic Copyright 2004, Gaetano Borriello and Randy H. Katz 30 1.
Clock skew The problem correct behavior assumes next state of all storage elements determined by all storage elements at the same time this is difficult in high-performance systems because time for clock to arrive at flip-flop is comparable to delays through logic effect of skew on cascaded flip-flops: 100 In 0 1 CLK0 CLK1 CLK1 is a delayed version of CLK0 T skew original state: IN = 0, 0 = 1, 1 = 1 due to skew, next state becomes: 0 = 0, 1 = 0, and not 0 = 0, 1 = 1 The last headache in timing is about the distribution of the clock signal. o far, we assumed that clocks are arriving at the FFs simultaneously. But those clock signals travel along the wires just like the other data signals. o Tp > Tskew +Th (in case that Tskew > 0) and Tperiod + Tskew > Tp + Tsu (in case that Tskew < 0) 31
ummary of latches and flip-flops Development of D-FF level-sensitive used in custom integrated circuits can be made with 4 switches edge-triggered used in programmable logic devices good choice for data storage register Preset and clear inputs are highly desirable on flip-flops used at start-up or to reset system to a known state D-FFs can be either level-sensitive or edge-triggered. For maintenance purposes, preset and clear inputs are desirable for FFs, which will be discussed later. Preset inputs initialize the values in FFs. Clear inputs will reset the values of FFs to 0s. 32
Metastability and asynchronous inputs Clocked synchronous circuits inputs, state, and outputs sampled or changed in relation to a common reference signal (called the clock) e.g., master/slave, edge-triggered Asynchronous circuits inputs, state, and outputs sampled or changed independently of a common reference signal (glitches/hazards a major concern) e.g., R- latch Asynchronous inputs to synchronous circuits inputs can change at any time, will not meet setup/hold times dangerous, synchronous inputs are greatly preferred cannot be avoided (e.g., reset signal, memory wait, user input) If we use only synchronous circuits in the system, then we just need to consider clocks for stable system operations. However, some components are asynchronous in the sense that the values of these components are changing individually without any common reference signal (e.g. clock signal). One typical case happens when an asynch circuit meets a synch circuit. 33
ynchronization failure Occurs when FF input changes close to clock edge the FF may enter a metastable state neither a logic 0 nor 1 it may stay in this state an indefinite amount of time this is not likely in practice but has some probability logic 1 logic 0 logic 1 logic 0 small, but non-zero probability that the FF output will get stuck in an in-between state oscilloscope traces demonstrating synchronizer failure and eventual decay to steady state ometimes, Tsu or Th is not long enough for stable transitions. The output of a FF may enter a meta-stable state. Three cases take place depending on the energy for the duration (Tsu + Th) to make transitions. uppose was 0 and now D is 1 to store bit 1 into. VI - equential Logic Copyright 2004, Gaetano Borriello and Randy H. Katz 34
Dealing with synchronization failure Probability of failure can never be reduced to 0, but it can be reduced (1) slow down the system clock this gives the synchronizer more time to decay into a steady state; synchronizer failure becomes a big problem for very high speed systems (2) use fastest possible logic technology in the synchronizer this makes for a very sharp "peak" upon which to balance (3) cascade two synchronizers this effectively synchronizes twice (both would have to fail) asynchronous input D D synchronized input Clk synchronous system There are three ways to reduce the probability of synch. failure. The first option gives the logic circuit more time to go to either 0 or 1. The second approach is similar; it gives less room to stay at meta-stable state. In the third choice, by cascading two FFs, the probability VI - equential of Logic the synch failure Copyright is even 2004, more Gaetano Borriello reduced and Randy at the H. Katz cost of slow-down. 35
Handling asynchronous inputs Never allow asynchronous inputs to fan-out to more than one flip-flop synchronize as soon as possible and then treat as synchronous signal Async Input Clocked ynchronous ystem D 0 Async Input D ynchronizer D 0 Clock Clock D 1 D 1 Clock Clock When an asynch input makes rendezvous with a synch part, only one FF will be placed at the junction. On the left, depending on the wire length, an asynch input can arrive at different times at two D FFs, which may cause unexpected results. To solve this issue, place a single D FF as shown on the right; so the input will change only. 36
Handling asynchronous inputs (cont d) What can go wrong? In 0 1 CLK input changes too close to clock edge (violating setup time constraint) In is asynchronous and fans out to D0 and D1 one FF catches the signal, one does not inconsistent state may be reached! This slide shows waveforms of the dangerous circuit in the previous slide. As the asynch input arrives late at the lower D FF, the energy may not be high enough to make a transition at 1. In designing a system, we intended to make changes at both FFs from the input from the asynch circuit, but we fail to do so. 37
Registers Collections of flip-flops with similar controls and logic stored values somehow related (for example, form binary value) share clock, reset, and set lines similar logic at each stage Examples shift registers counters OUT1 OUT2 OUT3 OUT4 "0" R R R R D D D D CLK IN1 IN2 IN3 IN4 From now on, we will look at a collection of FFs. The first memory element to look at is a register. A register is normally defined as a group of FFs with coordinated controls or shared controls. Examples of controls are clock, reset, set and so on. In this case, we can read/write 4 bits in parallel. 38
hift register Holds samples of input store last 4 input values in sequence 4-bit shift register: OUT1 OUT2 OUT3 OUT4 IN D D D D CLK One of the relatively simple registers is a shift register. Here one bit is shifted (or moved to right) to the next FF at each clock tick (its positive edge). At each positive edge, the stored value will come out and move to the next element. 39
Universal shift register Holds 4 values left_in left_out clear s0 s1 serial or parallel inputs serial or parallel outputs permits shift left or right shift in new values from left or right output input right_out right_in clock clear sets the register contents and output to 0 s1 and s0 determine the shift function s0 s1 function 0 0 hold state 0 1 shift right 1 0 shift left 1 1 load new input The shift register in the previous slide goes only from left to right. Here we want to design a generic or multi-purpose shift register with the above functionalities. In addition, we also want to hold the current value without I/O. Overall, we need some control variables. 40
Design of universal shift register Consider one of the four flip-flops new value at next clock cycle: clear s0 s1 new value 1 0 0 0 0 output 0 0 1 output value of FF to left (shift right) 0 1 0 output value of FF to right (shift left) 0 1 1 input Nth cell to N-1th cell D to N+1th cell CLK CLK clear, s0, s1 [N-1] (left) 0 1 2 3 Input[N] CLEAR s0 and s1 control mux [N+1] (right) Each memory module (that stores 1 bit) should be able to perform 5 functions. Note that there are multiple incoming lines and one of them should be selected. This should ring the bell. It will be convenient to use a MUX. Blue wires are about control while black VI - equential Logic Copyright 2004, Gaetano Borriello and Randy H. Katz 41 wires are data paths. Here, clear, 1 and 0 are depicted by a single wire for simplicity.
hift register application Parallel-to-serial conversion for serial transmission parallel outputs parallel inputs serial transmission One of the popular application of the shift register is serial transmission, where information is transmitted over the medium bit-by-bit. 42
Pattern recognizer Combinational function of input samples in this case, recognizing the pattern 1001 on the single input signal OUT OUT1 OUT2 OUT3 OUT4 IN D D D D CLK Another useful application of shift registers is bit string identification. In this case, bits are shifted from left to right. At any moment, if 4 bits are 1001, then OUT will be true. 43
Counters equences through a fixed set of patterns in this case, 1000, 0100, 0010, 0001 if one of the patterns is its initial state (by loading or set/reset) OUT1 OUT2 OUT3 OUT4 IN D D D D CLK If there are multiple patterns that are used for state representation, this register is typically referred to as a counter. Look at the shift register in the slide. uppose there is a initialization (or preset) logic that stores 1000 in the register, which is not shown here. Then, as the clock ticks, the bits are rotating this ring. That s why it is called a ring counter. 44
Activity How does this counter work? (initial value: 1000) OUT1 OUT2 OUT3 OUT4 IN D D D D CLK Counts through the sequence: 1000, 1100, 1110, 1111, 0111, 0011, 0001, 0000 Known as Mobius (or Johnson) counter 45
Binary counter Logic between registers (not just multiplexer) XOR decides when bit should be toggled always for low-order bit, only when first bit is true for second bit, and so on CLK OUT1 OUT2 OUT3 OUT4 D D D D "1" Here is a binary counter; the rule of thumb is that if all lower bits are true, than the upper bit should be toggled. OUT4 is the MB while OUT1 is the LB. 46
Four-bit binary synchronous up-counter tandard component with many applications positive edge-triggered FFs w/ synchronous load and clear inputs parallel load data from D, C, B, A enable inputs: must be asserted to enable counting ripple-carry out (RCO) is used for cascading counters high when counter is in its highest state 1111 Preset implemented using an AND gate logic (2) RCO goes high (3) High order 4-bits are incremented EN D C B A LOAD CLK CLR RCO D C B A (1) Low order 4-bits = 1111 If we use the binary counter in the previous slide as a basic component, we can build many complicated circuits, e.g. a wider binary counter. Here D is the MB. 47
Offset counters tarting offset counters use of synchronous load e.g., 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1111, 0110,... Ending offset counter comparator for ending value e.g., 0000, 0001, 0010,..., 1100, 1101, 0000 Combinations of the above (start and stop value) "1" "0" "0" "0" "0" "1" "0" "1" "1" "0" "0" EN RCO D D C C B B A A LOAD CLK CLR EN RCO D D C C B B A A LOAD CLK CLR Other examples are here; using the load input, we can control the initial value. Or by using some product term from the stored values, we can configure the ending value of the counter. 48
HDLs and equential Logic Flip-flops representation of clocks - timing of state changes asynchronous vs. synchronous hift registers imple counters As a tidbit, we will see some Verilog programs (HDLs) for sequential logic circuits. Because of the characteristics of sequential logic systems, there are peculiar features. 49
Flip-flop in Verilog Use always block's sensitivity list to wait for clock edge module dff (clk, d, q); input clk, d; output q; reg q; always @(posedge clk) q = d; endmodule This is an HDL program for a positive-edge triggered D FF. Again, reg is the keyword to declare a variable whose value needs to be tracked or stored. On the other hand, wire indicates a value that is passing between gates. Here posedge means the positive edge or the rising edge of the clock signal. 50
More Flip-flops ynchronous/asynchronous reset/set single thread that waits for the clock three parallel threads only one of which waits for the clock ynchronous Asynchronous module dff (clk, s, r, d, q); input clk, s, r, d; output q; reg q; always @(posedge clk) if (r) q = 1'b0; else if (s) q = 1'b1; else q = d; endmodule module dff (clk, s, r, d, q); input clk, s, r, d; output q; reg q; always @(posedge r) q = 1'b0; always @(posedge s) q = 1'b1; always @(posedge clk) q = d; endmodule Here synchronous and asynchronous flip-flops are described. 1 b0 means that this signal is 1 bit wide and 0 will be stored. In synch case, the FF is triggered only by the positive edge of the clock. Meanwhile, the asynch FF has three triggering variables. 51
Verilog, constant syntax Number in bits, apostrophe, radix (base number), and number Radix: b, o, d, h Let me talk about how Verilog expresses the constant number here. By default, we use decimal numbers. If we want to use binary or hexadecimal number, we have to specify the radix. The number before the apostrophe is the number of bits for the constant. 52
Incorrect Flip-flop in Verilog Use always block's sensitivity list to wait for clock to change module dff (clk, d, q); input clk, d; output q; reg q; always @(clk) q = d; Not correct! will change whenever the clock changes, not just on an edge. endmodule If we don t specify the posedge at the clock signal, then the D s value will be transferred to not only at the positive edge but also at the negative edge of the clock, which is not intended by the Verilog programmer. 53
Blocking and Non-Blocking Assignments Blocking assignments (X=A) completes the assignment before continuing on to next statement Non-blocking assignments (X<=A) completes in zero time and doesn t change the value of the target until a blocking point (delay/wait) is encountered Example: swap always @(posedge CLK) begin temp = B; B = A; A = temp; end always @(posedge CLK) begin A <= B; B <= A; end There are two kinds of assignments. In Verilog, the assignment statements within an always block are executed sequentially, which is on the left. If we use <= assignment, the value change is taking place at the end of the always block. 54
Register-transfer-level (RTL) Assignment Non-blocking assignment is also known as an RTL assignment if used in an always block triggered by a clock edge all flip-flops change together // B,C,D all get the value of A always @(posedge clk) begin B = A; C = B; D = C; end // implements a shift register too always @(posedge clk) begin B <= A; C <= B; D <= C; end An useful usage of the non-blocking assignment is shift registers, where all the bits (or values) are transferred in parallel. On the left, the behavior for the shift register has some problem. 55
Mobius Counter in Verilog initial begin A = 1 b0; B = 1 b0; C = 1 b0; D = 1 b0; end always @(posedge clk) begin A <= ~D; B <= A; C <= B; D <= C; end Here is an HDL specification of a Mobius counter 56
Binary Counter in Verilog module binary_counter (clk, c8, c4, c2, c1); input clk; output c8, c4, c2, c1; reg [3:0] count; initial begin count = 0; end always @(posedge clk) begin count = count + 4 b0001; end assign c8 = count[3]; assign c4 = count[2]; assign c2 = count[1]; assign c1 = count[0]; endmodule module binary_counter (clk, c8, c4, c2, c1, rco); input clk; output c8, c4, c2, c1, rco; reg [3:0] count; reg rco; initial begin... end always @(posedge clk) begin... end assign c8 = count[3]; assign c4 = count[2]; assign c2 = count[1]; assign c1 = count[0]; assign rco = (count == 4 b1111); endmodule On the left, there is a Verilog description for a binary counter without rco; on the right, rco is also described. 57
equential logic summary Fundamental building block of circuits with state latch and flip-flop R- latch, R- master/slave, D master/slave, edge-triggered D flip-flop Timing methodologies use of clocks cascaded FFs work because propagation delays exceed hold times beware of clock skew Asynchronous inputs and their dangers synchronizer failure: what it is and how to minimize its impact Basic registers shift registers counters Hardware description languages and sequential logic 58