Chapter 5 Synchronous Sequential Logic Sequential Circuits Latches and Flip-Flops Analysis of Clocked Sequential Circuits HDL Optimization Design Procedure
Sequential Circuits Various definitions Combinational circuits with feedback Combinational circuits with memory Combinational circuits with state whatever...
Synchronous... If there are synchronous circuits, there must be asynchronous as well. We (and everybody else) deal mostly with synchronous. Synchronous circuits have a clock (it can take a few different forms)
Asynchronous circuits Depend on time delay devices for storage Can exhibit instabilities (due to effects like racing conditions) Hard to design Used mainly for special subcomponents
Synchronous Sequential Circuits They do not look much different other than: they have one special input called clock all flip-flops change state in response to the same clock
Latches The simplest kind of memory They are primitive flip-flops Flip-flops can contain one or more latches usually more Great for understanding flip-flops without having to know electronics
S-R Flip-Flop S-R stands for Set-Reset Just two NOR gates could use NAND as well The output depends not only on the input but the on the previous output as well!
Using NAND Everything is just the opposite Set and Reset are active low The illegal input is -
Latches with ENABLE The bare latch is what nightmares are made of We can add a control input Eventually this will be the clock
Is it perfect? It has an indeterminate next state What if the feedback propagates more than once This could lead to more indeterminacies It would require a very short clock pulse.
D Flip-Flop The D flip-flop has one input The D stands for Data or Delay With one input it is hard to have an illegal input
Graphic Symbols Flip-flops are drawn as rectangles The standard names (S, R, D, J, K, etc) are drawn inside. If it follows negative logic then the input has a negation circle.
Edge Triggered Flip-Flops A long clock pulse can create problems This is because the flip-flop is triggered by the level of the clock pulse How about if it is triggered by the transition of the clock pulse Such flip-flops are edge triggered
Master-Slave D flip-flop Use two D flip-flops with control input The output of the first is the input to the second The first is the master The second is the slave
Master-Slave Operation When the CLK is low the slave copies the state of the master When the clock is high the state of the master is copied from its input The input cannot propagate more than one stage per clock transition.
Master-Slave Alternatives Master-Slave is not the only known solution. A less expensive version would need three bare latches
Operation When the CLK is the input to the SR output latch is -, and the output is maintained. When the CLK goes, the S of the output latch becomes equal to D and R becomes equal to D If D changes while CLK is high, the SR are not affected
Positive Edge Triggered The F-F responds only to -> transitions aka leading edge triggered The output of the F-F changes immediately after the clock transition Any change in the input has no effect before the clock transition.
Timing In real-life circuits nothing is instantaneous The input D has to stabilize for a short time before the clock transition this is called setup time The input D has to remain stable for a short time after the clock transition This is called hold time.
Graphic Symbol The clock of a positive edge triggered F-F is indicated by a small arrowhead and the letter C (sometimes CLK) The little arrowhead is called dynamic indicator. A small circle (bubble... whatever) designates a negative edge triggered F-F
Other Flip-Flops The least expensive F-F is the edge triggered D F-F (if you count VLSI real estate) It needs the fewest gates to implement. Often it needs the smallest total number of gates (gates inside the F-F and external logic)
Other Flip-Flops Other F-Fs can be built using D F-Fs There are three desired operations on a F-F Set (to ) Reset (to ) Toggle
J-K Flip-Flop Can do all desired operations Usually needs the smallest number of external gates (its excitation table has many don t cares) Often the best when using MSI technologies Less impressive in VLSI implementations Like SR but without illegal inputs
J-K Flip-Flop D = J Q + K Q The F-F is set when JK = The F-F is reset when JK = Nothing changes if JK = The F-F toggles if JK = That would be indeterminable for SR latches
T Flip-Flop T stands for trigger or toggle Was popular in the era of discrete transistors could be implemented with two transistors and several resistors and capacitors. Counters have essentially T F-F Can be thought of as a J-K F-F with the inputs tied together.
T Flip-Flop D = TQ + T Q The F-F toggles if the input T= Nothing happens if T=
Characteristic Tables The truth tables of F-F Give us the next state of the F-F given the input and current state Can be expressed in various equivalent forms
Characteristic Table for J-K JK Q(t+) Q(t) Q (t) No change Reset Set Toggle
Tables for D and T D Q(t+) T Q(t+)
Characteristic Equations Same info as tables, but in algebraic form The D F-F Q(t+) = D The J-K F-F Q(t+) = JQ + K Q The T F-F Q(t+)= TQ + T Q
Direct Inputs Need to preset a F-F during startup. also when we have a general reset Has to be independent of clock Rarely used as part of the overall behaviour.
Analysis of Clocked Sequential Circuits No new mathematics, algorithms An orderly procedure to investigate the functionality of the circuit Set of conventions
State Equations Every combination of the flip-flop values is called state The state changes after every clock pulse State equations are the equations that give us the next state as a function of the current state and the input
State Equations The state equations are also called transition equations We derive the state equations from the circuit schematic
Example We analyze a simple circuit with two F-F named A and B, one input x and an output y We derive the state equations first
The Equations These can be written as A(t+) = A(t)x(t) + B(t)x(t) B(t+) = A (t)x(t) And if we are lazy A(t+) = Ax + Bx B(t+) = A x
Not done yet The output equation is usually bundled y = (A + B)x The output is valid before the clock pulse, then the state changes, the input changes and the output finally settles before the next clock pulse.
State Table The state table presents the same information in tabular form Also called transition table Also bundled with the output data
Two Common Forms In the first form every row is labeled by all unique combinations of current state and input. The next state and output are separate columns In the second, we label rows with all current states and have multiple sets of columns for the next state and output.
State Table Present state Input Next State Output AB x AB y
State Table (Alt) Present State Next State Output x= x= x= x= AB AB AB y y
State Diagram We see the circuit more like something that changes states, than a collection of F-F and gates It is really a Finite State Machine (FSM) So can be represented by a State Diagram (you know, the thingy with the bubbles and the arrows between them...)
State Diagram The bubbles represent the states and are labeled (usually) with the binary number of the state The edges are the transitions and are labeled with the input that cause the transition We indicate the output after the slash
Mealy and Moore There are two slight variations in FSMs The Mealy, where the output is a function of the input and present state The Moore, where the output is a function of the present state alone.
Mealy and Moore In the Mealy the / (slash) and the output are written on the transition edge In the Moore model the / and the output are written inside the state bubble.
F-F Input Convention We might need to write explicitly the input equation for the F-F of our circuit If it is a D F-F named A then D_A = Ax + Bx Similarly D_B = A x
Analysis with D F-F We did that already It is easy because the next state is the same as the input
For this Example Input Equations D_A = A xor x xor y State Equations A(t+) = A xor x xor y There is no output (the state itself is usually the output in this case)
Analysis with J-K F-F Slightly more complex One needs to use the characteristic table or the characteristic equation for the J-K F-F
The Steps Determine the F-F input Equations List the binary values for each input equation and state Use the char. tables to determine the next state
The Input Equations These are: J_a = B K_a= Bx J_b = x K_b= A xor x
State Table V Present State Input Next State F-F Inputs AB x JA KA JB KB
State Table V2 Present State Input Next State F-F Inputs AB x AB JA KA JB KB
Alternatively... We can use the characteristic equation A(t+) = J_a A + K_a A B(t+) = J_b B + K_b B Plug in the values A(t+) = BA + B A + Ax B(t+) = x B + A x B + AxB Matter of taste
Analysis with T F-F Similar idea to J-K F-F We fill the state table in two stages
State Table Present State Next State FF input A B Input AB x AB JK JK
HDL for Sequential Circuits Behavioral Modeling using the always construct Structural Description By describing the interconnection between gates and FFs
The always Construct The always statement is executed repeatedly Normally conditioned by the event control expression or sensitivity list or just @-list Can have as many always statements as needed. All execute concurrently Concurrency is a fact of life in H/W
The always Construct The event list is an or separated list of signals The always statement is executed when there is a change in any of the signals The statement (or block of statements) is then executed once
Two Kinds of Events Level sensitive triggered by any change in level useful in combinational circuits Edge triggered triggered by positive only or negative only events useful in sequential circuits
Of course! There are two kinds of edge-triggered events keyword negedge keyword posedge That s because FF are of two kinds
Procedural Assignments These are gated and happen only when always blocks are executed Different from the dataflow assignment, which is continuous The lhs has to be of type reg. And guess what...
There are Two Kinds Blocking The assignment is completed before the next statement starts execution Similar to C and most other programming languages Non-Blocking The next statement sees the old value of the lhs of the previous statement
Example: Blocking Consider the following blocking procedural assignments, where A is initially 3 and B is initially B=A C=B+ After the execution C will contain 4
Example: non-blocking If the assignment is non-blocking B <= A C <= B + After the execution C will contain 2! Easier to understand if you think of B and C as collections of edge triggered FFs.
D Latch The D latch has two inputs the D input and the control input And one output If the control is high the output trails the input, otherwise holds the last input
HDL code for the D Latch //HDL Example 5 // //Description of D latch (See Fig.5 6) module D_latch (Q,D,control); output Q; input D,control; reg Q; always @ (control or D) if (control) Q = D; //Same as: if (control = ) endmodule
D Flip-Flop Slightly more complex It is triggered by the clock edge If the input D changes the state or output of the FF does not change before the clock edge
HDL for D Flip-Flop //HDL Example 5 2 // //D flip flop module D_FF (Q,D,CLK); output Q; input D,CLK; reg Q; always @ (posedge CLK) Q = D; endmodule
D FF with RESET We now have two asynchronous inputs The RESET is active low
HDL for D FF with RESET //D flip flop with asynchronous reset. module DFF (Q,D,CLK,RST); output Q; input D,CLK,RST; reg Q; always @(posedge CLK or negedge RST) if (~RST) Q = 'b; // Same as: if (RST = ) else Q = D; endmodule
Observation In the if statement the then clause is asynchronous logic Same for else if, if there was any. The last else statement is synchronous logic
Observation In the sensitivity list we have posedge CLK and negedge RST As long as RST is, the FF is reset, despite the fact that we trigger with negedge The CLK is effective only during the positive edge, and the only when RST=
T Flip-Flop The characteristic equation is Q(t+) = Q xor T We can use a D FF to build the T FF we could build it from scratch too... Use dataflow and structural model mix
HDL for T Flip-Flop //T flip flop from D flip flop and gates module TFF (Q,T,CLK,RST); output Q; input T,CLK,RST; wire DT; assign DT = Q ^ T ; //Instantiate the D flip flop DFF TF (Q,DT,CLK,RST); endmodule
T Flip-Flop from Scratch //T flip flop module T_FF (Q,T,CLK,RST); output Q; input T,CLK,RST; reg Q; always @ (posedge CLK or negedge RST) if (~RST) Q = 'b; else Q = Q ^ T; endmodule
J-K Flip-Flop The characteristic equation is Q(t+) = JQ + J K We use again a D FF
HDL for J-K F-F //JK flip flop from D flip flop and gates module JKFF (Q,J,K,CLK,RST); output Q; input J,K,CLK,RST; wire JK; assign JK = (J & ~Q) (~K & Q); //Instantiate D flipflop DFF JK (Q,JK,CLK,RST); endmodule
J-K from Scratch // Functional description of JK flip flop module JK_FF (J,K,CLK,Q,Qnot); output Q,Qnot; input J,K,CLK; reg Q; assign Qnot = ~ Q ; always @ (posedge CLK) case ({J,K}) 2'b: Q = Q; 2'b: Q = 'b; 2'b: Q = 'b; 2'b: Q = ~ Q; endcase endmodule
State Diagrams Verilog (and other HDLs) can immitate state diagrams There are two basic variations: Mealy and Moore Makes life easier to use keyword parameter.
Example: Mealy Mealy is the one with the outputs on the edges The structure of the HDL program reflects the H/W: one always for the sequential circuit one always for the next state calculation one always for the output
State Diagram in HDL module Mealy_mdl (x,y,clk,rst); input x,clk,rst; output y; reg y; reg [:] Prstate, Nxtstate; parameter S = 2'b, S = 2'b, S2 = 2'b, S3 = 2'b; always @ (posedge CLK or negedge RST) if (~RST) Prstate = S; else Prstate = Nxtstate; //Clock operations always @ (Prstate or x) //Determine next state case (Prstate) S: if (x) Nxtstate = S; S: if (x) Nxtstate = S3; else Nxtstate = S; S2: if (~x)nxtstate = S; S3: if (x) Nxtstate = S2; else Nxtstate = S; endcase always @ (Prstate or x) //Evaluate output case (Prstate) S: y = ; S: if (x) y = 'b; else y = 'b; S2: if (x) y = 'b; else y = 'b; S3: if (x) y = 'b; else y = 'b; endcase endmodule
Example: Moore Moore is the one with the outputs inside the state bubble (or implied) The HDL reflects again the (slightly) simpler H/W Here we combine the always.
Moore in HDL module Moore_mdl (x,ab,clk,rst); input x,clk,rst; output [:]AB; reg [:] state; parameter S = 2'b, S = 2'b, S2 = 2'b, S3 = 2'b; always @ (posedge CLK or negedge RST) if (~RST) state = S; //Initialize to state S else case (state) S: if (~x) state = S; S: if (x) state = S2; else state = S3; S2: if (~x) state = S3; S3: if (~x) state = S; endcase assign AB = state; //Output of flip flops endmodule
State Reduction Often a sequential circuit with fewer states can do exactly the same job There are multiple benefits from reducing the number of states State tables (or diagrams) generated by software tend to have redundant states.
The Benefits Fewer flip-flops More unused states, thus more don t cares
Definition Two FSM are equivalent when for all input sequences they produce the same output Unfortunately all is too many We have to find a more workable definition
How About... Define the equivalence of states. If we find that two states are equivalent we merge them Two states in an FSM are equivalent if for every input produce the same output and jump to the same state or to equivalent states.
Sounds better This is a workable definition We can use it to simplify state diagrams by hand We can use it to design an algorithm.
Example In the next FSM we observe that states g and e are equivalent with input they go to f and produce with input they go to a and produce
Some More... So e and g is one state with two different names. But now f and d are equivalent with input they go to {e,g} and produce with input they go to f and produce
The Algorithm Initial step: For every state fill in the truth table that relates inputs to outputs Place all the states in groups such that all states in the same group have identical truth tables
Iteration Repeatedly select a group of states i if the states within i jump to different groups, split i into several groups
The Same Example State a b c d e f g Inp Out Next a b c d a d e f a f g f a f
Groupings abc defg a bc a a bc b c defg df eg df eg
State Assignment With N states there are at least N! possible state assignments Some of them are better than others There is little algorithmic help to find the optimal state assignment
A Few Simple Ideas If there is a natural ordering in the states of the module, then assign consecutive binary numbers to the states Even better (sometimes) use Gray code instead of binary (minterms tend to fall near other minterms in the map)
Number of F-F A circuit always has a power of two number of states, although the FSM requires fewer We end up with unused states This is good: lots of don t cares! Sometimes it is worth having extra F-F just for the don t cares.
In the Extreme We can even have one F-F per state (aka one hot) This often saves enough gates to justify the real estate taken up by the extra F-F
Design Procedure Now we are ready to design a circuit Design consists of translating words to symbols, tables, HDL... specifying the logic optimizing the design for cost and or performance communicating the results
But most of all Keep things tidy and ordered Manage complexity
Detailed Steps Produce a state diagram Minimize it Assign binary values to states Choose the technology Obtain state table (binary coded) Minimize FF input equations
...Detailed Steps Draw logic diagram (or equivalent) Calculate costs Do it again until you nauseate (or have reduced the cost enough)
Word Specification Comes from the system architect Might or might not be exact, unambiguous There is some help from various design aids Needs experience
Example Design a module that detects three or more consecutive s. This module should have 4 states One state for zero s One for one One for two s One for three or more s
State Table Present Input Next Output AB x AB
Using D F-F Using D F-F the next state is the same as the F-F input A(t+) = Sum(3,5,7) B(t+) = Sum(,5,7) y = Sum(6,7)
Using J-K F-F Not much harder, but we need the excitation tables These are the inverses of the characteristic tables For J-K F-F the have lots of don t cares
J-K and T FF Excitation Tables Q(t) Q(t+) JK Q(t) Q(t+) T X X X X
State Table for J-K F-F Pres Input Next AB x AB F-F Inputs
State Table for J-K F-F Pres Input Next F-F Inputs AB x AB JK JK X X X X X X X X X X X X X X X X
State Table for 3-Bit Counter Present Next A2 A A A2 A A Flip-Flop Inputs
Present Next Flip-Flop Inputs A2 A A A2 A A T T2 T3