Chpter 5 Synchronous Sequentil Logic Outlines Sequentil Circuits Ltches Flip-Flops Anlysis of Clocke Sequentil Circuits Stte Reuction n Assignment Design Proceure 2
5. Sequentil Circuits Sequentil circuits re logic circuits with memories The Stte- the stte of the memory evices now, lso clle current stte Next Stte epens on the present stte n present inputs 3 5. Sequentil Circuits The behvior of n synchronous sequentil circuit epens from the knowlege of its signls t iscrete instnts of time The behvior of n synchronous sequentil circuit epens upon the input signls t ny instnt of time n the orer in which the inputs chnge 4
Outlines Sequentil Circuits Ltches Flip-Flops Anlysis of Clocke Sequentil Circuits Stte Reuction n Assignment Design Proceure 5 5.2 LATCHES The most bsic types of flip-flops operte with signl levels n re referre to s ltches Ltches re useful for storing binry informtion n for the esign of synchronous sequentil circuits, they re not prcticl for use in synchronous sequentil circuits. 6
SR Ltch The SR ltch is circuit with two cross-couple NOR gtes If is pplie to both the S n R inputs of the ltch, both outputs go to 7 SR Ltch The SR ltch is circuit with two cross-couple NAND gtes If is pplie to both the S n R inputs of the ltch, both outputs go to 8
SR Ltch The opertion of the bsic SR ltch cn be moifie by proviing n itionl control input tht etermines when the stte of the ltch cn be chnge 9 Logic Simultion of SR Ltch Behvior
D Ltch This ltch hs only two inputs:d(t) n C(control) The D input goes irectly to the S input n its complement is pplie to the R input Outlines Sequentil Circuits Ltches Flip-Flops Anlysis of Clocke Sequentil Circuits Stte Reuction n Assignment Design Proceure 2
5.3 FLIP-FLOPS The stte of ltch or flip-flop is switche by chnge in the control input. This momentry chnge is clle trigger 3 Ege-Triggere D Flip-Flop The construction of D Flip-Flop with two D ltches n n inverter The first ltch is clle the mster n the secon the slve. The circuit smples the D input n chnges its output Q only t the negtive-ege of the controlling clock. 4
Ege-Triggere D Flip-Flop An ege-triggere D flip-flop uses three SR ltches Two ltches respon to the externl D(t) n CLK(clock) inputs The thir ltch provies the outputs for the flip-flop. 5 Logic Simultion of Mster- Slve Flip-Flop 6
Mster-Slve JK Flip-Flop 7 D-Type Positive Ege- Triggere Flip-Flop 8
Flip-Flop Chrcteristic Tble 9 Ege-Triggere D Flip-Flop The timing of the response of flip-flop to input t n clock must be tken into consiertion when using ege-triggere flip-flops. There is minimum time, clle setup time, for which the D input must be mintine t constnt vlue prior to the occurrence of the clock trnsition. There is minimum time, clle the hol time, for which the D input must not chnge fter the ppliction of the positive trnsition of the clock 2
Ege-Triggere D Flip-Flop The grphic symbol for the egetriggere D flip-flop 2 Other Flip-Flops Other types of flip-flops cn be constructe by using the D flip-flop n externl logic. Two flip-flops wiely use in the esign of igitl systems re the JK n T flip-flops There re three opertions tht cn be performe with flip-flop Set it to Reset it to Complement its output 22
JK Flip-Flops The J input sets the flip-flop to The K input resets the flip-flop to When both inputs re enble, the output is complemente The expression for the D input is D = JQ'+ K' Q 23 T Flip-Flops The T flip-flop is complementing flip-flop n cn be obtine from JK flip-flop. The T flip-flop cn be constructe with D flip-flop n n exclusive-or gte The expression for the D input is D = T Q = TQ'+ T ' Q 24
Chrcteristic tbles JK flip-flop D Flip-Flop J K Q(t+) D Q(t+) Q(t) Q (t) No chnge Reset Set complement Reset Set T Flip-Flop D Q(t+) Q(t) Q(t) No chnge Complement 25 Chrcteristic equtions D flip-flop Q ( t + ) = D JK flip-flop T flip-flop Q ( t + ) = JQ' + K' Q Q ( t + ) = T Q = TQ' + T ' Q 26
Direct inputs Some flip-flop hve synchronous inputs tht re use to force the flip-flop to prticulr stte inepenent of the clock The input tht sets the flip-flop to is clle preset or irect set The input tht clers the flip-flop to is clle cler or irect reset when power is turne on in igitl system, the stte of the flip-flop is unknow 27 Direct inputs 28
Outlines Sequentil Circuits Ltches Flip-Flops Anlysis of Clocke Sequentil Circuits Stte Reuction n Assignment Design Proceure 29 5.4 Anlysis of clocke sequentil circuits The behvior of clocke sequentil circuit is etermine from the inputs, the outputs, n the stte of its flip-flop. The outputs n the next stte re both function of the inputs n the present stte. The nlysis of sequentil circuit consists of obtining tble or igrm for the time sequence of inputs, outputs, n internl sttes. It is lso possible to write Boolen expressions tht escribe the behvior of the sequentil circuit 3
Stte Equtions The behvior of clocke sequentil circuit cn be escribe lgebriclly by mens of stte eqution. A stte eqution(lso clle trnsition eqution) specifies the next stte s function of the present stte n input EX: A(t+)=A(t)x(t)+B(t)x(t) A(t+)=Ax+Bx B(t+)=A (t)x(t) B(t+)=A x y(t)=[a(t)+b(t)]x(t) y=(a+b)x 3 Stte tble The time sequence of inputs, outputs, n flip-flop sttes cn be enumerte in stte tble(sometimes clle trnsition tble) The tble consists of four sections lbele present stte, input, next stte, n output A sequentil circuit with m flip-flops n n inputs nee 2 m+n rows in the stte tble Present stte A B input x Next stte A B output y 32
Stte tble The stte tble hs only three section:present stte, next stte, n output PRESENT STATE X= NEXT STATE X= OUTPUT X= X= A B A B A B Y Y 33 Stte Digrm The informtion vilble in stte tble cn be represente grphiclly in the form of stte igrm. Strting from stte, the output is s long s the input stys t 34
Flip-Flop Input Equtions The prt of the combintionl circuit tht genertes externl outputs is escribe lgebriclly by set of Boolen functions clle output equtions The prt of the circuit tht genertes the inputs to flip-flops is escribe lgebriclly by set of Boolen functions clle flipflop input equtions (sometimes clle excittion equtions) Ex: Input: D A =Ax+Bx D B =A x Output: y=(a+b)x 35 Anlysis with D Flip-Flop Ex: Input eqution:d A =A x y 36
Anlysis with JK Flip-Flops The next stte vlues of sequentil circuit tht uses flip-flops such s JK or T type cn be erive using the following proceure: Determine the flip-flop input equtions in terms of the present stte n input vribles List the binry vlues of ech input eqution Use the corresponing flip-flop chrcteristic tble to etermine the next stte vlues in the stte tble 37 Anlysis with JK Flip-Flops Ex: input equtions:j A =B K A =Bx J B =x K B =A x A(t+)=JA +K A =BA +(Bx ) A =A B+AB +Ax B(t+)=JB +K B =x B +(A x) B =B X +ABx+A Bx 38
39 Anlysis with JK Flip-Flops K B J B K A J A B A X B A Flip-Flop Inputs Next stte Input Present stte 4 Anlysis With T Flip-Flop Ex: input eqution n output eqution T A =Bx T B =x y=ab A(t+)=(Bx) A+(Bx)A =AB +Ax +A Bx B(t+)=x B y B A X B A OUTPUT Next stte Input Present stte
Anlysis With T Flip-Flop 4 Mely n Moore Moel Mely moel: The output is function of both the present stte n input The output of the sequentil circuit re synchronize with the clock The inputs of the sequentil circuit must be synchronize with the clock n the outputs must be smple only uring the clock ege Moore moel: The output is function of the present stte only The output s my chnge if the inputs chnge uring the clock cycle 42
Outlines Sequentil Circuits Ltches Flip-Flops Anlysis of Clocke Sequentil Circuits Stte Reuction n Assignment Design Proceure 43 5.5 Stte reuction n ssignment Ex: stte b c e f f g f g Input output 44
Stte reuction n ssignment Ex: the stte tble of the circuit is liste in tble 5-6 Tble 5-6 PRESENT STATE b c e f g NEXT STATE X= c e g X= b f f f f OUTPUT X= X= 45 Stte reuction n ssignment Ex: Two present sttes tht go to the sme next stte n hve the sme output for both input combintions PRESEN T STATE b c e f NEXT STATE X= c e e X= b f f f OUTPUT X= X= 46
Stte reuction n ssignment Ex: sttes f n re equivlent n stte f cn be remove n replce by PRESENT STATE b NEXT STATE X= c X= b OUTPUT X= X= c e e 47 Ex: Stte reuction n ssignment stte Input output b c e e e 48
Stte Assignment For circuit with m sttes, the coes must contin n bits where 2 n >=m Unuse sttes re trete s on t cre conitions uring the esign. 49 Outlines Sequentil Circuits Ltches Flip-Flops Anlysis of Clocke Sequentil Circuits Stte Reuction n Assignment Design Proceure 5
5.6 Design Proceure The proceure for esigning synchronous sequentil circuits cn be summrize by list of recommene steps From the wor escription n specifictions of the esire opertion, erive stte igrm for the circuit Reuce the number of sttes if necessry Assign binry vlues to the sttes Obtin the binry-coe stte tble Choose the type of flip-flop to be use Derive the simplifie flip-flop input equtions n output equtions Drw the logic igrm 5 Synthesis using D Flip-Flops Ex:5-6 in section 5-5 Present stte Input Next stte OUTPUT A( t + ) = DA( A, B, x) = B( t + ) = DB( A, B, x) = y( A, B, x) = (3,5,7) (,5,7) (6,7) A B X A B y D A =Ax+Bx D B =Ax+B x Y=AB 52
Synthesis using D Flip-Flops Ex:5-6 in section 5-5 D A =Ax+Bx D B =Ax+B x Y=AB 53 Synthesis using JK Flip-Flops Ex:5-6 in section 5-5 Presen t stte Inpu t Next stte OUTPUT J A =Bx J B =x K A =Bx K B =(A x) A B X A B y 54
Synthesis using JK Flip-Flops Ex:5-6 in section 5-5 J A =Bx J B =x K A =Bx K B =(A x) 55 Synthesis using T Flip-Flops Ex:3-Bits counter 56
Synthesis using T Flip-Flops Ex:3-Bits counter Present stte Next stte Flip-Flop Inputs T A2 =A A A2 A A A2 A A T A2 T A T A T A =A T A = 57 Synthesis using T Flip-Flops Ex:3-Bits counter T A2 =A A T A =A T A = 58