Logic ad Computer Desig Fudametals Chapter 7 Registers ad Register Trasfers Part 2 Couters, Register Cells, Buses, & Serial Operatios Charles Kime & Thomas Kamiski 28 Pearso Educatio, Ic (Hyperliks are active i View Show mode) Overview Part Registers, Microoperatios ad Implemetatios Part 2 Couters, register cells, buses, & serial operatios Microoperatios o sigle register (cotiued) Couters Register cell desig Multiplexer ad bus-based trasfers for multiple registers Serial trasfers ad microoperatios Part 3 Cotrol of Register Trasfers Chapter 7 - Part 2 2
Couters Couters are sequetial circuits which "cout" through a specific state sequece They ca cout up, cout dow, or cout through other fixed sequeces Two distict types are i commo usage: Ripple Couters Clock coected to the flip-flop clock iput o the LSB bit flipflop For all other bits, a flip-flop output is coected to the clock iput, thus circuit is ot truly sychroous! Output chage is delayed more for each bit toward the MSB Resurget because of low power cosumptio Sychroous Couters Clock is directly coected to the flip-flop clock iputs Logic is used to implemet the desired state sequecig Chapter 7 - Part 2 3 Ripple Couter How does it work? D A Whe there is a positive edge o the clock iput of A, A complemets Clock C R The clock iput for flipflop D B B is the complemeted C R output of flip-flop A Reset Whe flip A chages from to, there is a positive edge o the clock iput of B CP A causig B to B complemet 2 3 Chapter 7 - Part 2 2
Ripple Couter (cotiued) The arrows show the cause-effect relatioship from the prior slide => The correspodig CP A B sequece of states => 2 3 (B,A) = (,), (,), (,), (,), (,), (,), Each additioal bit, C, D, behaves like bit B, chagig half as frequetly as the bit before it For 3 bits: (C,B,A) = (,,), (,,), (,,), (,,), (,,), (,,), (,,), (,,), (,,), Chapter 7 - Part 2 5 Ripple Couter (cotiued) These circuits are called ripple couters because each edge sesitive trasitio (positive i the example) causes a chage i the ext flip-flop s state The chages ripple upward through the chai of flip-flops, i e, each trasitio occurs after a clock-to-output delay from the stage before To see this effect i detail look at the waveforms o the ext slide Chapter 7 - Part 2 6 3
Ripple Couter (cotiued) Startig with C = B = A =, equivalet to (C,B,A) = 7 base, the ext clock icremets the cout to (C,B,A) = base I fie timig detail: t The clock to output delay PHL CP t PHL causes a icreasig delay from clock edge for t PHL A each stage trasitio Thus, the cout ripples t phl from least to most B sigificat bit C For bits, total worst case delay is t PHL Chapter 7 - Part 2 7 Sychroous Couters To elimiate the "ripple" effects, use a commo clock for each flip-flop ad a combiatioal circuit to geerate the ext state For a up-couter, use a icremeter => Icremeter Clock A3 A2 A A S3 S2 S S D3 D2 D D Q3 Q2 Q Q Chapter 7 - Part 2 8
Sychroous Couters (cotiued) Iteral details => Icremeter Iteral Logic XOR complemets each bit AND chai causes complemet of a bit if all bits toward LSB from it equal Cout Eable Forces all outputs of AND chai to to hold the state Carry Out Added as part of icremeter Coect to Cout Eable of additioal -bit couters to form larger couters Cout eable EN Clock D C D C D C D C Q Q Q 2 Q 3 Carry output CO (a) Logic Diagram-Serial Gatig Chapter 7 - Part 2 9 Sychroous Couters (cotiued) Carry chai series of AND gates through which the carry ripples Yields log path delays Called serial gatig Replace AND carry chai with ANDs => i parallel Reduces path delays Called parallel gatig Like carry lookahead Lookahead ca be used o COs ad ENs to prevet log paths i large couters Symbol for Sychroous Couter CTR EN Q Q Q 2 Q 3 CO Symbol EN Q Q C Q 2 C 2 Q 3 C 3 CO Logic Diagram-Parallel Gatig Chapter 7 - Part 2 5
Other Couters See text for: Dow Couter - couts dowward istead of upward Up-Dow Couter - couts up or dow depedig o value a cotrol iput such as Up/Dow Parallel Couter - Has parallel load of values available depedig o cotrol iput such as Divide-by- (Modulo ) Couter Cout is remaider of divisio by ; may ot be a power of 2 or Cout is arbitrary sequece of states specifically desiged state-by-state Icludes modulo which is the BCD couter Chapter 7 - Part 2 Couter with Parallel Add path for iput data eabled for = Add logic to: Cout D D C Q disable cout logic for = disable feedback from outputs for = eable cout logic for = ad Cout = The resultig fuctio table: D D 2 D C D Q Q 2 Cout Actio C Hold Stored Value Cout Up Stored Value D 3 D Q 3 X D C Clock Carry Output CO Chapter 7 - Part 2 2 6
Desig Example: Sychroous BCD Use the sequetial logic model to desig a sychroous BCD couter with D flip-flops State Table => Iput combiatios through are do t cares Curret State Q8 Q Q2 Q Next State Q8 Q Q2 Q Chapter 7 - Part 2 3 Sychroous BCD (cotiued) Use K-Maps to two-level optimize the ext state equatios ad maipulate ito forms cotaiig XOR gates: D = Q D2 = Q2 + QQ8 D = Q + QQ2 D8 = Q8 + (QQ8 + QQ2Q) The logic diagram ca be draw from these equatios A asychroous or sychroous reset should be added What happes if the couter is perturbed by a power disturbace or other iterferece ad it eters a state other tha through? Chapter 7 - Part 2 7
Sychroous BCD (cotiued) Fid the actual values of the six ext states for the do t care combiatios from the equatios Fid the overall state diagram to assess behavior for the do t care states (states i decimal) Preset State Next State 9 Q8 Q Q2 Q Q8 Q Q2 Q 8 2 5 2 7 3 3 6 5 Chapter 7 - Part 2 5 Sychroous BCD (cotiued) For the BCD couter desig, if a ivalid state is etered, retur to a valid state occurs withi two clock cycles Is this adequate? If ot: Is a sigal eeded that idicates that a ivalid state has bee etered? What is the equatio for such a sigal? Does the desig eed to be modified to retur from a ivalid state to a valid state i oe clock cycle? Does the desig eed to be modified to retur from a ivalid state to a specific state (such as )? The actio to be take depeds o: the applicatio of the circuit desig group policy See pages 2 of the text Chapter 7 - Part 2 6 8
Coutig Modulo N The followig techiques use a -bit biary couter with asychroous or sychroous clear ad/or parallel load: Detect a termial cout of N i a Modulo-N cout sequece to asychroously Clear the cout to or asychroously i value (These lead to couts which are preset for oly a very short time ad ca fail to work for some timig coditios!) Detect a termial cout of N - i a Modulo-N cout sequece to Clear the cout sychroously to Detect a termial cout of N - i a Modulo-N cout sequece to sychroously i value Detect a termial cout ad use to preset a cout of the termial cout value mius (N - ) Alteratively, custom desig a modulo N couter as doe for BCD Chapter 7 - Part 2 7 Coutig Modulo 7: Detect 7 ad Asychroously Clear A sychroous -bit biary couter with a asychroous Clear is used to make a Modulo 7 couter Use the Clear feature to detect the cout 7 ad clear the cout to This gives a cout of,, 2, 3,, 5, 6, 7(short),, 2, 3,, 5, 6, 7(short), etc Clock DON T DO THIS! Existece of state 7 may ot be log eough to reliably reset all flip-flops to Referred to as a suicide couter! (Cout 7 is killed, but the desiger s job may be dead as well!) D3 D2 D D Q3 Q2 Q Q CP LOAD CLEAR Chapter 7 - Part 2 8 9
Coutig Modulo 7: Sychroously o Termial Cout of 6 A sychroous -bit biary couter with a sychroous load ad a asychroous clear is used to make a Modulo 7 couter Use the feature to detect the cout "6" ad load i "zero" This gives a cout of,, 2, 3,, 5, 6,,, 2, 3,, 5, 6,, Usig do t cares for states Clock Reset above, detectio of 6 ca be doe with = Q Q2 D3 Q3 D2 Q2 D Q D Q CP LOAD CLEAR Chapter 7 - Part 2 9 Coutig Modulo 6: Sychroously Preset 9 o Reset ad 9 o Termial Cout A sychroous, -bit biary couter with a sychroous is to be used to make a Modulo 6 couter Use the feature to preset the cout to 9 o Reset ad detectio of Reset cout Clock D3 Q3 D2 Q2 D Q D Q CP LOAD CLEAR This gives a cout of 9,,, 2, 3,, 9,,, 2, 3,, 9, If the termial cout is 5 detectio is usually built i as Carry Out (CO) Chapter 7 - Part 2 2
Register Cell Desig Assume that a register cosists of idetical cells The register desig ca be approached as follows: Desig represetative cell for the register Coect copies of the cell together to form the register Applyig appropriate boudary coditios to cells that eed to be differet ad cotract if appropriate Register cell desig is the first step of the above process Chapter 7 - Part 2 2 Register Cell Specificatios A register Data iputs to the register Cotrol iput combiatios to the register Example : Not ecoded Cotrol iputs:, Shift, Add At most, oe of, Shift, Add is for ay clock cycle (,,), (,,), (,,), (,,) Example 2: Ecoded Cotrol iputs: S, S All possible biary combiatios o S, S (,), (,), (,), (,) Chapter 7 - Part 2 22
Register Cell Specificatios A set of register fuctios (typically specified as register trasfers) Example: : A B Shift: A sr B Add: A A + B A hold state specificatio Example: Cotrol iputs:, Shift, Add If all cotrol iputs are, hold the curret register state Chapter 7 - Part 2 23 Multiplexer Approach Uses a -iput multiplexer with a variety of trasfer sources ad fuctios K K Dedicated logic Ecoder Dedicated logic k Registers or shared logic S m S MUX k k R Chapter 7 - Part 2 2 2
Multiplexer Approach eable by OR of cotrol sigals K, K, K - - assumes o load for Use: Ecoder + Multiplexer (show) or x 2 AND-OR to select sources ad/or trasfer fuctios K K Dedicated logic Ecoder Dedicated logic k Registers or shared logic S m S MUX k k R Chapter 7 - Part 2 25 Example : Register Cell Desig Register A (m-bits) Specificatio: Data iput: B Cotrol iputs (CX, CY) Cotrol iput combiatios (,), (,) (,) Register trasfers: CX: A B v A CY :A B + A Hold state: (,) Chapter 7 - Part 2 26 3
Example : Register Cell Desig (cotiued) Cotrol = CX + CY Sice all cotrol combiatios appear as if ecoded (,), (,), (,) ca use multiplexer without ecoder: S = CX S = CY D = A i Hold A D = A i B i + A i CY = D2 = A i B i v A i CX = Note that the decoder part of the 3-iput multiplexer ca be shared betwee bits if desired Chapter 7 - Part 2 27 Sequetial Circuit Desig Approach Fid a state diagram or state table Note that there are oly two states with the state assigmet equal to the register cell output value Use the desig procedure i Chapter 5 to complete the cell desig For optimizatio: Use K-maps for up to to 6 variables Otherwise, use computer-aided or maual optimizatio Chapter 7 - Part 2 28
Example Agai State Table: A i Hold CX = CY = CX = B i = Ai v Bi CX = B i = Ai + Bi CY = CY = B i = B i = Four variables give a total of 6 state table etries By usig: Combiatios of variable ames ad values Do t care coditios (for CX = CY = ) oly 8 etries are required to represet the 6 etries Chapter 7 - Part 2 29 Example Agai (cotiued) K-map - Use variable orderig CX, CY, A i B i ad assume a D flip-flop D i A i CX X X B i X X CY Chapter 7 - Part 2 3 5
Example Agai (cotiued) The resultig SOP equatio: D i = CX B i + CY A i B i + A i B i + CY A i Usig factorig ad DeMorga s law: D i = CX B i + A i (CY B i ) + A i (CY B i ) D i = CX B i + A i + (CY B i ) The gate iput cost per cell = 2 + 8 + 2 + 2 = The gate iput cost per cell for the previous versio is: Per cell: 9 Shared decoder logic: 8 Cost gai by sequetial desig > 5 per cell Also, o Eable o the flip-flop makes it cost less Chapter 7 - Part 2 3 Multiplexer ad Bus-Based Trasfers for Multiple Registers Multiplexer dedicated to each register Shared trasfer paths for registers A shared trasfer object is a called a bus (Plural: buses) Bus implemetatio usig: multiplexers three-state odes ad drivers I most cases, the umber of bits is the legth of the receivig register Chapter 7 - Part 2 32 6
Dedicated MUX-Based Trasfers Multiplexer coected to each register iput produces a very flexible trasfer structure => S S MUX S L R L Characterize the simultaeous trasfers possible with this structure S MUX S2 R L2 S MUX R2 Chapter 7 - Part 2 33 Multiplexer Bus A sigle bus drive by a multiplexer lowers cost, but limits the available trasfers => Characterize the simultaeous trasfers possible with this structure Characterize the cost savigs compared to dedicated multiplexers S S S S MUX 2 L R L R L2 R2 Chapter 7 - Part 2 3 7
Three-State Bus The 3-iput MUX ca be replaced by a 3-state ode (bus) ad 3-state buffers Cost is further reduced, but trasfers are limited Characterize the simultaeous trasfers possible with this structure Characterize the cost savigs ad compare Other advatages? E E L R L R L2 R2 E2 Chapter 7 - Part 2 35 Serial Trasfers ad Microoperatios Serial Trasfers Used for arrow trasfer paths Example : Telephoe or cable lie Parallel-to-Serial coversio at source Serial-to-Parallel coversio at destiatio Example 2: Iitializatio ad Capture of the cotets of may flip-flops for test purposes Add shift fuctio to all flip-flops ad form large shift register Use shiftig for simultaeous Iitializatio ad Capture operatios Serial microoperatios Example : Additio Example 2: Error-Correctio for CDs Chapter 7 - Part 2 36 8
Serial Microoperatios By usig two shift registers for operads, a full adder, ad a flip flop (for the carry), we ca add two umbers serially, startig at the least sigificat bit Serial additio is a low cost way to add large umbers of operads, sice a tree of full adder cells ca be made to ay depth, ad each ew level doubles the umber of operads Other operatios ca be performed serially as well, such as parity geeratio/checkig or more complex error-check codes Shiftig a biary umber left is equivalet to multiplyig by 2 Shiftig a biary umber right is equivalet to dividig by 2 Chapter 7 - Part 2 37 Serial Adder The circuit show uses two shift registers for operads A(3:) ad B(3:) A full adder, ad oe more flip flop (for the carry) is used to compute the sum The result is stored i the A register ad the fial carry i the flip-flop Serial I Serial I /Right Shift Registers A3 A2 A A Parallel B3 B2 B B Parallel A FA B Sum Ci Cout Q D (Clock ad /Shift Cotrol ot show) With the operads ad the result i shift registers, a tree of full adders ca be used to add a large umber of operads Used as a commo digital sigal processig techique CP Chapter 7 - Part 2 38 9
Terms of Use All (or portios) of this material 28 by Pearso Educatio, Ic Permissio is give to icorporate this material or adaptatios thereof ito classroom presetatios ad hadouts to istructors i courses adoptig the latest editio of Logic ad Computer Desig Fudametals as the course textbook These materials or adaptatios thereof are ot to be sold or otherwise offered for cosideratio This Terms of Use slide or page is to be icluded withi the origial materials or ay adaptatios thereof Chapter 7 - Part 2 39 2