DIGITAL CIRCUIT COMBINATORIAL LOGIC

DIGITAL CIRCUIT COMBINATORIAL LOGIC Logic levels: one zero true false high low CMOS logic levels: 1 => 0.7 V DD 0.4 V DD = noise margin 0 =< 0.3 V DD Positive logic: high = 1 = true low = 0 = false Negative logic: high = 0 = false low = 1 = true Slide 1

LOGIC LEVELS IN MOST POPULAR FAMILIES LOGIC LEVELS Slide 2

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Boolean algebra: the logical AND of A and B is denoted as the logical OR of A and B is denoted as the logical XOR of A and B is denoted as A B A + B A B the inverse of A is A and the inverse of B is B the logical NAND of A and B is denoted as the logical NOR of A and B is denoted as A B A + B Slide 4

Standard logic gates with truth tables Slide 5

NAND is an universal logic function: INVERTER AND Slide 6

DeMorgan s theorems: A B = A + B A + B = A B DeMorgan s theorems expressed symbolically Slide 7

AND Two-input diode gates Slide 8

A B OUT 0 0 1 0 1 1 1 0 1 1 1 0 Diode-transistor NAND gate including a simple LED logic-level indicator Slide 9

MOS inverter with resistive load. Input and output waveforms showing switching delay due to capacitor discharge. Slide 10

Schematic representation of a CMOS inverter Slide 11

Schematic representation of a CMOS NAND gate with LED logic level Slide 12

FLIP-FLOPS: SAVING A LOGIC STATE Timing diagram with timing definitions for rising-edge-triggered flip-flop (the rising edge of the clock signal causes the output to change while the falling edge of the clock signal has no effect on the flip-flop) Slide 13

*The state after LL input condition is removed depends on which input signal goes high first; if both go simultaneously, state is undefined Simple RS latch made of two-input NANDs with state table Slide 14

*The state after LL input condition is removed depends on which input signal goes high first; if both go simultaneously, state is undefined D-type flip-flop with state table Slide 15

Simple timing diagram for D-type flip-flop (positive-edge-triggered) Slide 16

Master-slave flip-flops Slide 17

Edge-triggered type D flip-flop Slide 18

J K Q n+1 0 0 Q n 0 1 0 1 0 1 1 1 Q n JK flip-flop (negative-edge-triggered) Slide 19

Toggling flip-flops Slide 20

Divide-by-four ripple counter Slide 21

Synchronous divide-by-four ripple counter Slide 22

Four-bit counter Slide 23

Looking at contact bounce by driving a divide-by-four counter from a switch (a NAND latch is used as debouncer) Slide 24

clock 0 or 1 gated clock Timing diagram for a gated clock signal (the gated signal is simply the logical NAND of the gate and clock signals) Slide 25

Substandard outputs can result when gating clock signals Slide 26

MULTIVIBRATORS Astable These circuits keep changing from one state to the other Bistable They are stable in both of their allowed states. The output state is the result of the input signal. Monostable This circuits have only a single stable state Slide 27