Volume-6, Issue-1, January-February-2016 International Journal of Engineering and Management Research Page Number: 577-581 Embedded Logic Flip-Flops: A Conceptual Review Sudhanshu Janwadkar 1, Dr. Mahesh T Kolte 2 1 ME Student, VLSI & Embedded Systems, Department of E&TC, MITCOE, Pune, INDIA 2 Department of E&TC, MITCOE, Pune, INDIA ABSTRACT With advancement in CMOS technology, a lot of research has been done to develop various logic styles to improve the performance of logic circuits. D flip-flops (DFF) are fundamental building blocks in almost every sequential logic circuit. Hence, in sequential logic circuits, the overall performance of the circuit is affected by the performance of constituent DFFs. In recent years, the focus has been towards incorporating higher clock rates in a processor for better performance. To achieve high clock rates, fine granularity pipelining techniques are used, which implies that there are relatively a fewer levels of logic in each pipeline stage. A major consequence of this design trend is that the pipeline overhead has becoming more significant. The primary cause of pipeline overhead is the latency of the flip-flop or latch used to design the processor and the clock skew of the system. This calls out for the need of incorporating the logic functionality within the architecture of flip-flop. The new family of flipflops are called Embedded Logic Flip Flops. In this Paper, we have reviewed various Flip-flop architectures which have been proposed so far. Our attempt is to do a qualitative analysis and comparison of the proposed Embedded logic flip-flop designs. Keywords---- Embedded Logic, Latency, Edge-Triggered Flip-flop, Power dissipation I. INTRODUCTION There has been a fundamental & gradual shift in CMOS design technology with the level of integration increasing from few thousands of transistors per chip (LSI) to billions of transistors on single chip(vlsi). The frequency of operation has also increased dramatically from Megahertz (MHz) to Gigahertz (GHz). This improvement in technology and speed has called out the need for evaluating the performance of the design in terms of chip area, delay and power dissipation. In synchronous logic circuits, high speed is achieved using pipeline architectures. In deep-pipelined architectures, for an improved speed-up factor, a lower pipeline overhead is desirable. The pipeline overhead is a outcome of the latency associated with the pipeline elements, such as latches and flip-flops. For example, Let us assume that in some particular state-of-the-art highspeed processor, the clock cycle is 20 gate delays. Let the latency of the flip-flops used to store result intermediately is three gate delays. Then, this would imply that the flipflop overhead amounts to 15% of the total cycle time. This flip-flop latency ultimately degrades the overall performance of the system, since no useful logic operation is performed on the data when it is being latched. Another important consequence of the above trend is that the number of flip-flops used in the system has increased exponentially from a few thousand flip-flops in early designs to several tens of thousands of flip-flops in recent designs [10].These facts clearly mark-out the importance of marginalizing the delay associated with Flip-flop in the design. There have been many methods proposed to eliminate the drawback of power consumption and latency. The current trend towards this direction has been to incorporate the logic functionality into the flip-flop. This new family of flip-flops are called Embedded Logic Flipflops. The concept of Embedded logic flip-flop is shown in Fig. 1. Embedded Logic Flip-Flop(ELFF) are simple high speed low-power flip-flop implementations compared to the discrete combinations of static logic and a flip-flop in the design.[11] The merging of the logic function into the architecture of the D FLip-flop would mean that we can eliminate one or more levels of logic from the path leading to the flip-flop. Also, logic operations can be performed on the data during the times it is stored idly in the Flip-flop memory. Fig 1: Concept of Embedded Logic Flip-flop 577 Copyright 2016. Vandana Publications. All Rights Reserved.
In this Review Paper, we have compared the pros and cons of various Embedded Logic Flip Flop architectures that have been proposed in past for Embedded Logic Flip-flops. II. LITERATURE SURVEY Various techniques have been proposed in past to optimize the chip area and delay time of sequential logic circuits. However, we would be concentrating on the designs and architectures which have focused on merging the Logic function into Flip-flops as the primary technique. Gerosa et al. s (1994) have proposed PowerPC 603 master-slave latch [1]. The PowerPC 603 Master slave latch was a static design. The architecture is shown in Fig 2. An obvious disadvantage of PowerPC 603 Master Slave is that, being a static design, it suffered from increased positive setup time. Despite all these shortcomings, the design offers a good low power solution when the speed is not a primary concern. Fig 3: Edge-Triggered Semi-dynamic Flip flop (Klass 1998) The primary requirements of a flip-flop in highspeed digital design are short latency and a simple & robust clocking scheme. Although, the design by Klass(1998) provided for short-latency, no considerations were done towards clocking scheme. Ashutos Das et al. (1999) proposed various Single-phase pulsed flip-flop with an aim of reducing the pipeline overhead. One such architecture is shown in Fig 4. This family of flip-flop uses true singlephase clocking (TSPC). These TSPC latches can be combined in various different ways to implement edgetriggered flip-flops. While their single clock phase is advantageous, a drawback of single-phase pulsed flip-flops is large latency[3]. Fig 2: PowerPC 603 master-slave latch (Gerosa et al. s 1994 ) Klass(1998) proposes Edge Triggered Semidynamic Flip-flop. The architecture of which is shown in Fig 3. The circuit was composed of a dynamic front-end and a static backend. Hence it was named semi-dynamic. This family of flip-flops result in shorter latency, reduced clock load and is a good interface between static and dynamic logic. Moreover, they eliminate one gate delay from the critical path. The architecture uses a NAND gate which allows the shutoff of the pull-down path to be conditioned to the state of input D. This feature allows the reduction of the sampling window by about one inverter delay[2]. In later developments, G. Lauterbach has used this architecture in design of Ultra-Sparc III microprocessor architecture. He reports that the design is capable of incorporating logic functions with minimum delay penalty. This makes them very attractive for high-performance microprocessor design.[3] Fig 4: Single Phase Pulsed Flip-flop (Ashutos Das et al. 1999) The next work in this regard was towards incorporating logic functions into the latches. Ashutosh Das et al.(1999) propose SDFF(Semi-Dynamic Dlip-Flop) to which complex logic functions can be added easily. In this SDFF approach, most of the logic functions particularly suitable for domino logic, such as wide OR functions, multiplexers, and complex gates, can be implemented easily. In this design, For an N-input function, N transistors are needed. This approach would eliminate one or more levels of logic from the path leading to the flip-flop. But, this would be at the cost of increased latency of the design[3]. In Fig 5, A SDFF with embedded logic function Y= (A+B) (C+D) (E+F) (G+H) is shown. 578 Copyright 2016. Vandana Publications. All Rights Reserved.
propose that the transistor count can be reduced by sharing the transistors[5]. Fig. 5: Embedded Logic SDFF (Ashutos Das et al. 1999) Redundant data transitions as well as large precharge capacitance account for the major source of power dissipation in the conventional Semi-dynamic Flip-flop designs. Bai-Sun Kong et al. (2001) propose Conditional Capture Flip Flops. The design is shown in Fig. 6. CCFF is a complete family of low-power flip-flops which achieve reduction in power dissipation by eliminating redundant transitions of the internal nodes. These flip-flops have a negative setup time. This results in smaller data-tooutput(d-q) latency and it overcomes clock skew-related cycle time loss. Bai-Sun Kong et al. (2001) report that CCFF can achieve power dissipation of around 67%, as compared to the conventional flip-flops[4]. Fig. 6: Conditional Capture Flip Flops (Bai-Sun Kong et al. 2001) However, the disadvantage of CCFF is the increased hold time requirement and D-Q delay (Data to Output Delay) of the flip-flop. This can be accounted on the presence of conditional structures in the critical path. Also, the additional transistors added to implement the conditional circuitry make the flip-flop design bulky and hence result in an increase in power dissipation at higher data activities. Further, Nikola Nedovik et al. (2002) propose Dual rail Dynamic Flip-Flop. The design is shown in Fig. 7. Similar to SDFF, the dual-rail DFF can also incorporate logic functions. Due to the complementary nature of the circuit, 2N transistors are needed to implement a function with N inputs. However, Nikola Nedovik et al. (2002) also Fig. 7: Dual rail Dynamic Flip-flop (N. Nedovik et al. 2002) The obvious disadvantage of this design is that, in cases where the embedded logic is too complex, there is a risk that the charge stored in intermediate nodes of the logic may affect the dynamic nodes after the other has been evaluated. This concept is called back charge sharing. A possible reason for back charge sharing is that one of the complementary paths in the flip-flop is always left open. Peiyi Zhao et al. (2004) propose Conditional Discharge Flip-Flop. In this technique, the switching activity (as in case of CCFF) is eliminated. In this design, when the input is high, the discharge path is disconnected. This can be viewed as a Conditional Discharge technique; hence the flip-flop being called Conditional Discharge Flip- Flop. Peiyi Zhao et al. (2004) report that; the CDFF can save up to 39% of the energy with the same speed as that for the fastest pulsed flip-flops[5]. During our Literature Survey we found that not much Research Work was done towards developing new architectures during the years 2005-2010. However, minor changes were done in existing designs to improve performance. Rasouli (2005) propose single and Double edge triggered Semi-dynamic Flip-flops for high speed Applications. In this design, The increase in the speed has been achieved by lowering the number of the stack transistors in the discharge path[6]. Chen Kong Teh et al. (2006) have added feature of Conditional Data Mapping to CDFF for designing Low-Power and performance systems. They have also compared various state of art designs for 50% PDP in their Research Work[7]. O. Sarbishei et al. (2007) states that Clock overlap is an important issue in the design of sequential circuits. They propose D flip-flop which benefits from the overlap period of the clock signal. The work is based on 0.18 m CMOS technology. In order to evaluate the performance of the proposed DFFs, a 16-bit shift register and a 3-bit pipeline adder have been designed using the DFFs by the researchers. They report a D-Q delay of 142 ps and Power consumption of 360.4 W [8]. O. Sarbishei et al. (2010) present several efficient architectures of dynamic/static edge-triggered flip flops with a compact embedded logic. These structures benefit from the overlap period and fix most of the drawbacks of 579 Copyright 2016. Vandana Publications. All Rights Reserved.
the dynamic logic family. This architecture has embedded a pull-down network (PDN) into the overlap-based DFF. The pull-down network can be any embedded Logic function such as LUT, Multiplexer, inverter etc. If the PDN is replaced by a single nmos transistor, the design operates as a single DFF. Further, O. Sarbishei et al. (2010) have constructed a 4-bit Shift Regsiter based on the design of flip-flop and compared their work with earlier existing state-of-art design[9]. The major advantage of the SDFF has been the capability to incorporate complex logic functions efficiently. Although SDFF has the potential of offering improved efficiency in terms of speed and area, but it does not consider the power consumption criterion. As discussed earlier, an efficient logic structure incorporating logic functions must consider all three viz. speed, area and power into account. In subsequent years, attempts are being made to design a flip-flop, which can incorporate logic efficiently in terms of all three; power, speed and area. Kalarikkal Absel et al. (2013) propose a Low- Power solution, Dual Dynamic Node Pulsed Flip-Flop with efficient embedded logic. The design is shown in Figure 9. This design incorporates a PDN driven by the data-input instead of a transistor doing similar job. Due to this, charge sharing issue is also addressed to a great extent which otherwise becomes a serious issue when large logic is embedded in the design[10]. 3. In chip Design, scan circuitry can be added to the basic flip-flop design with nearly zero hit in performance IV. CONCLUSION In this Review Paper, we have studied various Flip-flop architectures with embedded logic in the design. We have attempted to identify the advantage and disadvantage of each design. The static designs offer a good alternative when speed is not a concern. Semidynamic & Dynamic Flip flop architectures such SDFF, DDFF, DRFF etc can incorporate logic structures efficiently into the designs but they yield poor performance in terms of power dissipation. Conditional Charging/discharging Flip-flop are efficient when it comes to delay and power consideration. However, their performance degrades if large logic structures are embedded into the design. So far, The Dual Dynamic Node Hybrid Flip-flop designs seem to offer the best performance when all the three performance parameters i.e area(or, number of transistors), power dissipation and speed(ie delay considerations) are considered. We conclude that there is still a lot of scope for research work to be done towards developing more efficient flip-flop designs incorporating logic functions. Design of memories and processors using such Embedded- Logic flip flops would optimize the on-chip area, delay & power consumption and hence improve the overall performance of the sequential circuits. REFERENCES Fig 9: Low-Power Dual Dynamic Node Pulsed Hybrid Flip-Flop (Absel et al. 2013) III. APPLICATIONS OF EMBEDDED LOGIC FLIP FLOPS 1. In complex DSP processors, pipeline latencies are a major issue. The partial result of a complex operation is stored in memory temporarily till the entire operation is completed. The result of this complex operation might be used by a simple operation. Incorporating the simple logic functionality into the memory would reduce the total delay. 2. These flip-flop architectures can be used for design of shift-register, memory, LFSR etc. Perofrmance improvement in terms of Power, Area and Delay is an advantage. [1] G. Gerosa, S. Gary, C. Dietz, P. Dac, K. Hoover, J. Alvarez, H. Sanchez, P. Ippolito, N. Tai, S. Litch, J. Eno, J. Golab, N. Vanderschaaf,and J. Kahle, A 2.2 W, 80 MHz superscalar RISC microprocessor, IEEE Journal of Solid- State Circuits, vol. 29, no. 12, pp. 1440 1452, Dec.1994. [2] Fabian mass, Semi-Dynamic and Dynamic Flip-FLops with Embedded Logic, Sun Microsystems Inc. Palo Alto, CA 94303 USA [3] Ashutosh Das, Fabian Klass, Chaim Amir, Kathirgamar Aingaran, Cindy Truong, Richard Wang, Anup Mehta, Ray Heald, and Gin Yee, A New Family of Semidynamic and Dynamic Flip-Flops with Embedded Logic for High- Performance Processors, IEEE Journal Of Solid-State Circuits, Vol. 34, No. 5, May 1999 [4] Bai-Sun Kong, Sam-Soo Kim, and Young-Hyun Jun, Conditional-Capture Flip-Flop for Statistical Power Reduction, IEEE Journal of Solid-State Circuits, VOL. 36, NO. 8, AUGUST 2001 1263 [5] Peiyi Zhao Tarek K. Darwish, Magdy A. Bayoumi,, High-Performance and Low-Power Conditional Discharge Flip-Flop, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 12, No. 5, May 2004 477 [6] C. K. Teh, M. Hamada, T. Fujita, H. Hara, N. Ikumi, and Y. Oowaki, Conditional data mapping flip-flops for low-power and high performance systems, IEEE Trans. Very Large Scale Integr. (VLSI) Syst.,vol. 14, no. 12, pp. 1379 1383, Dec. 2006. 580 Copyright 2016. Vandana Publications. All Rights Reserved.
[7] S. H. Rasouli, A. Khademzadeh, A. Afzali-Kusha, and M. Nourani, Low-power single- and double-edgetriggered flip-flops for high-speed applications, Proc. Inst. Elect. Eng. Circuits Devices Syst., vol. 152, no. 2, pp. 118 122, Apr. 2005. [8] O. Sarbishei and M. Maymandi-Nejad, Power-delay efficient overlap based charge-sharing free pseudo-dynamic D flip-flops, in Proc. IEEE Int. Symp. Circuits Syst., May 2007, pp. 637 640. [9] O. Sarbishei and M. Maymandi-Nejad, A novel overlap-based logic cell: An efficient implementation of flip flops with embedded logic, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., Vol. 18, no. 2, pp. 222 231, Feb. 2010. [10] KalarikkalAbsel,Lijo Manuel, R. K. Kavitha. Low- Power Dual Dynamic Node Pulsed Hybrid Flip-Flop Featuring Efficient Embedded Logic. In IEEE Transactions. VLSI Syst. 2013; vol.21; no.9; [11] Sudheer A, AjithRavindran Design and Implementation of Embedded Logic Flip-Flop for LowPower Applications Science Direct, Procedia Computer Science 46 ( 2015 ) 1393 1400 [12] Ms.Rashmi Patil, Dr. M.T.Kolte, Low Area Power - Aware FIR Filter for DSP International Journal of Engineering and Technical Research (IJETR) Vol. 2, Iss9, Sep 2014 581 Copyright 2016. Vandana Publications. All Rights Reserved.