Sequential ircuit esign: Part 1 esign of memory elements Static latches Pseudo-static latches ynamic latches Timing parameters Two-phase clocking locked inverters Krish hakrabarty 1 Sequential Logic FFs LOGI Out t p,comb In 2 storage mechanisms positive feedback charge-based Krish hakrabarty 2
ombinational logic Sequencing output depends on current inputs Sequential logic output depends on current and previous inputs Requires separating previous, current, future alled state or tokens Ex: FSM, pipeline clk clk clk clk in L out L L Finite State Machine Pipeline Krish hakrabarty 3 Sequencing ont. If tokens moved through pipeline at constant speed, no sequencing elements would be necessary Ex: fiber-optic cable Light pulses (tokens) are sent down cable Next pulse sent before first reaches end of cable No need for hardware to separate pulses But dispersion sets min time between pulses This is called wave pipelining in circuits In most circuits, dispersion is high elay fast tokens so they don t catch slow ones. Krish hakrabarty 4
Sequencing Overhead Use flip-flops to delay fast tokens so they move through exactly one stage each cycle. Inevitably adds some delay to the slow tokens Makes circuit slower than just the logic delay alled sequencing overhead Some people call this clocking overhead But it applies to asynchronous circuits too Inevitable side effect of maintaining sequence Krish hakrabarty 5 Sequencing Elements Latch: Level sensitive a.k.a. transparent latch, latch Flip-flop: edge triggered A.k.a. master-slave flip-flop, flip-flop, register Timing iagrams Transparent Opaque Edge-trigger clk (latch) clk Latch clk Flop (flop) Krish hakrabarty 6
Flip-Flop: Timing efinitions t In t setup t hold ATA STABLE t Out t pff ATA STABLE t Krish hakrabarty 7 Maximum lock Frequency FFs LOGI t p,comb Krish hakrabarty 8
Latch esign Pass Transistor Latch Pros + Tiny + Low clock load ons V t drop nonrestoring backdriving output noise sensitivity dynamic diffusion input Used in 1970 s Krish hakrabarty 9 Latch esign Transmission gate + No V t drop - Requires inverted clock Krish hakrabarty 10
Latch esign Inverting buffer +Restoring + No backdriving + Fixes either Output noise sensitivity Or diffusion input Inverted output Krish hakrabarty 11 Latch esign Buffered input + Fixes diffusion input + Noninverting Krish hakrabarty 12
Latch esign Buffered output + No backdriving Widely used in standard cells + Very robust (most important) - Rather large - Rather slow (1.5 2 FO4 delays) - High clock loading Krish hakrabarty 13 Latch esign Tristate feedback + Static Backdriving risk Static latches are now essential Krish hakrabarty 14
Latch esign atapath latch + Smaller, faster - unbuffered input Krish hakrabarty 15 esign of Memory Elements Positive edge-triggered flip-flop Why use inverters on outputs? Skew Problem : may be delayed with respect to (both may be 1 at the same time) This is what happens- Eliminating/Reducing skew: in 1 Transmission gate acts a buffer, should have same delay as inverter Krish hakrabarty 16
Latch design Static latch Jamb latch Weak inverter Krish hakrabarty 17 Latch esign Variant of latch Krish hakrabarty 18
Flip-Flop esign Flip-flop is built as pair of back-to-back latches Krish hakrabarty 19 Enable Enable: ignore clock when en = 0 Mux: increase latch - delay lock Gating: increase en setup time, skew Symbol Multiplexer esign lock Gating esign en Latch 1 0 Latch Latch en en en Flop 1 0 en Flop Flop en Krish hakrabarty 20
Reset Force output low when asserted Synchronous vs. asynchronous Symbol Latch Flop Synchronous Reset Asynchronous Reset Krish hakrabarty 21 Set / Reset Set forces output high when enabled Flip-flop with asynchronous set and set set Krish hakrabarty 22
ynamic Latches So far, all latches have been static-store state when clock is stopped but power is maintained ynamic latches reduce transistor count Eliminate feedback inverter and transmission gate Latch value stored on the capacitance of the input (gate capacitance) Krish hakrabarty 23 ynamic Latch and Flip-Flop ynamic latch ata stored as harge on gate capacitance ynamic negative edge-triggered flip-flop ifficult to ensure reliable operation Similar to RAM Refresh cycles are required Krish hakrabarty 24
harge-based Storage Non-overlapping clocks Schematic diagram Ps e udo -s tatic Latc h Krish hakrabarty 25 Master-Slave Flip-Flop A B Overlapping locks an aus e Race onditions Undefined Signals To reduce skew: generate complement of clock within the cell Extra inverter per cell Krish hakrabarty 26
Two-Phase locking Inverting a single clock can lead to skew problems Employ two non-overlapping clocks for master and slave sections of a flip-flop Also, use two phases for alternating pipeline stages Krish hakrabarty 27 Two-Phase locking 1 2 1 2 1 (t). 2 (t) = 0 1 =1, 2 = 0 1 =0, 2 = 1 Krish hakrabarty 28
2-phase non-overlapping clocks Pseudo-static flip-flop 1 2 2 1 1 2 t Important: Non-overlap time t must be kept small Krish hakrabarty 29 2-phase dynamic flip-flop 1 2 Input Sampled 1 2 Output Enable Krish hakrabarty 30
Flip-flop based on nmos pass gates Use of p Leakers 1 2 egraded voltage V -V t No need to route signals 1 2 Problem: Increased delay (extra inverter) pmos leaker transistors provide full-restored logic levels Krish hakrabarty 31 locked Inverters Similar to tristate buffer = 1, acts as inverter = 0, output = Z i1 i2 i3 Latch Krish hakrabarty 32
Flip-flop insensitive to clock overlap V V M2 M6 In M4 M8 M3 L1 M7 L2 M1 M5 section section 2 MOS flip-flop Krish hakrabarty 33 2 MOS avoids Race onditions V V V V M2 M6 M2 M6 In 1 M3 1 M7 In 0 M4 0 M8 M1 M5 M1 M5 (a) (1-1) overlap (b) (0-0) overlap Krish hakrabarty 34