Virtex-II Pro and VxWorks for Embedded Solutions Systems Engineering Group
Embedded System Development
Embedded Solutions Key components of Embedded systems development Integrated development environment (IDE: example TornadoII) Real Time Operating System (RTOS: example VxWorks) Board Support Package (BSP) System Image (example VxWorks image) Bootloader (bringing up the OS) Dynamic Linking of software modules Critical files and structure for embedded development 3
Embedded Solutions CF: local NV Storage Embedded System Bus JTAG Network Target Serial PPC Single Board Computer (SBC) Host Development Platform & IDE System Nodes & Applications / Plug in Modules 4
Integrated Development Environment (IDE) An IDE provides and enables the following: An Integrated Cross Development and Debug Environment for Embedded Systems (for example Tornado II / VxWorks) Rapid Prototyping Scalable Real Time OS Application Development (Post Board Bring-Up) Host Based Tools (Host Shell, Info Browser) Dynamic Download Produces VxWorks System Images Dynamically loadable software object modules Bootloader 5
RTOS & BSP Real Time Operating System - Scalability RTOS provides a deterministic task manager and inter-task communication facilities for embedded application development Core OS functionality is abstracted from the particular target architecture used. Thus providing a scalable system solution across multiple platforms Board Support Package (BSP)- Platform independence The BSP is the glue logic that is used to tie the hardware to the OS. Providing platform independence to the OS The platform abstraction of the BSP provides the OS with the necessary details of the underlying hardware through standard interface functions 6
VxWorks Real Time Kernel Fast and Deterministic Lightweight tasking model Minimal time in Kernel mode Scalable You only ship what you need Portable Across Microprocessor families API consistent across architectures Memory Management Task Management Semaphores Intertask Communications Interrupt Support System Clock 7
Tornado-II IDE Workspace Editor Projects Source *.c, *.cpp Header *.h 8
System Image The system image is a bootable set of core OS functionality customized from a base BSP. Tornado-II Integrated Development Environment (IDE) produces VxWorks system images. At compile time, the system image is defined by components included or excluded during the system build process Application code may be built into the system image at compile time Applications may later be upgraded using a loader that dynamically loads and unloads software modules on top of a running VxWorks system. 9
Dynamic Linking Memory Management Semaphores Interrupt Support Memory Management Semaphores Interrupt Support Task Management System Clock Intertask Communications SW_MOD A system image, based on the included set OS functionality and built-in application code is produced at compile time. DYNAMICALLY LOAD DYNAMICALLY UNLOAD Task Management System Clock Intertask Communications System Image A running VxWorks system can be upgraded via a dynamic linker loader Loads and unloads your compiled source code, while your target is running This allows you test out your application code one module at a time on top of an existing vxworks image. SW_MOD System Image 10
VxWorks Configuration Driver selection, Tunable parameters Application selection 11
Methods of Bringing Up an Embedded System Board Bring-Up Cable: Development & Debug w/ JTAG cable to deliver ELF software image and a Debug path into Processor (WRS VisionProbe-II) Boot ROM Delivery of system image from onboard non-volatile storage and booting VxWorks Bootloader Retrieve system image over the network Retrieve system image from local non-volatile storage (eg. CF) Launch system image from RAM RAM Network NTWK CPU ROM JTAG 12
Embedded System Upgrade Loading and Running an Application Local access of application in non-volatile storage Remote access of application over Network Run RAM resident application Network NTWK CPU JTAG RAM ROM 13
Embedded Development Files Expected files for embedded development VxWorks System Image ( ELF) Dynamically Linkable Software Modules ( ELF ) Bootloader ( ELF ) (ELF - Executable and Linkable Format) 14
Directory Structure In summary there are three main file types we have discussed that will be needed for our embedded solution development System image Software module Bootloader IMAGES (ELF Format) vxworks3 vxworks2 File System vxworks1 VXWORKS (Software) bootloader MODULES (ELF Format) sw_mod2.out sw_mod1.out 15
VxWorks Virtex-II Pro & System ACE-CF
Evolution of Embedded Solutions CF: local NV Storage Embedded System Bus JTAG Network Target Serial PPC Single Board Computer (SBC) Host Development Platform & IDE System Nodes & Applications / Plug in Modules 17
Evolution to Virtex-II Pro (Scalable System Solution) PPC405GP SBC PPC Single Board Computers (SBCs) Host Development Platform Backplane and Embedded System Bus PPC750 SBC 18
Embedded Development Platform (Rapid Prototyping) ML3 ML2 PPC405 SBCs ML300 & Virtex-II Pro ML1 19
Virtex-II Pro & System ACE-CF (Evolution of Embedded Solutions) JTAG Development and Debug Host Network JTAG TST Serial CF JTAG CFG Embedded Microprocessor 0 7 1 6 2 5 3 4 Reset CFG ADDR MPU GPIO Serial VT100
System ACE-CF Solution Board Bring-Up Cable via ACE-CF JTAG TST port: Development & Debug w/ JTAG cable to deliver ELF software image and a Debug path into Processor (WRS VisionProbe-II) Boot ROM ACE-CF JTAG delivery of system image from CF and booting VxWorks (eg JTAG cable like) Bootloader: Retrieve system image over the network Retrieve system image from CF via ACE MPU port Launch system image from RAM RAM Network NTWK CPU System ACE & CF JTAG TST JTAG 21
System ACE-CF Solution Loading and Running an Application Local access of application in CF Remote access of application over Network Run RAM resident application Network NTWK CPU JTAG RAM System ACE & CF JTAG TST 22
ML300 Embedded Development Platform Management of System Upgrade External RAM PHY MAC IPIF RJ45 IPIF Serial Port IPIF PPC IPIF MPU BRAM ML300 & Virtex-II Pro GPIO JTAG 0 7 1 6 2 5 3 4 CF CF CFG ADDR, Reset TST_JTAG MPU CFG_JTAG 23
Embedded Solution Comparison Network Network NTWK NTWK CPU JTAG CPU JTAG RAM System ACE & CF JTAG TST RAM ROM 24
Virtex-II Pro and System ACE RJ45 PHY Network MAC IPIF Serial Port IPIF NTWK External RAM IPIF PPC CPU JTAG IPIF MPU GPIO BRAM JTAG RAM System ACE & CF JTAG TST 0 7 1 CF CF CFG ADDR, Reset TST_JTAG MPU CFG_JTAG 6 2 5 3 4 25
Initial System Bring up System bring up from power on or system reset Multiple switch selectable configurations Hardware and SW boot FPGA configuration System ACE-CF loading system image and booting VxWorks ACE via JTAG loads system image from CF and boot VxWorks System ACE-CF bootloader Retrieve system image from CF via ACE MPU port & boot VxWorks 26
PPC Controlled Self Upgrade Virtex-II Pro self upgrade using System ACE-CF MPU port control of System ACE-CF by the PPC Hardware and SW upgrade FPGA configuration System ACE-CF loading system image and booting VxWorks ACE via JTAG loads system image from CF and boot VxWorks System ACE-CF bootloader Retrieve system image from CF via ACE MPU port & boot VxWorks 27
PPC Controlled Self Upgrade Virtex-II Pro self upgrade using System ACE-CF (contd) Load a new software module Dynamically link a new software module with VxWorks The OS stays up during this process Partial Reconfiguration of Virtex-II Pro ACE controlled update from CF via JTAG ACE file moved from CF via MPU port to RAM.ACE file played over MPU to JTAG under PPC control OS stays up during partial reconfiguration 28
System ACE-CF for Embedded Solutions
Directory Structure System ACE-CF can support the bring up capability and file structure expected in embedded systems System image Software module Bootloader XILINX.SYS. XILINX vxboot.ace System ACE Supported Local File System IMAGES (ELF Format) VXWORKS (Software) MODULES (ELF Format).out.out.out.out 30
System ACE-CF and Embedded Solutions System ACE can boot a software system image as expected in embedded systems And More Configure Virtex-II Pro or any Xilinx FPGA Load hardware IP as well as software IP from single ACE file Offers an MPU interface for application software configuration of FPGAs using ACE files Provides a Microdrive or Compact Flash based Local File System for non-volatile storage Provides a JTAG test port for test, debug an integration with embedded system development tools 31
Xilinx.sys Controlled Tree System ACE automatic configuration controller uses the.ace files located in the Xilinx.sys tree XILINX.SYS XILINX System ACE Supported Local File System VXWORKS (Software) vxboot.ace IMAGES (ELF Format) MODULES (ELF Format)..out.out.out.out 32
What s an.ace File and what does System ACE -CF do?.ace files are a Xilinx Proprietary binary SVF file format (Serial Vector Format) System ACE -CF contains an.ace file player that is used to play out JTAG commands/data.ace files can contain any combination of H/W and or S/W FPGA configuration data by converting a.bit to.ace PPC code/data by converting a.elf file (Executable and Linkable Format) to.ace 33
Xilinx.sys Controlled File Structure XILINX.SYS System ACE Supported Local File System dir = XILINX; cfgaddr0 = bootload; cfgaddr1 = xrom; cfgaddr2 = linux; cfgaddr3 = vxboot; cfgaddr4 = quake; cfgaddr5 = v2pdraw; cfgaddr6 = tictac; cfgaddr7 = vxworks; XILINX bootload xrom.ace.ace linux vxboot.ace.ace quake v2pdraw.ace tictac.ace vxworks.ace.ace 34
Options for.ace File Content HW (.bit) only.ace file Only the FPGA is configured A.bit file may contain SW targeted for BRAM via DATA2BRAM utility SW (.elf) only.ace file PPC is single stepped to load the SW into memory Assumes FPGA is configured and PPC is connected Combined HW (.bit) and SW (.elf).ace file Loads your HW and SW in a single.ace file 35
System ACE-CF File System Requirements ACE-CF can only access a DOS FAT12/16 file system ACE-CF requires a file named xilinx.sys at the root directory The xilinx.sys file describes one collection directory with up to 8 sub-dirs with each containing one or no.ace file All directories accessed by ACE -CF must be valid FAT 8.3 format 8.3 format does not apply to.ace file names Other directories and files may coexist on the CF Disk 36
Combined Local File System System ACE Supported Local File System It s Just a Disk! XILINX.SYS XILINX VXWORKS (Software) SCRIPTS (Utils) PR_ACE (Bitstreams) bootload xrom.ace.ace IMAGES linux (ELF Format) vxboot.ace.ace quake v2pdraw.ace.ace tictac vxworks.ace.ace MODULES (ELF Format).out.out.out.out.ace.ace.bit.bit 37
Directory Structure It s Just a Disk! 38
Virtex-II Pro and JTAG
V2P Combined JTAG Chains Using the JTAGPPC Block Integrates the PPC405 with the FPGA Fabric JTAG chain (dedicated JTAG pins) The combined chain supports development and debug tools ChipScope Pro (PC4) impact (PC4) GDB (PC4) SingleStep XE (visionprobeii) User Defined JTAG Pins on FPGA TDO TDI CPU JTAG Debug Port JTAG Config Port PPC 405 JTAGPPC Fixed JTAG Pins on FPGA 40
V2P Split JTAG Chains User defined JTAG Pins Provides a direct and isolated connection to the PPC405 JTAG I/F JTAGPPC block is not used in this configuration The isolated chain supports embedded development and debug tools User Defined JTAG Pins on FPGA CPU JTAG Debug Port TDO TDI JTAG Config Port PPC 405 Fixed JTAG Pins on FPGA 41
ML300 Reference Design How to hook up System ACE-CF
System ACE-CF & Virtex-II Pro JTAG Config & Debug Port 3.3V CPU JTAG Debug Port 2.5V Compact Flash 2.5V 33 MHz CF POR_RESET POR_BYPASS POR_TEST CFGMODE CLK TCK RESET CFGADDR[2:0] TST_JTAG MPU STAT& ERR LEDs VCCH VCCL CFPROG CFINIT 3.3V 2.5V CFG_JTAG TDO 2.5V JTAG CPU_TDI CPU_VCC 2.5V 405 2.5V G_CLK [ GPIO 43
System ACE and Virtex-II Pro ML300 The JTAG Bus to program the FPGA Fabric JTAG Config & Debug Port 3.3V Compact Flash 2.5V 33 MHz CF POR_RESET POR_BYPASS POR_TEST CFGMODE CLK TCK RESET CFGADDR[2:0] TST_JTAG MPU STAT& ERR LEDs VCCH VCCL CFPROG CFINIT 3.3V 2.5V CFG_JTAG TDO ML300 Schematic Rev B. pg. 3 of 55 Mode Switches for SysACE File selection 44
System ACE and Virtex-II Pro ML300 Access the JTAG Config port from one of three connectors JTAG Config & Debug Port 3.3V Compact Flash 2.5V 33 MHz CF POR_RESET POR_BYPASS POR_TEST CFGMODE CLK TCK RESET CFGADDR[2:0] TST_JTAG MPU STAT& ERR LEDs VCCH VCCL CFPROG CFINIT 3.3V 2.5V CFG_JTAG TDO ML300 Schematic Rev B. pg. 3 of 55 45
JTAG Connectors ML300 Three JTAG Connectors: P115 - Fixed JTAG pins only P114 and P109 - Fixed or User JTAG With the Jumper off, WRS VisionProbe can access the Fixed JTAG pins on P114 With the jumper connected, connect PC4 Cable to P115 to access Fixed JTAG Pins ML300 Schematic Rev B. pg. 3 of 55 46 P109 is a Mictor connector for use with the WRS Vision Probe
JTAG CPU Debug Port CPU JTAG Debug Port 2.5V ML300 CPU Debug Port allows direct access to User JTAG pins [ CPU_TDI CPU_VCC 2.5V 405 2.5V JTAG 2.5V G_CLK ML300 Schematic Rev B. pg. 3 of 55 47
System ACE MPU Port ML300 JTAG Config & Debug Port 3.3V CPU JTAG Debug Port 2.5V TCK POR_RESET POR_BYPASS POR_TEST TST_JTAG VCCH 3.3V CPU_TDI CPU_VCC. Ã[ Ã CF CFGMODE CLK RESET CFGADDR[2:0] MPU STAT& ERR LEDs VCCL CFPROG CFINIT 2.5V CFG_JTAG TDO 2.5V JTAG 2.5V 405 2.5V G_CLK ML300 Schematic Rev B. pg. 17 of 55 48
System ACE & Compact Flash ML300 JTAG Config & Debug Port 3.3V Compact Flash 2.5V CF TCK POR_RESET POR_BYPASS POR_TEST TST_JTAG VCCH VCCL 33 MHz CFGMODE CLK RESET CFGADDR[2:0] MPU STAT& ERR LEDs CFPROG CFINIT ML300 Schematic Rev B. pg. 27 of 55 49