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University of Florida EEL 3701 Fall 2012 Dr Eric M Schwartz Page 1/11 Exam 2 Instructions: Turn off all cell phones, beepers and other noise making devices Show all work on the front of the test papers Box each answer If you need more room, make a clearly indicated note on the front of the page, "MORE ON BACK", and use the back The back of the page will not be graded without an indication on the front You may not use any notes, HW, labs, books, or calculators This exam counts for 20% of your total grade Read each question carefully and follow the instructions You must pledge and sign this page in order for a grade to be assigned The point values for problems may be changed at prof s discretion Truth tables and voltage tables must be in counting order Label the inputs and outputs of each circuit with activation-levels For each mixed-logic circuit design, equations must not be used as replacements for circuit elements Label inputs of each gate with the appropriate logic equations Boolean expression answers must be in lexical order,( ie, /A before A, A before B, & D 3 before D 2) Good Evening! Welcome! Good luck & Go Gators!!! For K-maps, label each grouping with the appropriate equation Put your name at the top of this test page (and, if you remove the staple, all others) Be sure your exam consists of 11 distinct pages Sign your name and add the date below PLEDGE: On my honor as a University of Florida student, I certify that I have neither given nor received any aid on this examination, nor I have seen anyone else do so SIGN YOUR NAME DATE (7 November 2012) Regrade comments below: Give page # and problem # and reason for the petition Page 2-3 15 16 5 13 6-7 22 8 12 9-11 22 TOTAL 100 Available Points

University of Florida EEL 3701 Fall 2012 Dr Eric M Schwartz Page 2/11 Exam 2 [15%] 1 Design a system that sequences through the following outputs: A16, 216, E16, A16, 216, E16, etc 3 min The system must asynchronously reset to output the A16 when Start (active-high) goes true When the sequence output is E16, the active-low output Z should be true Use a JK-FF for the most significant bit of the design, a T-FF for the least significant bit, and a D-FF for any other bits you might need Note: All the given FFs have active-low asynchronous clear and set inputs Use the minimum number of flip-flops and then try to minimize the number of SSI gates necessary to solve this problem (No MSI gates, PLDs, or ROMs allowed) 5 min a) Complete the next-state truth table You may not need all the rows and/or columns 5 min b) Find the required simplified (MSOP or MPOS) equations

University of Florida EEL 3701 Fall 2012 Dr Eric M Schwartz Page 3/11 Exam 2 5 min 1 c) Design the complete circuit, minimizing the total number of components, but using the JK-FF and T-FF (and D-FF(s), if necessary) as described previously All inputs and outputs of the circuit should be clearly indicated coming into or out of the below box Your design must include the circuitry necessary to asynchronous re-start the system at output A16 when the Start (active-high) signal goes true and show the active-low output Z (which is true when the output is E16) Inputs Outputs

University of Florida EEL 3701 Fall 2012 Dr Eric M Schwartz Page /11 Exam 2 [6%] 2 Answer the following questions about a state machine designed with one EEPROM, one J-K flip, one T flip-flop, and any other necessary flip-flops of type D (3%) a) What is the size of the EEPROM [addresses x data bits] if the state machine has 2 inputs, 3 outputs, and 5 states? Provide numbers only, ie, 37 9, NOT expressions like 3 7 3 min 37 (3%) b) What is the size of the EEPROM [addresses x data bits] if the state machine has 1 input, 1 output, and 9 states? Provide numbers only, ie, 37 9, NOT expressions like 3 7 3 min 37 [3%] 3 Write the complete VHDL equation for the following: 2 min R = /O + S * /( C + O * /E) [7%] Answer the following questions (2%) a) When creating a Moore state machine, do we need a debounced switch circuit? 1 min Why or why not? Yes No (circle one) (2%) b) When creating a Mealy state machine, do we need a debounced switch circuit? 1 min Why or why not? Yes No (circle one) (3%) c) Can a D-FF be used in a debounced switch circuit design? Yes No (circle one) 1 min If so, how? If not, why?

University of Florida EEL 3701 Fall 2012 Dr Eric M Schwartz Page 5/11 Exam 2 [5%] 5 Draw a complete circuit diagram including min two switch circuits, one for an active-high input signal, X(H) and one for an active-low input, Y(L) These switch circuits are used for the inputs of a 2-input OR gate with bubbles at the inputs and output (ie, a BNOR gate) Draw the switches in their true positions Draw an LED circuit at the output of this gate for the active-low output, W(L) Do NOT draw a layout What is the equation of the circuit that you have drawn? [8%] 6 Draw an ASM chart for the following potential description for the 2013 RoboBoat 12 min Competition Wait and listen for the start gun to sound (which is detected with the Start sound detector) Until the start gun sounds, output a Red light When the start gun is heard, utilize the camera (by looking at the red and green buoys) to execute the Slalom maneuvers Continue to slalom until the camera detects the blue balloon (BB) When the blue balloon is spotted, immediately display I see it on the Display and then begin the ramming stage (with no special additional outputs) Continue to display I see it and drive into the blue balloon until it is popped (which is detected with the Pop sound detector) After the balloon is popped, search for a Fire (with the fire detection circuit) while playing the Siren When the fire is detected, immediately turn off the Siren Then shoot water on the fire by turning on the bilge Pump until the fire is no longer detected Then turn off the pump, output a Green light, and repeat (ie, listen for the Start gun to sound) Inputs: Output: Start, BB, Fire, Pop Red, Slalom, Display, Pump, Siren, Green

University of Florida EEL 3701 Fall 2012 Dr Eric M Schwartz Page 6/11 Exam 2 D Data Bits D 0 $E0 $E0 [22%] 7 Given as many 16x EEPROMs as needed and as many 16x8 SRAMs as needed, design the 3 min memory module described below, with an active-low chip enable, CE The device should begin with 16x8 of EEPROM and then immediately follow with 32x8 of SRAM The entire memory must start at address $E0 and the first address of the 32x8 of SRAM must immediately follow the last EEPROM address Assume another module uses addresses 0 through $DF and no more memory will be added later Add the minimum number of memory devices and the minimum number of additional SSI components required (No other MSI or LSI components are allowed) ( %) a) Draw vertical and horizontal lines in the box below and label each resulting box with the 5 min memory type and size, using only the defined types and sizes given above Also, fill in the subscript on the D at the top left and the maximum address at the bottom right Increasing Addresses = max address ( %) b) What is the address and data ranges for each of the memory components drawn above (in binary and in hex)? 5 min 16x EEPROM(s): 16x8 RAM(s):

University of Florida EEL 3701 Fall 2012 Dr Eric M Schwartz Page 7/11 Exam 2 ( %) 7 c) Design the required memory device circuit diagram below Add the minimum number 5 min of additional memory components and SSI gates necessary (no MSI gates, LSI gates or PLDs) Add address subscripts as needed and cross out unneeded address and data pins Use labels instead of wires for the design Also, write the equations for each CS at the bottom of the page Show all connections with either labels or wires (labels are preferred), just as in Quartus Don t forget the system s active-low chip enable, CE D 0 D 1 D 2 D 3 D D 5 D 6 D 7 D 8 D 9 D 10 D 11 Equations:

University of Florida EEL 3701 Fall 2012 Dr Eric M Schwartz Page 8/11 Exam 2 [12%] 8 Use the below circuit diagram and the ROM contents table to the right to solve 3 min this problem Note that the addresses in the table are in octal [base 8] and the values in the table are in hex [base 16] (This problem is very similar to a problem in homework 8 that was also done in class) Note that one of the flip flops is a T-FF (10%) a) Derive the ASM chart for this circuit Show ALL work, ie, use at least part of the below blank table (Do not miss part b below) 10 min X(H) Q1 Q0 A2 A1 A0 8 x 5 ROM D3 D2 D1 D0 T1 D0 T D Q Q Q1 Q0 Y1(H) Y0(H) Contents of the ROM Addr Value Octal Hex 0 3 1 2 A 3 2 5 3 6 7 7 5 37 (2%) b) Assume that after building the circuit, you find that the D3 output of the ROM is bad, 2 min ie, the connection to D3 is broken Generate the simplified (MSOP or MPOS) equation and circuit diagram for the new Y1

2 min INPUT Bus University of Florida EEL 3701 Fall 2012 Dr Eric M Schwartz Page 9/11 Exam 2 REGA Bus REGB Bus OUTPUT Bus MSA1 MSA0 REGA Bus Cin MSC2:0 3 MUX A s REG A MUX B s REG B Combinatorial Logic MUX C s MSB1 MSB0 REGB Bus Cout OUTPUT Bus MSC MSA1:0/ MSB1:0 [22%] 9 A block diagram of your lab 6 is shown here, along with two tables from the same handout Use proper default values for MSA, MSB, and MSC, as done in lab 6 Bus Selected as Input to Combinatorial Logic 00 INPUT Bus 01 REG A Bus 10 REG B Bus 11 Output Bus Action 000 REGA Bus to OUTPUT Bus 001 REGB Bus to OUTPUT Bus 010 complement of REGA Bus to OUTPUT Bus 011 bit wise AND REGA/REGB to OUTPUT Bus 100 bit wise OR REGA/REGB Bus to OUTPUT Bus 101 sum of REGA Bus & REGB Bus to OUTPUT Bus 110 shift REGA Bus left one bit to OUTPUT Bus 111 shift REGA Bus right one bit to OUTPUT Bus without sign extension (3%) a) Assume that you can add a small additional circuit to determine when there would be an min overflow when addition is used (output is V) (This circuit should always work, whether you are adding or not, just as Cout always works) Design this circuit Show ALL your work Assume all signals are active-high

University of Florida EEL 3701 Fall 2012 Dr Eric M Schwartz Page 10/11 Exam 2 (%) 9 b) Use the table below to determine (with this RALU from lab 6) the average of 3 and 7 5 min (Your algorithm should still work for any two unsigned numbers with a sum of less than 15) Store the result in register B Describe what is accomplished in each step Use the minimum number of clock cycles Give appropriate values for ALL signals 1 2 3 5 6 7 # MSA MSB MSC Input Cin RegA RegB Output Cout RegA+ RegB+ Output+ Cout+ 1 0000 0000 2 3 5 6 7 (%) c) Use the table below to SUBTRACT $3 from $7 (Your algorithm should still work even 5 min if the two numbers are changed) Store your solution in register B Describe what is accomplished in each step Use the minimum number of clock cycles Give appropriate values for ALL signals 1 2 3 5 6 7 # MSA MSB MSC Input Cin RegA RegB Output Cout RegA+ RegB+ Output+ Cout+ 1 1111 1111 2 3 5 6 7

5 min University of Florida EEL 3701 Fall 2012 Dr Eric M Schwartz Page 11/11 Exam 2 (d + e = 11%) 10 min Action 9 d) Describe how to add these two additional functions to the lab 6 design by referring to the block diagram These changes should be done without using Cin Hint: You will need to insert another component into the design What component should be inserted? Draw as much detail as necessary to describe your change INPUT Bus REGA Bus REGB Bus OUTPUT Bus MSA1 MSA0 REGA Bus Cin MUX A s REG A MUX B s REG B Combinatorial Logic MSB1 MSB0 REGB Bus Cout OUTPUT Bus Increment REGA Bus to OUTPUT Bus Decrement REGA Bus to OUTPUT Bus MSC2:0 3 MUX C s (d + e = 11%) 8 e) Use the table below to INCREMENT the value presently in register A, then add this to 5 min the value in register B, and then DECREMENT the sum and put the result in register B Describe what is accomplished in each step Use the minimum number of clock cycles Give appropriate values for ALL signals, including any that you may need to add (utilizing, if necessary, the provided extra column after the MSC column) # MSA MSB MSC Input Cin RegA RegB Output Cout RegA+ RegB+ Output+ Cout+ 1 0010 0111 2 3 5 6 7 1 2 3 5 6 7