Synthesis of Sequential Reversible Circuits through Finite State Machine

Synthesis of Sequential Reversible Circuits through Finite State Machine A Dissertation Submitted in partial fulfillment for the award of degree of Master of Technology (with specialization in Computer Science) in Department of Computer Science and Engineering Supervisor Dr. S.C. Jain Professor, CSE Submitted By: Shubham Gupta Enrollment No: 12E2UCCSM45P616 Department of Computer Science and Engineering University College of Engineering Rajasthan Technical University Kota (Rajasthan) August 2014

Candidate's Declaration I hereby declare that the work, which is being presented in the Dissertation, entitled Synthesis of Sequential Reversible Circuits Through Finite State Machine in partial fulfillment of Master of Technology with specialization in Computer Science and Engineering, submitted to the Department of Computer Science & Engineering, University College of Engineering, Rajasthan Technical University, Kota is a record of my own investigations carried under the guidance of Dr. S. C. Jain Professor, Computer Science, University College of Engineering, RTU Kota. I have not submitted the matter presented in this Dissertation Report any where for the award of any other degree. Shubham Gupta Computer Science Engineering Enrollment No.: 12E2UCCSM45P616 University College of Engineering, RTU, Kota (Rajasthan) Counter Signed by Supervisor Dr. S.C. Jain Professor, Department of Computer Science & Engineering, University College of Engineering, Kota (Rajasthan) ii

Certificate This is to certify that this Dissertation entitled Synthesis of Sequential Reversible Circuits Through Finite State Machine has been successfully carried out by Shubham Gupta (Enrollment No.: 12E2UCCSM45P616), under my supervision and guidance, in partial fulfillment of the requirement for the award of Master of Technology Degree in Computer Science & Engineering from University College of Engineering, Rajasthan Technical University, Kota for the year 2012-2014. Dr. S.C. Jain Professor, Department of Computer Science & Engineering, University College of Engineering, Kota (Rajasthan) iii

Acknowledgments It is matter of great pleasure for me to submit this report on dissertation entitled Synthesis of Sequential Reversible Circuits through Finite State Machine, as a part of curriculum for award of Master in Technology with specialization in Computer Science & Engineering degree of Rajasthan Technical University, Kota. I am thankful to my Dissertation guide Dr. S. C. Jain, Professor in Department of Computer Science for his constant encouragement, able guidance and for giving me a new platform to build by career by giving me a chance to learn different fields of this technology. I am also thankful to the Head of Computer Science Department for the valuable support. I would like to acknowledge my thanks to entire faculty and supporting staff of Computer Engineering Department in general and particularly for their help, directly or indirectly during my dissertation work. I express my deep sense of reverence to my parents, family members and my friends for their unconditional support, patience and encouragement. DATE Shubham Gupta iv

List of Figures Figure 1.1 ITRS Feature Size Projection 3 Figure 1.2 Cost Efficiency Benefits 4 Figure 1.3 Feynman Gate 5 Figure 1.4 Block Diagram of Sequential Logic Circuit 6 Figure 1.5 Design of D flip-flop 6 Figure 2.1 Block diagram of NOT Gate 13 Figure 2.2 2 bit Feynman Gate (a) Truth Table; (b) Block Diagram 13 Figure 2.3 3 bit Toffoli Gate (a) Truth Table; (b) Block Diagram 14 Figure 2.4 3 bit Fredkin Gate (a) Truth Table; (b) Block Diagram 14 Figure 2.5 3 bit Peres Gate (a) Truth Table; (b) Block Diagram 15 Figure 2.6 3 bit New Gate (a) Truth Table; (b) Block Diagram 15 Figure 2.7 Block Diagram of Sayem Gate 16 Figure 2.8 Block Diagram of HNFG Gate 16 Figure 2.9 Flow Chart of Transformation Based Approach 18 Figure 2.10 (a)moore and (b) Mealy FSM Machine 19 Figure 2.11 (a) An original FSM and (b) its Reverse 20 Figure 3.1 Proposed 4 4 reversible SVS gate 25 Figure 3.2 Proposed Reversible Design of T Flip-Flop 27 Figure 3.3 Block Diagram of Proposed T Flip-Flop 28 Figure 3.4 A Conventional 4-bit Asynchronous Up-Counter 29 Figure 3.5 Proposed 4-bit Reversible Asynchronous Up-Counter 29 Figure 3.6 Proposed 4-bit Reversible Asynchronous Down-Counter 32 Figure 3.7 Proposed 4-bit Reversible Asynchronous Up/ Down-Counter 33 v

Figure 3.8 Conventional 4 bit Synchronous Up Counter 34 Figure 3.9 Proposed 4-bit Reversible Synchronous UP Counter 35 Figure 3.10 Conventional 4 bit Synchronous Up/ Down Counter 37 Figure 3.11 Proposed 4-bit Reversible Synchronous Up/Down Counter Design 38 Figure 4.1 A flow chart for realizing the reversible circuits from an FSM 42 Figure 4.2 Original FSM of String Accepter 44 Figure 4.3 Reverse FSM of String Accepter 44 Figure 4.4 Reversible FSM of String Accepter 45 Figure 4.5 Realization of reversible string accepter by reversible FSM 46 Figure 4.6 Original FSM of 3-bit odd parity generator 49 Figure 4.7 Reverse FSM of 3-bit odd parity generator 49 Figure 4.8 Reversible FSM of 3-bit odd parity generator 50 vi

List of Tables Table 2.1 Truth Table Method 10 Table 2.2 Truth table for a 3-input and 3-output function 11 Table 2.3 A reversible truth table 12 Table 2.4 A logical reversible AND function 12 Table 2.5 Truth Table of Sayem Gate 16 Table 2.6 Truth Table of HNFG Gate 17 Table 3.1 Truth Table of the Proposed Reversible Gate 26 Table 3.2 Truth Table of T Flip-Flop 27 Table 3.3 Truth Table of 4 bit Asynchronous Reversible Up-Counter 31 Table 5.1 Comparative Results of Proposed Reversible T Flip-Flops 53 Table 5.2 Comparison Between Existing and Proposed Reversible Asynchronous UP Counter Design Table 5.3 Comparison Between Existing and Proposed Reversible Asynchronous DOWN Counter Design Table 5.4 Comparison Between Existing and Proposed Reversible Asynchronous UP/ DOWN Counter Design Table 5.5 Comparison of Existing and Proposed Reversible Synchronous UP Counter Design Table 5.6 Comparison Between Existing and Proposed Reversible Synchronous UP/ Down Counter Design 53 54 54 55 55 vii

CONTENTS List of Figures List of Tables Table of Contents v vii viii Abstract 1 1 Introduction 2 1.1 Motivation 2 1.2 Reversible Computing 4 1.3 Reversible Gates and Reversible Circuits 4 1.4 Sequential Reversible Computing 5 1.5 Sequential Reversible Circuits 6 1.6 Objectives 7 1.7 Organization of Thesis 7 2 Background & Literature Survey 9 2.1 Boolean Algebra 9 2.2 Reversible Gates and Circuits 11 2.2.1 Definition of Reversible Logic 11 2.2.2 Basic Reversible Gates 13 2.2.3 Sequential Reversible Gates 15 2.3 Synthesis Approaches of Sequential Reversible Computing 17 2.4 Optimization Parameters 18 2.4.1 Gate Counts 18 2.4.2 Garbage Outputs 18 viii

2.4.3 Constant Inputs 19 2.5 Finite State Machine (FSM) 19 2.5.1 Background 20 2.5.2 Symbols and Formalism of FSM 21 2.6 Related Work 22 2.6.1 Reversible Finite State Machine 22 2.6.2 Reversible T Flip-Flop 22 2.6.3 Reversible Asynchronous and Synchronous Counters 23 2.7 Survey Extraction 24 3 Design of Sequential Reversible Counters 25 3.1 Proposed Reversible Gate 25 3.2 Proposed Reversible T Flip-Flop 26 3.3 Design of Asynchronous Reversible Counters 28 3.3.1 Proposed 4-bit Asynchronous Reversible Up-Counter 29 3.3.2 Proposed 4-bit Asynchronous Reversible Down-Counter 32 3.3.3 Proposed 4-bit Asynchronous Reversible Up/ Down-Counter 32 3.4 Design of Synchronous Reversible Counters 34 3.4.1 Proposed 4-bit Synchronous Reversible Up-Counter 34 3.4.2 Proposed 4-bit Synchronous Reversible Up/ Down Counter 37 3.5 Summary 40 4 Approach and Realization of Sequential Reversible Circuit from FSM 41 4.1 General Model of Sequential Circuit 41 4.2 Approach of Realization the Sequential Reversible Circuit 41 4.3 Experimental Setup of Reversible Circuits 43 4.3.1 To realize reversible circuit of string accepter by reversible FSM 43 ix

4.3.2 To realize the reversible circuit of odd parity generator of 3-bit with a single space between successive strings by reversible FSM 48 4.4 Summary 51 5 Results 52 5.1 Comparative Results of Proposed Reversible T Flip-Flop 52 5.2 Comparative Results of Proposed Asynch. Reversible Counters 53 5.2.1 5.2.2 5.2.3 Comparative Results of Proposed Reversible Asynchronous Up- Counter Design Comparative Results of Proposed Reversible Asynchronous Down-Counter Design Comparative Results of Proposed Reversible Asynchronous Up/ Down-Counter Design 53 54 54 5.3 Comparative Results of Proposed Synch. Reversible Counters 54 5.3.1 5.3.2 Comparative Results of Proposed Reversible Synchronous Up- Counter Design Comparative Results of Proposed Reversible Synchronous Up/ Down-Counter Design 55 55 5.4 Results of Sequential Reversible Circuits (From FSM) 55 5.5 Summary 56 6 Conclusion and Future Scope 57 6.1 Contributions 57 6.2 Future Scope 57 Paper Publications Out of the Dissertation 59 7 Reference 60 x

ABSTRACT Reversible computing has attracted the attention of researchers due to its low power consumption and less heat dissipation compared to conventional computing. A number of reversible gates have been proposed by different researchers and various combinational circuits based on reversible gates have been developed. However the realization of sequential circuit in reversible logic is still at premature stage. Sequential circuits were not available because of feedback was not allowed in reversible circuit. However allowing feedback in space (not in time), some sequential reversible gates and circuits have been reported in the literature. In this dissertation, we have addressed the problem from two sides. One side is to propose a low cost reversible gate suitable for sequential building block i.e. T flip-flop and hence designing low cost synchronous and asynchronous counters. Another side is to generate the circuit from its behavioral description described in FSM form. Our propose designs of reversible counters are significantly better in optimization parameters such as gate counts, garbage outputs and constant inputs available in literature. We have also proposed a procedure for obtaining reversible circuit from behavioral description through FSM. A very few attempts have been reported in the literature for the conversion FSM to reversible FSM. We have found no such complete procedure for obtaining reversible sequential circuit in literature. It was observed that the attempt made in [27] for generating reversible FSM from traditional (original) FSM were not suitable for generating sequential reversible circuit. This work has improved the generation of reversible FSM and evolved the step by step procedure to generate the sequential reversible circuit from reversible FSM. Because of non-availability of generated sequential reversible circuit in literature, our results cannot be compared with any other circuits. We expect that the sequential reversible circuits will help in debugging the reversible circuits, handling the ambiguous state of an FSM and generating the original input in reverse direction by reversing the original output. 1

Chapter - 1 INTRODUCTION The computing technology and operating requirements are increasing at a high speed and achieving high packaging densities in current computing scenario. Due to the limitations such as heat dissipation, low packaging density, etc. the conventional computing is not capable to deal with such fast growing demand. Today s computing scenario demands moving beyond conventional way of computing. Some alternatives are addressed to resolve the issues of conventional computing. Out of these alternatives, the reversible computing is emerging as a promising technology that produces high packaging density, computation speed and low power consumption, etc. In this chapter, section 1.1 describes the motivation behind reversible computing as an alternative technology, section 1.2 introduces of reversible computing, section 1.3 illustrates the reversible gates and reversible circuits, section 1.4 describes the concept of sequential reversible computing, section 1.5 elaborates the sequential reversible circuits, section 1.6 describes the objectives of the dissertation work and finally section 1.7 states the organization of thesis. 1.1 Motivation Tremendous changes has been occurred in the world of computing such as computer power, speed, efficiency is increased. From 1950 s to today, hardware technology has changed from vacuum tubes to multi-million gate solid-state devices. According to Moore s law in 1960 [1], on every one and half year to two years, the count of transistors per unit area will be almost double. A road map has been drawn by ITRS of required feature size projection in future at atomic level in 2050 [2] as shown in Figure 1.1. By Moore s prediction, particularly energy loss has evolved as a major limitation of conventional computing. The problem of energy dissipation is related to technological non-ideality of switches and materials. Over the last decades, the use of new fabrication processes and higher level of integration have dramatically reduced the energy. According to R. Landauer's principle [3], some other part of problem arises which does not have a solution. The principle of R. Landauer states that KT ln2 joules of energy for every bit of information is lost if logic computations are not necessarily reversible in nature. Here, K is Boltzmann's constant and T is the absolute temperature at which operation is performed. In modern computers, the energy loss is 2

considered due to the loss of information. On a loss of bit information, the current processors dissipate 100 times of this amount of heat. G. Moore [1] predicted that the information loss is main reason for exponential growth of heat dissipation and it will become a significant amount of energy loss in next future. Figure 1.1 ITRS Feature Size Projection Packaging density limitations may also generate the problem of portability. Social, economic and budgeting problems may also arise due to the energy dissipation that leads power consumption. In current scenario, it is very difficult to improve the parameters of conventional computing to overcome the energy loss. The researchers found a new technology that offers comprehensive improvement and continue growth momentum over conventional computing limitations. Reversible computing has shown this potential to support this momentum. 3

1.2 Reversible Computing The limitations and problems in conventional computing can be overcome by a new emerged technology reversible computing. No information loss in result of circuit/ device design is called reversible. In circuit design, it naturally manages the generated energy due to the loss of information. C. H. Bennett [4] proved that almost negligible heat dissipation would be possible if the digital circuit built from reversible gates. Because of this characteristic, reversible computing has high packaging density, high computation speed and no heat dissipation. Therefore, reversibility will become an important characteristic in future circuit design. As shown in Figure 1.2, ITRS [2] defined that in the best case a reversible computer may have 1, 00,000 times better cost efficient as compare to conventional computers. The applications of reversible computing are quantum computation, optical computing, ultra low power CMOS design, DNA computing and nanotechnology etc. From reversible environment, reversible computing has physical and logical reversibility. The logical operations are operated by reversible logic blocks which are known as reversible gates in reversible computing. Figure 1.2 Cost Efficiency Benefits 1.3 Reversible Gates and Reversible Circuits In digital system design, most of the gates are not reversible. The reversible operations are not performed in the gates such as AND, OR, EXOR and EXNOR but most commonly gate only NOT gate follow the characteristic of reversibility. A reversible gate performs a 4

bijective (onto) function between input and output vectors. It means that in a reversible gate inputs and outputs are same in number. In 1985, R. Feynman [5] addressed a Feynman gate. The block diagram of Feynman gate has two inputs and two outputs as shown in Figure 1.3. Figure 1.3 Feynman Gate In the next chapter, a detailed study is presented on the reversible gates. To design the reversible circuits a set of reversible gates are needed. Theree is a different synthesis mechanism of reversible circuits from conventional circuits. No fan-out, each inputof the reversible output pattern should be unique and acyclic nature is the main characteristics circuits. A reversible circuit that uses only Feynman gates called as Feynman circuit or Feynman based reversible circuit (Feynman Network). In the literature, a number of reversible circuits have been addressed to build large and complex circuits. The synthesis mechanism and techniques are well established for combinational circuits. Recently, the development on sequential reversible circuits is started. The next section describes the basics of sequential reversible computing and synthesis techniques. 1.4 Sequential Reversiblee Computing Researchers have made a significant research work in reversible logic and the area of reversible combinational logic is well developed. However, there is not much research is carried out in the field of synthesis of sequential reversible circuit. There are some reasons behind a slowdown research work in this area. In the beginning, there is a wide convention that the feedback is not allowed in reversible computing but in one of the well known fundamental paper, T. Toffoli [6] has defined that feedback can be allowed in reversible computing. According to T. Toffoli, A sequential network is reversible if its combinational part (i.e., the combinational network obtained by deleting the delay elements and thus breaking the corresponding arcs) is reversible. In 1982, E. Fredkin [7] has adapted this concept to propose the first design of the reversible sequential circuit called the JK latch [7] having the feedback loop from the output to input. Apart from this, J.E. Rice [8] and other researchers have also claimed that sequential circuits are reversible in nature. Recently, A. 5

Banerjee et al. [9] have redefined that feedback is allowed in space but not in time. Hence, the development of reversible sequential circuits has begun. The synthesis of sequential building blocks such as flip-flops, counters, registers and synchronous sequential circuits can be carried out by sequential reversible logic. In this work, we propose the realization of reversible counters (synchronous and asynchronous) and synchronous sequential reversible circuits such as string accepter, odd parity generator. The chapter 2 describes the proposed work on the realization. 1.5 Sequential Reversiblee Circuits The sequential reversible circuit output depends upon the present input and also on past output. Therefore, a memory element is required to store the past output. In Figure 1.4, the block diagram of sequential reversible logic circuit is shown. The combinational reversible logic circuit operates on these inputs to produce the outputs [10]. Figure 1.4 Block Diagram of Sequential Logic Circuit In 2012, the design of D flip-florealization of D flip-flop is shown in Figure is proposed by Md. Selim Al Mamun et.al [11]. The 1.5. Figure 1..5 Design of D flip-flop, presented in [11] 6

The realization of D flip-flop has two gates, modified Fredkin gate and Double Feynman gate [11]. The detailed explanation of these gates is given in chapter 2. The design of D flip-flop has one normal output and other one is complemented output. In the proposed realization CLK is the clock. The design has 1 garbage output (g 1 ) and two constant inputs. 1.6 Objectives In this dissertation work, we have taken up the project to synthesis and optimize the sequential circuits in reversible computing. The key points of the dissertation are as follows: To propose a reversible gate and design T flip-flop from proposed reversible gate with minimum optimization parameters To realize the reversible synchronous and asynchronous counter (Up, Down, Up/Down) from the proposed reversible T flip-flop To improve the method of generating the reverse Finite State Machine (FSM) to construct reversible FSM To propose a method for the realization of synchronous sequential reversible circuit from FSM To realize the reversible circuit for string accepter and odd parity generator from proposed method To prove the proposed method of realizing the sequential reversible circuit from theorems and to compare the results with previous proposed designs in literature 1.7 Organization of Thesis The work of dissertation is as follows: Chapter 2, titled Background & Literature Survey describes the classic definition and related objects of reversible logic are explained. By this brief introduction, the reader gains the real objective and notations of reversible logic theory. The previous work on sequential circuit realization is summarized and analyzed in this section. The introduction, background and formalism of FSM are explained in this chapter. The main focus of this chapter is to point out the weakness of previous design and approaches. 7

The first step in our research is to propose a reversible gate and design T flip-flop using proposed reversible gate with minimum optimization parameters. The chapter 3, titled Design of Sequential Reversible Counters is focused on minimization of the T flip-flop and to propose the design of sequential reversible counters. The theorems are also proposed to explain the realization of reversible counters. Chapter 4, titled Approach & Realization of Sequential Reversible Circuit from FSM explains the improvement method of generating reverse FSM is explained to construct the reversible FSM. At last, the reversible circuit is realized from reversible FSM using our method. Chapter 5, titled Results proposes a comparative and statistical study on the synthesis of flip-flop and counters. The reversible circuit of string accepter and odd parity generator are used for verification of results. Chapter 6, titled Conclusion and Future Scope concludes the thesis work and points out to the directions of further research in the area of sequential reversible logic synthesis. 8

Chapter - 2 BACKGROUND & LITERATURE SURVEY The development of sequential reversible computing is introduced in the chapter 2. Boolean algebra, definition of reversible logic, reversible gates, synthesis methods of sequential reversible computing, FSM formalism and related work are covered in this chapter. The synthesis of circuits in conventional computing is well established but the synthesis and optimization of sequential reversible computing is still at premature stage. In this chapter, the proposed method and designs of sequential reversible circuits such as flip-flops and counters are addressed and analyzed. The techniques for obtaining conventional irreversible circuits from FSM are well established. A very few attempts have been reported in the literature for the conversion FSM to reversible FSM. To the best of our knowledge, this is the first attempt for realizing sequential reversible circuit using reversible FSM. The proposed work related to reversible FSM is also addressed in this chapter. We organize the background (reversible logic and FSM) and survey in following categories: Boolean Algebra Reversible Gates and Circuits Synthesis Approaches of Sequential Reversible Computing Optimization Parameters Introduction, Background and Formalism of FSM Related work Survey Extraction 2.1 Boolean Algebra To start a discussion on reversible logic, it is good to have some brief overview on Boolean logic. 0 and 1 are the two Boolean constants. To describe a Boolean function of n variables truth table is useful. In conventional computing, a truth table has 2 n rows and n+ 1 column. A function of n Boolean variables has 2 n number of different inputs. In this way, the truth table has 2 n rows [12]. The conventional way of representing the truth table is to arrange 2 n 9

Boolean patterns in a lexicographical order. A lot of storage space is required for the truth table though ordering of input is not important. For the simplification and to save storage space, the truth vector is used. The usefulness of truth vector can be explained by comparing a function with truth table method. Example 1: Consider a truth table as shown in Figure 2.1. For the same function, the truth vector is {0, 1, 0, 0, 1, 0, 1, 1}. In general, a function of n variables the truth vector requires n+ 1 times less storage than truth table. So, the truth vector is useful wherever it is convenient. Table 2.1 TRUTH TABLE METHOD A B C F(A, B, C) 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 0 1 1 0 1 1 1 1 1 A p-input and q-output (multiple output) defines a Boolean function (f 1 (x 1, x 2, x 3,., x p ), f 2 (x 1, x 2, x 3,., x p ),,f q (x 1, x 2, x 3,., x p )) with (p+ q) columns in truth table. Equivalently, p-input q- output (multiple output) Boolean function is a vector-function of q Boolean functions. A multiple output function can be represented as truth vector. So, the binary representation of output pattern for each of the 2 p elements of this vector is an integer bearing an interval of [0... 2 q -1] [12]. From the Example 1, one can conclude that the above described truth table method saves onefourth of the storage space. Example 2: In table 2.2, a 3-input and 3-output (multiple outputs) Boolean function is given. The truth vector is {0, 1, 2, 3, 7, 6, 5, 4}. 10

Table 2.2 TRUTH TABLE FOR A 3-INPUT AND 3-OUTPUT FUNCTION A B C f 1 f 2 f 3 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 1 1 1 0 1 1 1 0 1 1 0 1 0 1 1 1 1 1 0 0 Here, the operations of concatenation or conjunction, negation and EXOR are used. For more details on Boolean logic refer [12]. 2.2 Reversible Gates and Circuits Before an introduction of popular reversible gates and circuits, we are addressing the definition of reversible logic in this section. 2.2.1 Definition of Reversible Logic Definition 1: The reversible function is the main object in reversible logic theory. It is defined as follows [13]: A Boolean function F(x 1, x 2, x 3,., x n ) with multiple output of n variables is reversible if: The number of outputs is equal to the number of inputs Each output pattern has a bijection function In this way, the reversible function performs one to one correspondence between input and output vectors. Example 3: A formula (A, B) (A, AÅB) satisfies a 2-input and 2-output function. The given truth table below is reversible. 11

Table 2.3 A REVERSIBLE TRUTH TABLE A B A AÅ B 0 0 0 0 0 1 0 1 1 0 1 1 1 1 1 0 The analysis of the truth table verifies the reversibility. Example 4: Consider a function (A, B) AB (logical AND operation). It is not possible to make it reversible by adding a single output [6]. If we add one input and two outputs then, the function becomes reversible which is shown in Table 2.4. Table 2.4 A LOGICAL REVERSIBLE AND FUNCTION A B C A B ABÅC 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 1 1 0 1 1 1 1 1 1 1 1 0 As observed in the truth table, variable C will be zero at third output column value to get the desired function. In other words, the input C must be constant zero to realize the function. A, B are two garbage outputs. This function realizes the Toffoli gate [6]. Therefore, to make a function reversible, it is necessary to add input and output values. Definition 2: To make p-input and q-output function reversible garbage outputs are added. To make (p, q) function reversible constant inputs (present value inputs) are added. A single constant input C=0 is added as shown in Example 4. 12

A simple formula derives a relation between the constant inputs and number of garbage outputs [12] input + constant input = output + garbage outputs 2.2.2 Basic Reversible Gates In this section, we illustrate about the popular reversible gates which are use in synthesis of sequential reversible circuits. In 1973, C.H. Bennett [4] showed that if reversible gate are using for circuit realization then it is possible to gain less or almost no energy loss. Researchers have proposed a number of reversible gates. These are: NOT Gate: It is a 1 1 basic reversible logic gate. In 1980, T. Toffoli showed that NOT gate is reversible [6]. The block diagram is shown in Figure 2.1. A P=A Figure 2.1 Block diagram of NOT Gate Feynman Gate: The truth table of a 2-bit Feynman gate (FG) is shown in Figure 2.2(a), and its block diagram is shown in Figure 2.2(b) [5]. Feynman Gate can be used as a copying gate. Since a fan-out is not allowed in reversible logic, this gate can be used for duplication of the input to two outputs. Figure 2. 2 2 bit Feynman Gate (a) Truth Table; (b) Block Diagram Toffoli Gate: In 1980, T. Toffoli introduced a famous Toffoli gate. The truth table of a 3- bit Toffoli gate (TG) is shown in Figure 2.3(a), and its block diagram is shown in Figure 2.3(b) [6]. Toffoli gate is used as a universal gate in reversible logic. 13

Figure 2.3 3 bit Toffoli Gate (a) Truth Table; (b) Block Diagram Fredkin Gate: The truth table of a 3-bit Fredkin gate (FRG) is shown in Figure 2.4(a) and its block diagram is shown in Figure 2.4(b) [7]. Fredkin gate is the mostly used reversible gate to design reversible latches and flip-flops. Figure 2.4 3 bit Fredkin Gate (a) Truth Table; (b) Block Diagram Peres Gate: It is a 3 3 reversible gate. The truth table of the Peres gate is shown in Figure 2.5(a) and its block diagram is shown in Figure 2.5(b) [14]. The Peres Gate is the combination of Feynman Gate (FG) and Toffoli Gate (TG). 14

Figure 2.5 3 bit Peres Gate (a) Truth Table; (b) Block Diagram Figure 2.5 3 bit Peres Gate (a) Truth Table; (b) Block Diagram 2.2.3 Sequential Reversible Gates In this subsection, some important reversible gates are explained which are also used in the synthesis of sequential reversible circuits. These are: New Gate: The truth table of a 3 3 reversible gate is shown in figure 2.6(a). Figure 2.6(b) shows the block diagram of New Gate (NG). The first attempt on the realization of sequential reversible building blocks H. Thapliyal et al. [15] has used New Gate. Figure 2.6 3 bit New Gate (a) Truth Table; (b) Block Diagram Sayem Gate: A new reversible 4 4 gate named Sayem Gate (SG) is proposed by Abu Sadat Md. Sayem et al. [16]. The truth table of Sayem gate is shown in Table 2.5. Its block diagram is shown in figure 2.7. V. Rajmohan et al. [17] used this gate for the realization of T, D flip-flops, counters and shift registers. 15

Table 2.5 TRUTH TABLE OF SAYEM GATE Figure 2.7 Block Diagram of Sayem Gate HNFG Gate: M. Haghparast et al. [18] have proposed a reversible gate which is used for the realization of shift registers. The block diagram of HNFG Gate is shown in Figure 2.8 and its truth table is shown in Table 2.6 respectively. Figure 2.8 Block Diagram of HNFG Gate 16

Table 2.6 TRUTH TABLE OF HNFG GATE There are several reversible gates are which are used for the realization of sequential reversible circuits. For the synthesis of sequential reversible circuits such as flip-flops, counters and registers the above proposed gate, Fredkin Gate, Feynman Gate etc. are used. 2.3 Synthesis Approaches of Sequential Reversible Computing For the synthesis and optimization of combinational reversible circuits, the approaches such as transformation based methods [19], Search-based methods [20], Cycle-based methods [21] and BDD [23] were proposed by different researchers. However, in the synthesis techniques of sequential reversible circuits only transformation based method is used. The transformation based synthesis method proposes to compares the identity function (I) with a given permutation (F) as shown in figure 2.9. It applies reversible gates to transform F into I. The synthesis of sequential reversible logic can be done by two approaches. Often, it is useful to have two approaches to solve a problem [23]. The first approach can be considered by examining the conventional logic implementations of sequential reversible circuits such as flip-flops and counters. The replacement of conventional gates in these elements by reversible gates will be the resultant sequential reversible logic 17

circuits. According to the second approach, the problem is examined from a logic synthesis point of view. A truth table is given with the desired logic [24]. We can make a cascade of reversible logic elements which transforms the inputs to final outputs. Figure 2.9 Flow Chart of Transformation Based Approach Thus, after a careful selection of sequential reversible gates, we can start incorporating these gates into a process of synthesis with the target of generating sequential logic circuits. From a careful survey of sequential reversible circuit synthesis (the details is given in section 2.6), we can conclude that the technique of incorporating the sequential networks into reversible logic synthesis is not yet investigated. However, the above explained transformation based approaches are reasonably useful for the synthesis of sequential reversible networks. 2.4 Optimization Parameters The synthesis of sequential reversible logic is carried out by transformation based. After the synthesis process, the optimization of the circuit is required. The optimization process can be started with the synthesis process or after the synthesis. It is also called the post synthesis optimization. The design of any reversible logic can be minimized based upon some necessary parameters. These parameters are explained as follows: 2.4.1 Gate Counts: The total number of reversible gates required to realize a reversible circuit is referred as gate counts [25]. In figure 1.5, the gate count is 2. 2.4.2 Garbage Outputs: The unwanted or unused outputs which are needed to maintain reversibility of a reversible gate is called as Garbage Outputs [25]. 18

2.4.3 Constant Inputs: In the synthesis of sequential reversible circuits, it is a very important factor. Constants are the input lines that are either set to zero or one in the circuit s input side [25]. In this way, our goal is to synthesis of sequential reversible circuit and design optimization of sequential reversible logic in terms of all important parameters, viz., the gate counts, garbage outputs and constant inputs as observed that these optimization parameters can further be reduced. 2.5 Finite State Machine (FSM) An FSM consist a finite set of states and transitions among them. The machine can be in only one of the states at any point of time and can transition to the next state based on the current state and current value of inputs. An output is also be generated during the transition. In figure 2.10 the finite set of states is S 0, S 1 and transitions among them are shown by arrows. There are two types of FSM with output; (i) Moore Machine and (ii) Mealy Machine. In figure 2.10(a) and 2.10(b), the examples of Moore and Mealy machine are demonstrated respectively. The input value is always marked on the arrows and the output values are given under '/' sign inside the states of Moore machine. But in the case of Mealy machine, output values are given under '/' sign on arrows [26]. (a) (b) Figure 2.9 (a) Moore and (b) Mealy FSM 19

Both these machines are equivalent and one can convert into another by existing standard techniques. Constructing a reversible FSM with normalizing the issues, sequential reversible circuits can be realized. The realization of the circuit is of interest to reduce the heat dissipation in future reversible technologies. 2.5.1 Background Often, a finite state machine is one of the important methods that describe the behavior of sequential digital circuits. An FSM can be described as a set of states and transitions among them. One of the states is designated as initial state and one or more states as final states. The transitions represent the change in state on specific inputs and produce new state and input. FSM can be viewed as a circuit that receives a sequence of inputs and produces a corresponding sequence of outputs while changing its own internal state. In order to incorporate reversibility in the circuits, a new FSM can be designed from the given original FSM such that it works in the reverse direction of the original one [26]. Normally, the sequence of the inputs is given to the initial/current state of the original FSM and sequence of outputs is generated at next/final state of an FSM as shown in Figure 2.11(a). In the reversing process of an FSM as shown in Figure 2.11(b), it can start from the original final state, consume the original outputs in reverse direction and produce the original inputs. Simply, one can generate the reverse of an FSM by reversing the transitions. In addition to reversible logic design the reverse FSM is useful in error analysis, debugging and fault tolerance for controllers and for designing sequential circuits. (a) (b) Figure 2.11 (a) An original FSM and (b) its Reverse 20

2.5.2 Symbols and Formalism of FSM In this work, we focus on Mealy machines. We first define a number of symbols: 0 1: represents either 0 or 1 in a bit position {0, 1}: represents the set of 0 and 1 s * : represents zero or more repetitions of s s + : represents one or more repetitions of s (0 1)+: represents any non-empty vector of 0s and 1s in any order A Mealy FSM can be formally defined by a four tuples (Q, I, O, f) where: Q: represents finite non-empty set of states I: represents finite non-empty set of input values O: represents finite non-empty set of output values f: represents combined state-transition and output function; f: Q I Q O Hence, for every combination of current state and input, f produces the next state and the output. Before explaining the steps to realize the sequential reversible circuit by reversible FSM, some issues can be defined as follows [27]: A. Definition 1: Ambiguous Previous State An FSM contains ambiguous previous state if it contains at least one state which can be entered from two different states but sharing the same output value: $ qi, q j, qkî Q qi ¹ q j $ ii,i jî I In such case, state q k has ambiguous previous state. $ o Î O f (q i,i i ) = f (q j,i j) = f (q k,o k ) (1) k B. Definition 2: Conflicting States The conflicting states of a state q k and output value o k consists of all previous states of q k that produce the same output o k when transitioning to q k Following equation (1) above, all q i and q j comprise the conflicting set of q k : 21

C. Definition 3: Don't Care Condition CS (q k,o k ) = {q i $ q jî Q qi ¹ q j $ ii,i jî f (q,i ) = f (q,i ) = (q,o )} (2) i i j j k k The don t care condition arises when an output bit does not depend on input of previous state. This is required for obtaining output and optimization using K-map. I 2.6 Related Work In current literature, researchers have proposed the design of sequential reversible circuits. The synthesis and optimization technique of sequential reversible circuits is also proposed. The following points describe the previous proposed work in reversible finite state machine and sequential reversible circuit. 2.6.1 Reversible Finite State Machine The realization of reversible Finite State Machine was proposed by D. Vasudevan et al. [27] in 2009. The two issues in FSM were also addressed by the researchers and they generated reversible FSM by merging original and reverse FSM. However, improvement in reverse FSM generation procedure is needed for realization of reversible circuit from reversible FSM. Researchers have addressed a procedure to obtain the reversible FSM using FSM as input and implemented its behavior in Field Programming Gate Array (FPGA). 2.6.2 Reversible T Flip-Flop In 2005, H. Thapliyal et al. [15] have addressed the design of reversible T flip-flop. In the designing of reversible T flip-flop, the conventional design of a flip-flop was used. The Fredkin, Feynman and New Gate was used as AND, NOT and NOR Gate respectively. This was the first attempt on the designing of reversible T flip-flop. The proposed design has 10 reversible gates, 12 garbage outputs and 10 constant inputs. This work was very general and further investigation is needed in order to optimize the published results. J. E. Rice [8] has proposed reversible T flip-flop by using NOT gates and R-S latches in 2006. The realization of R-S latch was proposed by Toffoli, Extended Toffoli and NOT gate. The results were improved from the previous proposed design of reversible T flip-flop. The proposed reversible design has 13 reversible gates, 14 garbage outputs and 13 constant inputs. 22

In 2006, the reversible design of T flip-flop was proposed by S. K. S. Hari et al. [22] from basic reversible Fredkin and Feynman gates. The improved results were found after a comparison from the previous proposed design on sequential reversible T flip-flop. The proposed reversible design of T flip-flop has 3 garbage outputs, 5 reversible gates and 2 constant inputs. In 2007, A. Banerjee et al. [9] have proposed the realization of reversible T flip-flop. For the construction of reversible T flip-flop, Toffoli gate (CCNOT Gate), Feynman gate (CNOT gate) and NOT were used. The proposed reversible T flip-flop has 14 reversible gates, 10 garbage outputs and 10 constant inputs. It is observed that the further optimization is needed in the reversible design and our proposed design is much optimized than the above proposed work. A novel concept on the designing of reversible flip-flops was proposed by Min-Lun Chuang et al. [28] in 2008. In this work, T flip-flop was reported by using one D and T latche, which was an improvement over the proposed design of H. Thapliyal. The realization of D and T latche has Toffoli, Feynman and NOT gate. The proposed circuits were optimized in terms of gate counts, garbage outputs which were 5 and 3 respectively. In 2011, V. Rajmohan et al. [17] have reported the realization of reversible T flip-flop. The realization of T flip-flop has one Fredkin gate and two Sayem gates. Hence 3 gates, 3 garbage outputs and 2 constant inputs have been used in constructing the reversible T flip-flop. 2.6.3 Reversible Asynchronous and Synchronous Counters V.Rajmohan et al. [17] have proposed the design of reversible up-down asynchronous and synchronous counters in 2011 from reversible T flip-flop. The design has 15 reversible gates, 12 garbage outputs and 11 to 13 constant inputs. In 2012, Lafifa Jamal et al. [29] have proposed the realization of reversible synchronous counter from JK flip-flop. The proposed JK flip-flop has 3 reversible gates (two Fredkin gate and one Double Feynman gate), 3 garbage outputs and 2 constant inputs. The realization of reversible synchronous counter has 20 gates, 22 garbage outputs and 16 constant inputs. In 2013, Pradeep Singla et al. [30] have proposed the design of synchronous and asynchronous counters from JK flip-flop. The proposed JK flip-flop has 10 reversible gates (4 Mux gate, 2 New gate and 4 Feynman gate), 12 garbage outputs and 10 constant inputs. Hence, the reversible counters have 31-34 reversible gates, 36-38 garbage outputs and 31-33 constant inputs. 23

2.7 Survey Extraction From the careful survey on the synthesis and optimization of sequential reversible circuits, it can be concluded that most of these work considered the optimization of number of reversible gates, garbage outputs and constant inputs. We have observed that the designs of T flip-flop can be optimize in terms of optimization parameters (gate counts, garbage outputs and constant inputs) to directly optimize the design of synchronous and asynchronous counters as T flip-flop is used in the realization of counters. In the realization of reversible circuit from reversible FSM, we observed that the obtained reversible FSM can be extended for obtaining reversible circuits. Hence, a modified process can be proposed to generate a reversible FSM followed by reverse FSM. The next subsequent chapters of this dissertation will explain our proposed work. 24

DESIGN OF SEQUENTIAL REVERSIBLE COUNTERS Chapter 3 This chapter illustrates the proposed synthesis and optimization of sequential reversible circuits. The proposed design has low cost optimization parameters. In this chapter, a new reversible gate is proposed and this gate is used to realize the T flip-flop. The realization of reversible synchronous and asynchronous (UP, DOWN) counters is also proposed by T flipflop. The conventional design of counters is used to propose reversible synchronous and asynchronous counters. The transformation based approach is applied for the realization of counters. The algorithm and theorems are proposed for the design of counters. The next sections of this chapter are described as follows: Proposed Reversible Gate Proposed T Flip-Flop Design of Asynchronous Reversible Counters Design of Synchronous Reversible Counters 3.1 Proposed Reversible Gate To realize the sequential reversible counters, we present a new 4 4 reversible SVS gate. This gate maps input vectors I (A, B, C, D) to output vectors O (P, Q, R, S) where P = A, Q = BC A B AB C, R = BC A B AB C D and S = A C AB respectively. Figure 3.1 shows the block diagram of SVS gate. Table 3.1 shows the relevant truth table of the proposed gate. Figure 3.1 Proposed 4 4 reversible SVS gate 25

Table 3.1 TRUTH TABLE OF THE PROPOSED REVERSIBLE GATE 3.2 Proposed Reversible T Flip-Flop A flip-flop is a bi-stable multi-vibrator. A flip-flop has only two stable states. In this section we propose the realization of level triggered T Flip-flop from our proposed reversible SVS gate. This flip-flop Toggle or complement its state so the T flip-flop is known as Toggle flip-flop. The modification of JK flip-flop is T flip-flop. T flip-flop is realized from JK flip-flop by connecting both the inputs J and K together [10]. The characteristic equation of T flip-flop is Q n = (T. CLK) Q n-1. When the T input is in the 0 state prior to a clock pulse, the Q n output will not change with clocking. When the T input is in the 1 level prior to clocking, the output will be Q n. The truth table shows that when T=0, then Q n =Q n-1, the next output is the same as the present state and no change occurs. When T=1 and CLK=1, then Q n =Q n-1, i.e. state of the flip-flop is complemented. Table 3.2 shows the truth table of T flip-flop. 26

Table 3.2 TRUTH TABLE OF T FLIP-FLOP CLK T Q n-1 Q n 0 0 0 0 1 0 0 1 0 0 1 1 1 0 1 0 0 1 0 0 1 1 0 1 0 1 1 1 1 1 1 0 The characteristic equation of T flip-flop can be directly mapped into proposed SVS gate. The clock is applied at input A of the SVS gate. The feedback is applied at input B to output R of the SVS gate to realize the characteristic equation of the T flip-flop. The toggle and constant input 0 is applied at input C and D. The garbage outputs in the T flip-flop are output P and S. The output Q n of SVS gate is considered as output of proposed reversible T flip-flop. The four input combinations can be found in the proposed reversible level triggered T flipflop as (CLK = 0, T = 0, Q n-1 = 0), (CLK = 0, T = 1, Q n-1 = 0), (CLK = 1, T = 0, Q n-1 = 0), and (CLK = 1, T = 1, Q n-1 = 1), the output Q n is 0. The proposed design of reversible T flipflop has 2 garbage outputs and 1 constant input. The reversible design of T flip-flop is shown in figure 3.2 and its corresponding block diagram is shown in figure 3.3. Figure 3.2 Proposed Reversible Design of T Flip-Flop 27

Figure 3.3 Block Diagram of Proposed T Flip-Flop In the realization of sequential counters T flip-flop is mostly used because of its inherent divide by- 2 capabilities. When a clock is enabled, the output changes state at every input cycle [10]. This type of action is required in many cases of counters. 3.3 Design of Asynchronous Reversible Counters This section illustrates the design and realization of asynchronous reversible counter from the proposed reversible T flip-flop. The algorithms and theorems are also described to prove and justify the reversible design of asynchronous counters. In literature, very little work has been proposed in the design of reversible asynchronous and synchronous counters and found that the optimization can be possible in the previous designs. Therefore, we are proposing the realization of asynchronous counters. The realization of reversible synchronous counters is proposed in next subsection. To realize the reversible counters transformation based approach is used. The steps can be followed to propose all type of reversible counters. These are the general steps which are applicable in the realization of every reversible counter. i. Consider a conventional circuit of desired counter ii. Select the flip-flop to be used iii. Replace the conventional gates (AND, OR gate etc.) from reversible gate( Toffoli, Feynman gate) in conventional circuit iv. Derive the excitation functions and working for the selected counters, and finally v. Realize the logic network for the excitation function of the reversible counter In terms of logical operations the asynchronous counter is the simplest one. In an asynchronous counter, the clock pulse is applied to the first flip-flop and the next flip-flop is 28

triggered by the output of the previous flip-flop. The first steps of the counters switches first and successive stages change their states causing a ripple through effect of the count pulses [10]. 3.3.1 Proposed 4-bit Asynchronous (Ripple) Reversible Up-Counter The conventional circuit diagram of a 4-bit asynchronous up-counter is shown in figure 3.4. Figure 3.4 A Conventional 4-bit Asynchronous Up-Counter The reversible design of the 4-bit asynchronous Up-Counter is shown in figure 3.5. At the output of each reversible T Flip-flop, the Feynman Gate is used for the complemented Q output with the input B=1. These complemented Q outputs of each T Flip-flop trigger the subsequent T Flip-flops and the reversible design performs the Up-Counter operation [34].. Figure 3.5 Proposed 4-bit Reversible Asynchronous Up-Counter 29