BHARATHIDASAN ENGINEERING COLLEGE, NATTRAMPALLI DEPARTMENT OF ECE

BHARATHIDASAN ENGINEERING COLLEGE, NATTRAMPALLI DEPARTMENT OF ECE CS6201 DIGITAL PRINCIPLES AND SYSTEM DESIGN 1 st year 2 nd semester CSE & IT Unit wise Important Part A and Part B Prepared by L.GOPINATH M.Tech., ASST.PROF DEPARTMENT OF ECE UNIT I - BOOLEAN ALGEBRA AND LOGIC GATES PART A 2 MARKS

1. Define binary logic Binary logic consists of binary variables and logical operations. The variables are designated by the alphabets such as A, B, C, x, y, z, etc., with each variable having only two distinct values: 1 and 0. 2. What is meant by Digital Systems? A digital system is a system that manipulates discrete elements of information that is represented by binary form i.e. 0 s and 1 s. 3. List the number systems i) Decimal Number system ii) Binary Number system iii) Octal Number system iv) Hexadecimal Number system 4. Convert 7368 into an equivalent binary number. (Nov/Dec-11) The binary equivalents of 7, 3 and 6 are 111,011 & 110 respectively. Therefore 7368 = 1110111102 5. Which gates are called as the universal gates? What are its advantages? (May/Jun-11,Nov/Dec-12,Nov/Dec-13,May/Jun-13,May/Jun-15) The NAND and NOR gates are called as the universal gates. These gates are used to perform any type of logic application. 6. State the sequence of operator precedence in Boolean expression? x Parenthesis x AND x OR 7. What are the different types of number complements? x Radix Complement x Diminished Radix Complement 8. Why complementing a number representation is needed. Complementing a number becomes as in digital computer for simplifying the subtraction operation and for logical manipulation complements are used. 9. How to represent a positive and negative sign in computers x Positive (+) sign by 0 x Negative (-) sign by 1. 10. What is meant by Map method? The map method provides a simple straightforward procedure for minimizing Boolean function.

11. What is meant by two variable map? (May/Jun-13) Two variable map have four minterms for two variables, hence the map consists of four squares, one for each minterm. 12. State Duality principle. (Nov/Dec-12) The dual of any Boolean function can be obtained by changing each OR sign to an AND sign and vice versa and complementing any 0 or 1 appearing in the expression. 13. Why parity checker is needed? Parity checker is required at the receiver side to check whether the expected parity is equal to the calculated parity or not. If they are not equal then it is found that the received data has error. 14. What is meant by parity bit? Parity bit is an extra bit included with a binary message to make the number of 1 seither odd or even. The message, including the parity bit is transmitted and then checked at the receiving and for errors. 15. What are the needs for binary codes? x Code is used to represent letters, numbers and punctuation marks. x Coding is required for maximum efficiency in single transmission. x Binary codes are the major components in the synthesis (artificial generation) of speech and video signals. x By using error detecting codes, errors generated in signal transmission can be detected. x Codes are used for data compression by which large amounts of data are transmitted in very short duration of time. 16. Mention the different type of binary codes? x Binary weighted code x Binary non - weighted code x Sequential code x Alphanumeric code x Error-detecting and error-correcting code 17. List the advantages and disadvantages of BCD code? Advantages of BCD code: a. Any large decimal number can be easily converted into corresponding binary number b. A person needs to remember only the binary equivalents of decimal number from 0 to 9. c. Conversion from BCD into decimal is also very easy. Disadvantages of BCD code: a. The code is least efficient. It requires several symbols to represent even small numbers. b. Binary addition and subtraction can lead to wrong answer. c. c. Special codes are required for arithmetic operations.

d. This is not a self-complementing code. e. Conversion into other coding schemes requires special methods. 18. What is meant by self-complementing code? A self-complementing code is the one in which the members of the number system complement on themselves. This requires the following two conditions to be satisfied. x The complement of the number should be obtained from that number by replacing 1s with0s and 0s with 1s. x The sum of the number and its complement should be equal to decimal 9. Example of a self-complementing code is i) 2-4-2-1 code. ii). Excess-3 code 19. Mention the advantages of ASCII code x There are 27 =128 possible combinations. Hence, a large number of symbols, alphabets etc.., can be easily represented. in which the alphabets, etc.., are assigned to each code word. x The parity bits can be added for error-detection and correction. 20. What are the disadvantages of ASCII code? x x There is a definite order The length of the code is larger and hence more bandwidth is required for transmission. x With more characters and symbols to represent, this is not sufficient. 21. Application of octal number system: It is highly in convenient to handle long strings of binary numbers while entering into the digital systems. It may cause errors also. Therefore, octal numbers are used for entering binary data and displaying certain information. 22. What is a Logic gate? (May/Jun-14) Logic gates are the basic elements that make up a digital system. The electronic gate is a circuit that is able to operate on a number of binary inputs in order to perform a particular logical function. 23. List out the advantages and disadvantages of K-map method? The advantages of the K-map method are x It is a fast method for simplifying expression up to four variables.

x It gives a visual method of logic simplification. x Prime implicants and essential prime implicants are identified fast. x Suitable for both SOP and POS forms of reduction. x It is more suitable for class room teachings on logic simplification. The disadvantages of the K-map method are x It is not suitable for computer reduction. x K-maps are not suitable when the number of variables involved exceed four. x Care must be taken to fill in every cell with the relevant entry, such as a 0, 1 (or) don t care terms. 24. Mention any two applications of DeMorgan s theorem. (May/June 2007) It is used to convert SOP expression into POS expression and vice versa. It is used to simplify the Boolean expressions. 25. Express F = A + B C as sum of minterms. (Nov/Dec 07) A + B C = A (B + B) (C + C) + (A + A) B C = (AB + AB) (C + C) + ABC + ABC = ABC + ABC + ABC + ABC + ABC + ABC = ABC + ABC + ABC + ABC + ABC = m (1, 4, 5, 6, 7) 26. Find the complement of A + BC + AB. (Nov/Dec 08) F = A + BC + AB = A + AB + BC = A + BC = A BC = A (B + C) = AB + AC

27.State Distributive Law. (Nov/Dec 13) If + and are the two binary operators on a set x, then + is said to be distributive over whenever A (B + C) = A B + A C 28.What is prime implicant? (Nov/Dec 13) A prime implicant is a product term obtained by combining the maximum possible number of adjacent squares in the map. They cannot be reduced further. 29. State DeMorgan s theorem.(may/june 09, 13, Apr/May 11, 05, Nov/Dec 06) DeMorgan suggested two theorems that form an important part of Boolean algebra. They are: Theorem 1: AB = A + B Theorem 2: A + B = A B 30. What are don t care terms? (May/June 13) I0 represent the dont care conditions. Two terms are used as don t care terms such as X or d 31.Find the Octal equivalent of the Hexadecimal number DC.BA (May/Jun-16) 32. What is Meant by Multilevel Gates Network? PART B 16 MARKS 1. a. Explain the various types of K-Map with Examples (Nov/Dec-12) (12) b. Prove that x + 1 = 1 (2) c. Prove that x + xy = x (2) 2. a. Simply the Boolean Function Using Three Variable K-Map (May/Jun-14)

F(X, Y, Z) = (3, 4, 6, 7) (8) b. Simply the Boolean Function Using Four Variable K-Maps F(W,X,Y,Z) = (0,1,2,4,5,6,8,9,12,13,14) (8) 3. a. Explain logic operations with NAND Gates? (8) b. Explain Multilevel NAND Gates? (8) 4. a. Explain Implementation of NOR Gates? (8) b. Explain AND- OR Invert Implementation (8) 5. Simplify the given Boolean Function (May/June 13) (i) a Sum of products form (ii) Product of sum form and implement if using basic gates. F(A, B, C, D) = (0, 1, 2, 5, 8, 9, 10) 6. Minimize the following function using K-Map. Implement the resultant function using NOR gates only. (May/June 05) F(A, B, C, D, E) = П M (2, 4, 7, 9, 26, 28, 29, 31) 7. Simplify the Boolean function using tabulation method (May/June-11) (16) F= sum (0,1,4,11,15,32,29,28) 8. Find a minimal sum of product representation for f(a, B, C, D, E) = m(1, 4, 6, 10, 20, 22, 24, 26) + d(0, 11, 16, 27) using K-Map method. Draw the circuit of the minimal expression using only NAND gates. (May/June 13) 9. Simplify the given Boolean function using tabulation method. F(A, B, C, D) = m(1, 2, 3, 5, 7, 9, 10, 11, 13, 15) (Nov/Dec 2012) 10. Simplify the logic function using Quine-McCluskey F(A, B, C, D) = m (1, 3, 4, 5, 9, 10, 11) + d (6, 8) (Nov/Dec 2011) 11. Reduce the Expression Using Mc-Cluskey method. (May/Jun-16) F(x1,x2,x3,x4,x5) = m(0, 2, 4, 5, 6, 7, 8, 10, 14, 17, 18, 21, 29, 31) + d(11, 20, 22) 12. Determine the MSP form of the Switching function (May/Jun-16) F(a, b, c, d)= _(0, 2, 4, 6, 8) + _d(10, 11, 12, 13, 14, 15)

UNIT II - COMBINATIONAL LOGIC Part A 2 Marks. 1. Define Combinational circuit (Nov/Dec-05,Nov/Dec-11,May/Jun-12,May/Jun-16) A combinational circuit consist of logic gates whose outputs at anytime are determined directly from the present combination of inputs without regard to previous inputs. 2. Explain the design procedure for combinational circuits (May/Jun-11) x Determine the number of available input variables & required O/P variables. x Assigning letter symbols to I/O variables x Obtain simplified Boolean expression for each O/P. x Obtain the logic diagram. 3. What is code conversion? If two systems working with different binary codes are to be synchronized in operation, then we need digital circuit, which converts one system of codes to the other. The process of conversion is referred to as code conversion. 4. What is code converter? It is a circuit that makes the two systems compatible even though each uses a different binary code. It is a device that converts binary signals from a source code to its output code. One example is a BCD to Xs3 converter. 5. Analysis procedure for combinational circuits x Find the given circuit is combinational or sequential. x Combinational circuit has a logic gate with no feedback paths or memory elements. x A feedback path is a connection from the output of one gate to the input of second gate that forms part of the input to the first gate 6. Design procedure for combinational circuits (May/Jun-14) i) Determine the required number of inputs and outputs and assign a symbol to each.

ii) Derive the truth table that defines the required relationship between inputs and outputs. iii) Obtain the simplified Boolean functions for each output as a function of the input variables. iv) Draw the logic diagram and verify the correctness of the design. 7. What is a half-adder? The combinational circuit that performs the addition of two bits is called a half-adder. 8. What is a full-adder? The combinational circuit that performs the addition of three bits is called a full-adder. 9. What is half-subtractor? The combinational circuit that performs the subtraction of two bits is called a halfsubtractor. 10. What is a full-subtractor? The combinational circuit that performs the subtraction of three bits is called a halfsubtractor. 11. What is Binary parallel adder? A binary parallel adder is a digital function that produces the arithmetic sum of two binary numbers in parallel. 14. Logic equation for half adder S=X Y C=X.Y 15. Limitations of Half-adder In multidigit addition, add two bits along with the carry of previous digit addition. Effectively such addition requires addition of three bits. This is not possible with half adder. Hence, half-adders are not used in practice. 16. Limitations of Half-adder In multidigit subtraction, subtract two bits along with the borrow of previous digit subtraction. Effectively such subtraction requires subtraction of three bits. This is not possible with half subtractor. 17. Define Hardware Description Language (HDL) (Nov/Dec-14) The size and complexity of the digital systems increases, they cannot be designed manually; their design is highly complex. At the most detailed level, they may consists of millions of elements i.e.) transistor or logic gates. So the computer-aided tools are used to design the Hardware Description Language. 18. Structure of Verilog module module <module name> <port list>;

<declares> items> endmodule <module 19. Operators in Verilog HDL x Boolean logical x Unary reduction logical x Bitwise logical x Relational x Binary arithmetic x Unary arithmetic 20. What is meant by look ahead carry? (Nov/Dec 2011, May/Jun 13, Apr/May 11) A carry-look ahead adder is a adder which is used to reduce the amount of time required and improves the speed of addition operation by predicting the carry of n th bit. 21.What is BCD adder? A BCD adder is a circuit that adds two BCD digits in parallel and produces a sum digit also in BCD. 22. What is Magnitude Comparator? (Nov/Dec 2011, May/Jun 13, Apr/May 11) A Magnitude Comparator is a combinational circuit that compares two numbers, A and B and determines their relative magnitudes. 23. What is decoder? A decoder is a combinational circuit that converts binary information from n input lines to a maximum of 2 n unique output lines. 24. What is encoder? An encoder is a combinational circuit that converts binary information from 2 n Input lines to a maximum of n unique output lines. 25. Define Multiplexing (Nov/Dec-13) Multiplexing means transmitting a large number of information units over a smaller number of channels or lines. 26. What is Demultiplexer? A Demultiplexer is a circuit that receives information on a single line and transmits this information on one of 2 n possible output lines. 27. What is the function of the enable input in a Multiplexer? The function of the enable input in a MUX is to control the operation of the unit. 28. Give the applications of Demultiplexer. (Nov/Dec-13)

Multiplexing means transmitting a large number of information units over a smaller number of channels or lines. 29. What is priority encoder? A priority encoder is an encoder that includes the priority function. The operation of the priority encoder is such that if two or more inputs are equal to 1 at the same time, the input having the highest priority will take precedence. 30. Can a decoder function as a Demultiplexer? i) It finds its application in Data transmission system with error detection. ii) One simple application is binary to Decimal decoder. 31. Mention the uses of Demultiplexer Demultiplexer is used in computers when a same message has to be sent to different receivers. Not only in computers, but any time information from one source can be fed to several places. 32. List basic types of programmable logic devices.. Read only memory. Programmable logic Array. Programmable Array Logic 33. List out the applications of multiplexer The various applications of multiplexer are a. Data routing. b. Logic function generator. c. Control sequencer. d. Parallel-to-serial converter. 34. List out the applications of decoder The applications of decoder are a. Decoders are used in counter system. b. They are used in analog to digital converter. c. Decoder outputs can be used to drive a display system. 35. Give other name for Multiplexer and Demultiplexer. x Multiplexer is otherwise called as Data selector. x Demultiplexer is otherwise called as Data distributor. 36. What is logic synthesis? (May/June 2011) 37. What are the modeling techniques in HDL? (May/June 2013,2012) 38. Give the need for using carry look ahead adder (nov/dec 2011)

Ans: To reduce the carry propagation delay and to reduce the complexity in designing combimnational circuis 39. Construct 4x16 decoder using 3x8 decoders. (Nov/dec2012) 40. Implement full adder using 2 half adders (Nov/dec2012) 41.Draw the truthtable for BCD to excess 3 code (Nov/Dec2013) Part B - 16 Marks 1. a. Explain the Design procedure for Combination Logic Circuits (6) b. Explain the Logic implementation of half adder and half-subtractor (10) 2. a. Explain Logical Implementation of Full adder and Full Subtractor (Nov/Dec-13) (10) b. Draw the Logic Diagram for BCD to Excess 3 code Converter with Explain (6) 3. a. Explain the analysis procedure for combinational circuit (May/Jun-12,May/Jun-14) (6) b. Explain the 4- bit Full adder (4) c. Explain the Block Diagram of BCD Adder (6) 4. a. Explain the 4 Bit Magnitude Comparator (May/Jun-15) (10) b. Explain the Design Procedure for HDL (6) 5. Design a logic circuit that accepts a 4-bit Grey Code and Converts it into 4-bit binary ( code. (May/Jun-16) M 6. Design a Full Adder with input x, y, z and two outputs S and C. The circuits performs x + y +z, z is the input carry, C is the output carry and S is the sum. (May/Jun-16) (10) 7. a. Explain the excess 3 to BCD Code Converter (May/Jun-13) (8) 8. a. Explain the Logic Diagram of 3 to 8 line Decoder (May/Jun-15) b. How to Construct the 4 x 16 Decoder with two 3 x 8 Decoder (8) 9. a. Explain the 4 to 1 line Multiplexer (Nov/Dec-15) (8) b. Explain the 2 to 1 line Multiplexer (8) 10. Implement Boolean function using mux (Nov/Dec-11) (8) F=sum (1,2,5,6,8,9,10,15,14)

11. Construct 5 to 32 decoder using one 2 to 4decoder and four 3 to 8 decoder (Nov/Dec-12) 12. Construct 4 x16 decoder using 2 3x8 decoders with enable input (Nov/Dec2013) 13.Explain the Design Procedure for HDL 14.Explain the binary adder/subtractor circuit (April/may 2010) 15.Discuss the carry look ahead adder generation (April/may 2010) 16.Design binary multiplier circuit (Nov/Dec2010) 17. What is meant by model and modeling techniques in HDL? UNIT III SYNCHRONOUS SEQUENTIAL LOGIC Part A 2 Marks 1. What is sequential circuit? (Nov/Dec-14) Sequential circuit is a broad category of digital circuit whose logic states depend on a specified time sequence. A sequential circuit consists of a combinational circuit to which memory elements are connected to form a feedback path.

2. List the classifications of sequential circuit. i) Synchronous sequential circuit. ii) Asynchronous sequential circuit. 3. What is Synchronous sequential circuit? A Synchronous sequential circuit is a system whose behavior can be defined from the knowledge of its signal at discrete instants of time. 4. What is a clocked sequential circuit? (May/Jun-11,Nov/Dec-12) Synchronous sequential circuit that use clock pulses in the inputs of memory elements are called clocked sequential circuit. One advantage as that they don t cause instability problems. 5. What is called latch? Latch is a simple memory element, which consists of a pair of logic gates with their inputs and outputs inter connected in a feedback arrangement, which permits a single bit to be stored. 6. List different types of flip-flops. i) SR flip-flop ii) Clocked RS flip-flop iii) D flip-flop iv) T flip-flop v) JK flip-flop vi) JK master slave flip-flop 7. What do you mean by triggering of flip-flop? The state of a flip-flop is switched by a momentary change in the input signal. This momentary change is called a trigger and the transition it causes is said to trigger the flip-flop. 8. What is an excitation table? (Nov/Dec-13) During the design process we usually know the transition from present state to next state and wish to find the flip-flop input conditions that will cause the required transition. A table which lists the required inputs for a given chance of state is called an excitation table. 9. Give the excitation table of JK-flip flop? (May/Jun-15, May/Jun-16) Present state Next state Flip-flop Inputs Qn Qn+1 J K 0 0 0 X 0 1 1 X

1 0 X 1 1 1 X 0 10. Give the excitation table of SR-flip flop? (Nov/Dec-14) Present state Next state Flip-flop Inputs Qn Qn+1 R S 0 0 X 0 0 1 0 1 1 0 1 0 1 1 0 X 11. What is counter? A counter is used to count pulse and give the output in binary form. 12. What is synchronous counter? (Nov/Dec-13) In a synchronous counter, the clock pulse is applied simultaneously to all flip-flops. The output of the flip-flops change state at the same instant. The speed of operation is high compared to an asynchronous counter 13. What is Asynchronous counter? In an Asynchronous counter, the clock pulse is applied to the first flip-flops. The change of state in the output of this flip-flop serves as a clock pulse to the next flip-flop and so on. Here all the flip-flops do not change state at the same instant and hence speed is less. 14. What is the difference between synchronous and asynchronous counter? Synchronous counter: 1. Clock pulse is applied simultaneously Clock pulse is applied to the first flip-flop, the change of output is given as clock to next flip-flop Asynchronous counter: 1. Speed of operation is high Speed of operation is low. 15. Name the different types of counter. a) Synchronous counter b) Asynchronous counter i) Up counter ii) Down counter iii) Modulo N counter iv) Up/Down counter. 16. What is up counter? A counter that increments the output by one binary number each time a clock pulse is applied. 18. What is down counter?

A counter that decrements the output by one binary number each time a clock pulse is applied. 19. What is up/down counter? A counter, which is capable of operating as an up counter or down counter, depending on a control lead. 20. What is a ripple counter? A ripple counter is nothing but an asynchronous counter, in which the output of the flipflop changes state like a ripple in water. 21. What are the uses of a counter? i) The digital clock ii) Auto parking control iii) Parallel to serial data conversion. 22. What is Johnson counter? It is a ring counter in which the inverted output is fed into the input. It is also known as a twisted ring counter. 23. Define Flip flop. (May/Jun-15) The basic unit for storage is flip flop. A flip-flop maintains its output state either at1 or 0 until directed by an input signal to change its state. 24. Give the comparison between combinational circuits and sequential circuits Combinational circuits Memory unit is not required Parallel adder is a combinational circuit Sequential circuits Memory unit is required Serial adder is a sequential circuit. 25. Design a 3-bit ring counter and find the mod of the designed counter. (Nov/Dec 12). 26. What is Excitation table? (May/June 08) 27. What is race around condition? (May/June 08) 28. What are the classifications of synchronous sequential circuits? (Nov/Dec 12) 29. Classify the registers with respect to serial and parallel input output. (May/June 07) 30. What is a sequence generator? (May/June 06) 31. Define state assignment. (Nov/Dec 05) 32. Write the characteristic equation of a JK flip-flop. (May/Jun-14, 05) 33. Convert D flip-flop to T flip flop. (May/June 13, Nov/Dec 12) 34.What is the minimum number of Flip-Flop needed to build a counter of modulus 8 (May/Jun-16)

35.What is Lockout? How it is avoided? (May/Jun-16) PART B 1. Write down the characteristic equation and explain the operation of JK-Flip-Flop. 2. Draw the logic diagram of D-FF using NAND gates and explain. (Nov/Dec 2008) 3. Explain the operation of a JK master slave flip-flop. (Nov/Dec 2009) (ii) Convert D-flip-flop to JK flip- 4. How will you convert the following flip-flop? (i) Convert JK flip-flop to SR flip-flop. (May/Jun 2007) flop. (iii) Convert T-flip-flop to SR flip-flop. 5. Draw the clocked RS flip-flop and explain with truth table. (May/Jun 2007) 6. Design a 3-bit modulo 5 synchronous counter using JK flip-flop. (May/Jun 2008, May/Jun-16) 7. Draw a 3-bit reversible counter and explain its operation. (May/Jun 2006) 8. Explain the working of a BCD-ripple counter with timing diagram. (Nov/Dec 2004) 9. Design a 3-bit asynchronous ripple counter using T-flip-flops and explain its operation. (May/Jun 2009) 10. Draw a 3-bit universal shift register and explain. (May/Jun 2009) 11. Design a clocked sequential machine using T-Flip-Flop for the following state diagram. Use straight binary state assignment. (Apr/May 2011)

12. Design a synchronous sequential circuit using T Flip-Flop for the given state diagram. (May/Jun-13) 13. Implement the following Boolean function with a 4x1 Multiplexer and External Gates. Connects inputs A and B to the selection lines. The input requirements for the four data lines will be a function of variables C and D these values are obtained by expressing F as a function of C and D for each of the four cases when AB = 00, 01, 10 and 11. These function may have to be implemented with external gates. F(A, B, C, D) = (1, 2, 5, 7, 8, 10, 11, 13, 15). (May/Jun-16) 14. Design a binary counter using T Flip flops to count in the following sequence. i) 000, 001, 010, 011, 100, 101, 111, 000 (May/Jun-16) ii) 000, 100, 111, 010, 011, 000 UNIT IV

ASYNCHRONOUS SEQUENTIAL LOGIC Part A 2 Marks 1. Define Asynchronous sequential circuit? In asynchronous sequential circuits change in input signals can affect memory element at any instant of time. 2. Comparison between synchronous & Asynchronous sequential circuits? (May/Jun-12) Synchronous sequential circuits Memory elements are clocked flipflops Easier to design. Asynchronous sequential circuits Memory elements are either unlocked flip flops or time delay elements. More difficult to design. 3. What is fundamental mode sequential circuit? -input variables changes if the circuit is stable -inputs are levels, not pulses -only one input can change at a given time. 4. What is the significance of state assignment? In synchronous circuits-state assignments are made with the objective of circuit reduction. Asynchronous circuits-its objective is to avoid critical races. 5. When do race conditions occur? (May/Jun-11,May/Jun-13,Nov/Dec-13) Two or more binary state variables change their value in response to the change in input variable. 6. Write short note on shared row state assignment. (May/Jun-13) Races can be avoided by making a proper binary assignment to the state variables. Here, the state variables are assigned with binary numbers in such a way that only one state variable can change at any one state variable can change at any one time when a state transition occurs. To accomplish this, it is necessary that states between which transitions occur be given adjacent assignments. Two binary are said to be adjacent if they differ in only one variable. 7. Write short note on one hot state assignment. The one hot state assignment is another method for finding a race free state assignment. In this method, only one variable is active or hot for each row in the original flow table, i.e., it requires one state variable for each row of the flow table. Additional row are introduced to provide single variable changes between internal state transitions.

8. What are the different techniques used in state assignment? x shared row state assignment x one hot state assignment 9. What are the steps for the design of asynchronous sequential circuit? -construction of primitive flow table -reduction of flow table -state assignment is made -realization of primitive flow table 10. What is hazard? Hazard is an unwanted switching transient. 11. What are the steps for the design of asynchronous sequential circuit? 1. Construction of a primitive flow table from the problem statement. 2. Primitive flow table is reduced by eliminating redundant states using the state reduction 3. State assignment is made 4. The primitive flow table is realized using appropriate logic elements. 12. Give the comparison between state Assignment Synchronous circuit and state assignment asynchronous circuit. In synchronous circuit, the state assignments are made with the objective of circuit reduction. In asynchronous circuits, the objective of state assignment is to avoid critical races. 13. What are races? (Nov/Dec-12,May/Jun-15) When 2 or more binary state variables change their value in response to a change in an input variable, race condition occurs in an asynchronous sequential circuit. In case of unequal delays, a race condition may cause the state variables to change in an unpredictable manner. 14. Define non critical race. (Nov/Dec-14,May/Jun-16) If the final stable state that the circuit reaches does not depend on the order in which the state variable changes, the race condition is not harmful and it is called a non critical race. 15. Define critical race? (May/Jun-16) If the final stable state depends on the order in which the state variable changes, the race condition is harmful and it is called a critical race. 16. Define flow table in asynchronous sequential circuit. In asynchronous sequential circuit state table is known as flow table because of the behavior of the asynchronous sequential circuit. The stage changes occur in independent of a clock, based on the logic propagation delay, and cause the states to flow from one to another. 17. Define merger graph. (Nov/Dec-12)

The merger graph is defined as follows. It contains the same number of vertices as the state table contains states. A line drawn between the two state vertices indicates each compatible state pair. It two states are incompatible no connecting line is drawn. 18. What is fundamental mode? (May/Jun-10) A transition from one stable state to another occurs only in response to a change in the input state. After a change in one input has occurred, no other change in any input occurs until the circuit enters a stable state. Such a mode of operation is referred to as a fundamental mode. 19. What is essential hazard? (May/Jun-11) Essential hazard is the result of the effects of a single input variable change reaching one feedback path before another feedback path. In particular, as a result of a single input variable change, a state variable may also change. 20. How essential hazard can be eliminated? Essential hazard can always be eliminated in a realization by the insertion of sufficient delays in the feedback paths. 21. What are the problems involved in asynchronous circuits? The asynchronous sequential circuits have three problems namely, 1. Cycles 2. Races 3. Hazards 22. List the different techniques used for state assignment. a. Shared row state assignment b. One hot state assignment 23. What is static-0 hazard? When the output is to remain at the value 0 and a momentary 1 output is possible during the transition between the two input states, then the hazard is called as static-0 hazard. 24. What is static-1 hazard? When the output is to remain at the value 1 and a momentary 0 output is possible during the transition between the two input states, then the hazard is called a static-1 hazard.

25. What is synchronous sequential circuit? (Nov/Dec 13) Synchronous sequential circuit is a system whose behaviour can be defined from the knowledge of its signals at discrete instants of time. 26 What are the two types of asynchronous sequential circuits? (Apr/May 11) Sequential circuits without clock pulses are called asynchronous sequential circuits. They are classified into two types. (1) Fundamental mode (2) Pulse mode 27.Differentiate fundamental mode and pulse mode asynchronous sequential circuits. (Nov/Dec 12, Nov/Dec 11) S.No. Fundamental Mode Pulse Mode 1. Input variables are levels. Input variables are pulses. 2. Delay lines are used as a memory element. Flip-flops are used as a memory element. 28. Write short notes on Hazards. (Nov/Dec 13) A hazard is the potential or actual malfunction of a logic network during the transition between two input states as a result of a single variable change, where a malfunction is any deviation from the intended response. 29. Design a 3 input AND gate using verilog. (Nov/Dec 12) 30.Draw the wave forms showing static 1 hazard? (May/Jun-16)

PART B 1. Write short notes on the following: (i) Stable state (ii) Unstable state (iii) Cycles (iv) Races (Nov/Dec 2003) 2. Write the design procedure of asynchronous sequential circuit. 3. Describe the hazards that could occur in asynchronous sequential circuit. What are the ways in which they get eliminated. (Nov/Dec 2005, 2008) 4. Draw the fundamental mode asynchronous sequential circuit and explain in detail. 5. Define the terms: (Nov/Dec 2006, May/June 2009) (Nov/Dec 2006) (i) Critical race, (ii) Non-critical race, (iii) Flow table 6. Design an asynchronous circuit that will output only the first pulse received whenever a control I/P is asserted from low to high state. Any further pulses will be ignored. (May/June 2008) 7. Explain briefly the dynamic and essential hazards. (May/June 2009) 8. Design a circuit with primary inputs A and B to give an output Z equal to 1 when A becomes 1 if B is already 1. Once Z = 1, it will remain so until A goes to 0. Draw state diagram, wave form, primitive flow table for designing this circuit. (May/June 13) 9. Design a circuit with inputs A and B to give an output Z = 1 when AB = 11 but only if A becomes 1 before B, by drawing total state diagram, primitive flow table and output map in which transient state is included. (May/June -12)

10. Design an asynchronous sequential circuit that has two inputs X2 and X1 and one output Z. When X1 = 0, the output Z is 0. The first change in X2 that occurs while X1 is 1 will cause output Z to be 1. The output Z will remain 1 until X1 returns to 0. (Nov/Dec 2008, May/June 2009) 11. Design an asynchronous sequential circuit with 2 inputs X and Y and with one output Z whenever Y is 1, input X is transferred to Z. when Y is 0; the output does not change for any change in X. use SR latch for implementation of the circuit. (May/Jun-16) 12.Discuss in detail the procedure for reducing the flow table with an example. (May/Jun-16) UNIT V MEMORY AND PROGRAMMABLE LOGIC Part A 2 Marks 1. List basic types of programmable logic devices.. Read only memory. Programmable logic Array. Programmable Array Logic 2 Explain ROM A read only memory (ROM) is a device that includes both the decoder and the OR gates within a single IC package. It consists of n input lines and m output lines. Each bit combination of the input variables is called an address. Each bit combination that comes out of the output lines is called a word. The number of distinct addresses possible with n input variables is 2 n. 3. Define address and word In a ROM, each bit combination of the input variable is called on address. Each bit combination that comes out of the output lines is called a word. 4. What is programmable logic array? How it differs from ROM? In some cases the number of don t care conditions is excessive, it is more economical to use a second type of LSI component called a PLA. A PLA is similar to a ROM in concept; however it does not provide full decoding of the variables and does not generates all the minterms as in the ROM. 5. What is memory and draw the block diagram of memory cell.

6. What is the difference between programmable array logic (PAL) and programmable logic array (PLA) 7.. State the types of ROM x Masked ROM. x Programmable Read only Memory x Erasable Programmable Read only memory. x Electrically Erasable Programmable Read only Memory. 8. What is volatile and non-volatile memory? (Nov/Dec 2013) Volatile memory: It is a memory unit which lose stored information when power is turned off. Example: RAM Non-volatile memory: It is a memory unit which retains stored information, even though power is turned off. Example: ROM and magnetic disc 9. Give the advantages of RAM. (Nov/Dec 2013) a. Fast operating speed. b. Read out of a RAM does not affect the content stored. c. Low power dissipation less than 0.5 MW per bit. (iv) It has self compatible. 10. What are the different types of programmable logic devices? (May/June 2013) The types of programmable logic devices are: a. Programmable Read Only Memory (PROM) b. Programmable Array Logic (PAL) (iii) Programmable Logic Array (PLA) (iv) Field Programmable Gate Array (FPGA) 11. Distinguish between PLA and PAL. (May/June 2013, Apr/May 2011) (i) PLA Both AND and OR arrays are programmable. PAL OR Array is fixed and AND array is programmable. (ii) Costliest and complex. Cheaper and simple. (iii) Reprogrammed easily. Complex to reprogram. 12. Give the difference between RAM and ROM? (Nov/Dec 2011) RAM ROM

(i) RAM has both read and write capability. ROM has only read operation. (ii) It is volatile memory. It is non-volatile memory. (iii) It is faster and costly. It is slow and cheap. 13.What is masked ROM? It is a type of ROM which stores the data permanently into the memory device during the manufacturing process. 14.Write short-notes on PROM. PROM is a Programmable Read Only Memory. It allows uses to store data or program. PROMs use the fuses with material like nichrome and polycrystalline. The user can blow these fuses by passing around 20 to 50 ma of current for the period of 5 to 20 s. The blowing of fuses is called programming of ROM. 15. Write short notes on EPROM. EPROM is Erasable Programmable Read Only Memory. EPROM use MOS circuitry. They store 1s and 0s as a packed of charge in a buried layer of the IC chip. We can erase the stored data in the EPROMs by exposing the chip to ultra violet light via its quartz window for 15 to 20 minutes. It can be reprogrammed. 16.Write short notes on EEPROM. EEPROM Electrically Erasable PROM. It use MOS circuitry. Data is stored as charge or no change of an insulated layer or an insulated floating gate in the device. 17. Define static RAM and dynamic RAM. Static RAM use flip-flops as storage elements and therefore store data indefinitely as long as dc power is applied. Dynamic RAM use capacitors as storage elements and cannot retain data very long without capacitors being recharged by a process called refreshing. 18. Define address and word. In a ROM, each bit combination of the input variable is called on address. Each bit combination that comes out of the output lines is called a word. 19. How many address inputs, data inputs and data outputs are required for a 16k 12 memory?

Since there are 12 bit per word. So this memory requires 12 data inputs and 12 data outputs. The total number of memory locations is 16 k i.e., 16 2 10 = 2 4 2 10 = 2 14 locations. It requires 14 address inputs. 20. What is Combinational PLD The PROM is a Combinational Programmable Logic Device. A combinational PLD is an integrated circuit with programmable gates divided into an AND array and an OR array to provide an AND-OR sum of product implementation. There are three major types of combinational PLDs and they differ in the placement of the programmable connections in the AND-OR array. 21. How is individual location in a EEPROM Programmed or erased? (May/June 2006) Since it is electrically erasable memory by activating particular row and column. It is possible that individual can be programmed or erased. 22. Define cache memory. It is a relatively small, high-speed memory that can store the most recently used instructions of data from larger but slower main memory. 23. Give the features of UV EPROM. UV EPROM is electrically programmable by the user, but the stored data must be erased by exposure to ultra-violet (UV) light over a period of several minutes. 24. What are flash memories? They are high density read/write memories that are non-volatile, which means data can be stored indefinitely without power. 25. What are the terms that determine the size of PAL? The size of a PLA is specified by the (i) Number of inputs (ii) Number of product terms (iii) Number of outputs 26.What is volatile and non-volatile memory? (Nov/Dec 2013) Volatile memory: It is a memory unit which lose stored information when power is turned off. Example: RAM Non-volatile memory: It is a memory unit which retains stored information, even though power is turned off. Example: ROM and magnetic disc 27. Give the advantages of RAM. (Nov/Dec 2013)

(i) Fast operating speed. (ii) Read out of a RAM does not affect the content stored. (iii) Low power dissipation less than 0.5 MW per bit. (iv) It has self compatible. 28. What are the different types of programmable logic devices? (May/June 2013) The types of programmable logic devices are: (i) Programmable Read Only Memory (PROM) (ii) Programmable Array Logic (PAL) (iii) Programmable Logic Array (PLA) (iv) Field Programmable Gate Array (FPGA) Part B 1. Write notes on RAM, its operation and its types (May/Jun-12,Nov/Dec-15) 2. Discuss the operation of memory decoding and elaborate its application as address multiplexing and coincident decoding circuits 3 a. Explain the Programmable Logic array (May/Jun-10) (8) b. Explain the Programmable array Logic (Nov/Dec-15) (8) 4. a. Comparison between PROM, PLA and PAL (May/Jun-10,May/Jun-13) b. Realise the function gives using a PLA with 6 Input, 4 Outputs and 10 AND gates (10) F1(A,B,C,D,E,F) = (0,1,7,8,9,10,11,15,19,23,27,31,32,33,35,39,40,41,47,63) (Nov/Dec-10) 5. Draw the basic block diagram of PLA device and Implement the following (Nov/Dec-13) F2(A,B,C,D,E,F) = (8,9,10,11,12,14,21,25,27,40,41,42,43,44,46,57,59) using PAL 6. Write notes on PLA and PAL (Nov/Dec-14,May/Jun-15)

7. Define Memory and discuss the operation & types of RAM and ROM (May/Jun-12 Nov/Dec- 14) 8. Elaborate the construction of sequential programmable devices in detail 9. Explain ASIC in detail 10. Implement following function using PLA (May/Jun-14,May/Jun-16) (8) Z1= ab d e+a b c d e +bc+de, Z2=a c e, Z3=bc+de+c d e+bd, Z4=a c e+ce using 5x8x4 PLA 11. Implement the two following Boolean function using 8x2 PROM. (May/Jun-13) F (x,y,z) = 13,5,6,7 F (x,y,z) = 1,2,3,4 12.Briefly discuss the sequential Programmable Devices. 13.Implement the following two Boolean function with a PLA F1 = AB + AC + A B C and F2 = (AC + BC) (May/Jun-15) (May/Jun-15)