Source: M. Morris Mano and Michael D. Ciletti, Digital Design, 4rd Edition, 2007, Prentice Hall. Register Transfer Level in Verilog: Part II Lan-Da Van ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2014 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/
Sequential Binary Multiplier A numerical example: 23 10111 multiplicand 19 10011 multiplier 10111 10111 00000 00000 10111 437 110110101 product The product obtained from the multiplication of two binary numbers of n bits each can have up to 2n bits. 2
Sequential Binary Multiplier Among many possibilities for distributing the effort of multiplication over multiple clock cycles: only one partial product is formed and accumulated in a single cycle of the clock Instead of shifting the multiplicand to the left, the partial product being formed is shifted to the right. When the corresponding bit of the multiplier is 0, there is no need to add all 0 s to the partial product 3
ASMD Chart Block diagram Datapath 4
ASMD Chart 5
A: a shift register with parallel load and a synchronous clear Q: a shift register with parallel load P: a binary down counter with parallel load C: a flip-flop with synchronous clear B: registers parallel load ASMD Chart 6
Design of a digital system Control Logic Control logic of the control unit Register transfer in the datapath unit 7
Control Logic-State Assignment only one bit change uses as many bits as there are states in the circuit (uses a flip-flop for each state) 8
Control Logic-Controller Design Designed manually by The sequential logic procedure outlined in Chapter 5 The sequence-register-and-decoder method One-hot design (one flip-flop per state) Automatically synthesizing the circuit from an HDL description. 9
Sequence Register and Decoder T 0 T 1 T 2 (shaded outputs: Moore-type) DG1 = T1 DG0 = T0 Start + T2 Zero' 10
Sequence Register and Decoder Instead of using flip-flop outputs, we use the outputs of the decoder to indicate the present-state condition of the sequential circuit. 11
One-Hot Design (One Flip-Flop Digital Circuit Lab per State) G1 G0 G2 By inspection! DG0 = G0 Start' + G2 Zero DG1 = G0 Start + G2 Zero' DG2 = G1 12
One-Hot Design G0 G1 By inspection! DG0 = G0 Start' + G2 Zero DG1 = G0 Start + G2 Zero' G2 DG2 = G1 13
One-Hot Design (One Flip-Flop Digital Circuit Lab per State) DG0 = G0 Start' + G2 Zero DG1 = G0 Start + G2 Zero' DG2 = G1 14
HDL of Binary Multiplier 15
default next_state=s_idle; 16
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Testing the Multiplier 18
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FIGURE 8.19 Simulation waveforms for one-hot state controller 22
Behavioral HDL of a Parallel Multiplier 23
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Design with Multiplexers Sequence-register-and-decoder scheme Replacing the gates with multiplexers results in a regular pattern of three levels of components. The first level consists of multiplexers that determine the next state of the register. The second level contains a register that holds the present binary state. The third level has a decoder that asserts a unique output line for each control state. 26
An example ASM chart ASMD chart No datapath annotations No outputs ASM chart 27
An example (cont.) 4-state Controller Design with Multiplexers Three-level implementation TBD (present state) 28
An example (cont.) 29
An example (cont.) (two gates) 30
Design Example: Count the Number of Ones in a Register Block diagram 31
Design Example (cont.) Complete ASMD chart 32
Design Example (cont.) 33
Design Example (cont.) 34
Design Example (cont.) Control implementation 35
HDL Example HDL Example 8.8 36
HDL Example Digital Circuit Lab 37
HDL Example 38
HDL Example 39
HDL Example 40
HDL Example 41
HDL Example 42
HDL Example 43
HDL Example 44
Simulation waveforms 45
Simulation waveforms (cont.) 46