CCD Linear Image Seor MN36 6-Bit CCD Linear Image Seor Overview The MN36 is a 6-pixel high seitivity CCD linear image seor combining photo-sites using low dark output floating photodiodes and CCD analog shift registers for read out. It provides large output at a high S/N ratio for visible light inputs over a wide range of wavelength. Features 6 floating photodiodes and n-channel buried type CCD shift registers for read out are integrated in a single chip. Extremely high seitivity has been obtained by employing an onchip voltage amplifier circuit. Use of photodiodes with a new structure has made the dark output voltage very low. All the input pulses can be driven by CM 5-type logics. Has a smooth spectral characteristics that is close to the seitivity of the human eye in the entire visible region. Large signal output of typically 7m at saturation can be obtained. Operation with a single + positive power supply. Block Diagram SS SG 9 Signal output amplifier Compeation output amplifier Clock driver 3 4 6 DD R DD R B to B5 : Black reference pixels D to D6 : Dummy invalid pixels 3 4 5 6 7 8 9 6 9 8 7 6 5 4 3 (Top iew) C WDIP-G-47 B B B3 B5 B5 D D D3 3 4 5 Pin Assignments 57 58 59 6 D4 D5 D6 SS SG Application Graphic and character read out in fax machines, image scanners, etc. Measurement of position and dimeio of objects. includes following four Product lifecycle stage.
MN36 CCD Linear Image Seor Absolute Maximum Ratings (Ta=5 C, SS=) Parameter Symbol Rating Unit Power supply voltage Input pin voltage Output pin voltage Operating temperature range Storage temperature range DD I O Topr Tstg.3 to +5.3 to +5.3 to +5 5 to + 6 4 to + C C Operating Conditio oltage conditio (Ta= 5 to +6 C, SS=) Power supply voltage CCD shift register clock High level CCD shift register clock Low level Shift gate clock High level Shift gate clock Low level Reset gate clock High level Reset gate clock Low level DD H L SH SL RH RL.4. 5.. 5.. 5.. 3. 5.5.5 5.5.5 5.5.5 Timing conditio (Ta= 5 to +6 C) Shift register clock (, ) frequency fc See drive timing diagram. f C =/T.5. MHz Reset clock ( R ) frequency fr See drive timing diagram. f R =/T.. MHz Shift register clock (, ) rise time t Cr 6 See drive timing diagram Shift regisster clock (, ) fall time t Cf 6 Shift clock ( SG ) rise time Shift clock ( SG ) fall time t Sr t Sf 5 5 Shift clock set up time t Ss See drive timing diagram Shift clock pulse width Shift clock hold time Reset clock rise time tsw t Sh trr 5 3 Reset clock fall time trf 5 3 See drive timing diagram Reset clock pulse width trw 4 5 Reset clock hold time trh 5 Electrical Characteristics Clock input capacitance (Ta= 5 to +6 C) Shift register clock input capacitance C,C 35 4 pf IN = Reset clock input capacitance CR 5 3 pf f =MHz Shift clock input capacitance CS 3 pf includes following four Product lifecycle stage. DC characteristics Power supply current IDD DD = + 8 5 ma AC characteristics Signal output delay time t
CCD Linear Image Seor MN36 Optical Characteristics <Ipection conditio> Ta=5 C, DD =, H = SH = RH =5 (pulse), f C =.5MHz, f R =MHz, T int (accumulation time)=ms Light source: Daylight type fluorescent lamp Optical system: A slit with an aperture dimeio of mm mm is used at a distance of mm from the seor (equivalent to F=). Load resistance = k Ohms These specificatio apply to the 6 valid pixels excluding the dummy pixels D to D6. Respoivity R 38 45 5 /lx s Photo respoe non-uniformity Odd/even bit non-uniformity Saturation output voltage Saturation exposure Dark signal output voltage Dark signal output non-uniformity Shift register total trafer efficiency Output impedance Dynamic range Signal output pin DC level Compeation output pin DC level PRNU O/E SAT SE DRK NU STTE ZO DR Note Note Note 3 Note 3 Dark condition, see Note 4 Dark condition, see Note 4 Note 5 Note 6 Note 6.5.9 9 3.5 3.5.7.38.8. 5 3. 3. 6. 6. % % lx s m m % kω Signal and compeation output pin DC level difference Note 6 5 m Note ) The photo respoe non-uniformity (PRNU) is defined by the following equation, where X ave is the average output voltage of the 6 valid pixels and x is the absolute value of the difference between X ave and the voltage of the maximum (or minimum) output pixel, when the surface of the photo-sites is illuminated with light having a uniform distribution over the entire surface. PRNU= x (%) X ave The incident light inteity shall be 5% of the standard saturation light inteity. Note ) The odd/even bit non-uniformity (O/E) is defined by the following equation, where X ave is the average output voltage of the 48 valid pixels and Xn is the output voltage of the n th pixel, when the surface of the photo-sites is illuminated with light having a uniform distribution over the entire surface. 59 O/E= Xn Xn+ n= (%) 59 X ave In other words, this is the value obtained by dividing the average of the output difference between the odd and even pixels by the average output voltage of all the valid pixels. The incident light inteity shall be 5% of the standard saturation light inteity. Note 3) The Saturation output voltage ( SAT ) is defined as the output voltage at the point when the linearity of the photoelectric characteristics cannot be maintained as the incident light inteity is increased. (The light inteity of exposure at this point is called the saturation exposure.) Note 4) The dark signal output voltage ( DRK ) is defined as the average output voltage of the 6 pixels in the dark condition at Ta=5 C and T int =ms. Normally, the dark output voltage doubles for every 8 to C rise in Ta, and is proportional to T int. The dark signal output non-uniformity (NU) is defined as the difference between the maximum output voltage among all the valid pixels and DRK in the dark condition at Ta=5 C and T int =ms. includes following four Product lifecycle stage. DRK NU Note 5) The dynamic range is defined by the following equation. Since the dark signal voltage is proportional to the accumulation time, the dynamic range becomes wider when the accumulation time is shorter. DR= SAT DRK
MN36 CCD Linear Image Seor Optical Characteristics (continued) Note 6) The signal output pin DC level ( ) and the compeation output pin DC level ( ) are the voltage values shown in the following figure. Reset feed through level SS SS Pin Descriptio Pin No. Symbol Pin name Condition 3 4 5 DD R Signal output Compeation output Power supply Reset clock 6 CCD Clock (Phase ) 7 8 9 3 4 5 6 7 8 9 CCD Clock (Phase ) SG Shift gate clock Ground Note) Connect all pi externally to SS. Cotruction of the Image Seor SS The MN36 can be made up of the three sectio ofa) photo detector region, b) CCD trafer region (shift register), and c) output region. a) Photo detector region The photoelectric conversion device coists of an µm floating photodiode and a 3µm channel stopper for each pixel, and 6 of these devices are linearly arranged side by side at a pitch of 4µm. The photo detector's windows are 4µm 4µm squares and light incident on areas other than these windows is optically shut out. The photo detector is provided with 5 optically shielded pixels (black dummy pixels) which serve as the black reference. b) CCD Trafer region (shift register) The light output that has been photoelectrically converted is traferred to the CCD trafer for each odd and even pixel at the timing of the shift clock ( SG ). The optical signal electric charge traferred to this analog shift register is successively traferred out and guided to the output region. A buried type CCD that can be driven by a two phase clock (, ) is used for the analog shift register. c) Output region The signal charge that is traferred to the output region is sent to the detector where voltage amplification is executed and impedance traformation is done using source follower stage. The DC level component and the clock noise component not containing optical signals are output from the pin. By carrying out differential amplification of the two outputs and externally, it is possible to obtain an output signal with a high S/N ratio by reducing the clock noise, etc. includes following four Product lifecycle stage.
CCD Linear Image Seor MN36 Timing Diagram () I/O timing SG INTEGRATION TIME (Tint.) SG t Sr t Sf t Cr t Cf 9% 9% % 9% 5% % t RS 9% R 5% % t Ss R () Drive timing t SW t Sh Graphs and Characteristics 3 4 6 7 8 9 58 59 6 6 6 63 64 65 66 4 6 3 5 3 4 6 7 8 B B B 5 B 5 B 5 Blank feed (for 8 pixels) Relative respoivity (%) 8 6 4 59 D D D 3 Black reference 3 6 D 4 D 5 D 6 pixel signal (for 5 pixels) alid pixel signal (for 6 pixels) Invalid pixel signal (for 3 pixels) 9% t Rr t RW t Invalid pixel signal (for 3 pixels) trf 9% % T Under standard operating condition Note) t Rh Repeat the trafer pulses (cp) for more than 4 periods. Reference level Spectral Respoe Characteristics Signal output voltage includes following four Product lifecycle stage. 4 5 6 7 8 Wavelength (nm)
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