Falling-edge flip-flop Difference with latch: output changes on (not after) falling clock edge 53
Falling-edge flip-flop Clocked operation: Note clock edges. 54
Falling-edge flip-flop Data must be valid before falling edge of clock and must stay valid until output is set (propagation). Setup and hold time. 55
Register files Think MIPS: Registers can be read and written in one instruction (often possible in one clock cycle) One instruction can, at most, read two registers and write one register To address registers we need a number. This points us to chose a decoder and a multiplexer. Need two inputs, one output We also need memory. This points us to Data flip-flops If we read a register, number suffices. If we write a register, we also need data and a decoder 56
Register file simplified 57
Register read ports Register number selects register in decoder AND gate in multiplexer outputs one selected register 58
Register write port Write signal activates write operation Each register implemented with flipflops Remember, flip-flops change on the clock edge This enables simultaneous read and write in one cycle 59
Random Access Memories Two flavours: SRAM: data stored statically (as in flip-flops) DRAM: data stored but needs to be refreshed continuously SRAM is the material used for caches DRAM used for main memory 60
SRAM Array of memory cells Fixed time to any datum Characterized by two values: How many entries, e.g. 4M How many bits per entry, e.g. 8 bits. Entries define the number of address lines Example:4M x 8, 4M=2 22, need 22 address lines, 8-bit input line, 8-bit output line 61
SRAM Example 2M x 16 2-4 ns latency for thin SRAMs 8-20ns for thick SRAMS Setup and hold times for writes Can not implement with MUX! (too expensive) 62
Tri-state buffers Selects one output Enables memory cells (flip-flops) to share an output line Has a highimpendance state to disable cell output 63
Small SRAM example (4 by 2) 64
Large SRAM with feasible decoder 65
DRAM SRAMs expensive (flip-flop per bit of output) 4-6 transistors for the needed logic gates DRAM concept Use single transistor per cell, which is either charged or not charged Charge can be stored in a capacitor, which unfortunately loses charge with time Needs refreshing, hence the term dynamic RAM. Refreshing amounts to reading and writing back the content Charge can be kept for several ms. Memory controller responsible for refreshing Refresh operations need to overlap with normal read-write accesses 66
Two-level DRAM access Row decoder 1-to-2048 2048 x 2048 array Address [21-11] Address[10-0] Column latches Mux Dout 67
Finite state machines Systems with state, which depends on both the inputs and the previous state of the system Two functions: next state and output States correspond to all possible values of internal storage (n bits, 2 n states) Output combines current state and inputs. Moore machines and Mealy machines We discuss synchronous state machines, controlled with a clock 68
State machine 69
Example: traffic light Traffic lights in north-south, east-west intersection NSlite, EWlite signals that assert green light in each direction NScar, EWcar signals from sensors detecting car presence in each direction Rules: Light changes to green if car waiting; otherwise green light is the one of the last car that crossed the intersection Assume 30 seconds cycle in each direction Need two states, NSgreen, EWgreen 70
State and output functions Current state nscar ewcar next state nsgreen 0 0 nsgreen nsgreen 0 1 ewgreen nsgreen 1 0 nsgreen nsgreen 1 1 ewgreen ewgreen 0 0 ewgreen ewgreen 0 1 ewgreen ewgreen 1 0 nsgreen ewgreen 1 1 nsgreen Output function nslite ewlite nsgreen 1 0 ewgreen 0 1 71
Graphical representation of FSM 72
FSM implementation 73
FSM Implementation State assignment, let nsgreen=0, ewgreen=1 NextState=CurrentState EWcar CurrentState NScar NSlite=CurrentState EWlite=CurrentState 74