Page 1/11 Instructions: urn off all cell phones, beepers and other noise making devices. Show all work on the front of the test papers. Box each answer. If you need more room, make a clearly indicated note on the front of the page, "MORE ON BACK", and use the back. he back of the page will not be graded without an indication on the front. You may not use any notes, HW, labs, other books, or calculators. his exam counts for 22% of your total grade. Read each question carefully and follow the instructions. You must pledge and sign this page in order for a grade to be assigned. he point values for problems may be changed at prof s discretion. Put your name at the top of this test page (and, if you remove the staple, all others). Be sure your exam consists of 11 distinct pages. Sign your name and add the date below. Good Evening! Welcome! Good luck & Go Gators!!! or each circuit design, equations must not be used as replacements for circuit elements. or each mixed-logic circuit diagram, label inputs of each gate with the appropriate logic equations Boolean expression answers must be in lexical order,( i.e., /A before A, A before B, & D 3 before D 2 ). Label the inputs and outputs of each circuit with activation-levels. or K-maps, label each grouping with the appropriate equation. PLEDGE: On my honor as a University of lorida student, I certify that I have neither given nor received any aid on this examination, nor I have seen anyone else do so. SIGN YOUR NAME DAE (10 Nov 2009) Regrade comments below: Give page # and problem # and reason for the petition. Page Available Points 2-3 1 10 5 10 6 12 7 12 8 8 9 1 10 12 11 8 OAL 100
15 min University of lorida EEL 3701 all 2009 Drs. E. M. Schwartz and A. A. Arroyo Page 2/11 [1%] 1. Design a system that counts the following sequence: 0,1,2,3,7,0 etc. he system must asynchronously reset to count 0 when Start (active-high) goes true. When the count is 3, the active-low output Z should be true. Use a JK- for the most significant bit of the counter, a - for the least significant bit, and a D- for any other bits you might need. min Note: All the given s have asynchronous clear and set inputs. a) Complete the next-state truth table. Add or remove columns if necessary. 5 min b) ind the required simplified equations.
Page 3/11 min 1. c) Design the complete counter circuit, minimizing the total number of components, but using the JK- and - [and D-(s), if necessary] as described above. All inputs and outputs of the circuit should be clearly indicated coming into or out of the below box. Your design must include the circuitry necessary to re-start the counter at count 0 asynchronously, when the Start(H) signal goes true. (2%) 1. d) Write the VHDL equation for the D- input (assuming you were using a CPLD for your controller). Just write the VHDL equation; you do not have to make a VHDL file. D
Page /11 [10%] 2. he following figure shows a block diagram design of a controller based on the ROM 10 min method and with D flip-flops. Assume that all inputs and outputs are active-high. he ROM contents are also given in the below table. (his problem is nearly identical to a problem in class homework 8 that was also done in class.) (9%) a) Derive the corresponding ASM chart. Show ALL work. (Do not miss part b below.) Contents of the ROM Addr Value Hex Hex 0 $19 1 $08 2 $0B 3 $06 $10 5 $10 6 $00 7 $00 (1%) b) If Y2 in part a is changed to active-low, describe all the changes in the ASM (if any) or redraw the ASM (with the changes).
Page 5/11 10 min [10%] 3. Answer the following questions about the ASM chart below. (0%) a. How many s are required: (1%) b. How many outputs are Moore? List them: (1%) c. How many outputs are Mealy? List them: (8%) d. Assign the state bits for this ASM as follows: P=0, N=1, M=2, Q=3, and R=. Complete the below next state truth table. Since this is a truth table, the only entries in the table should be 0 or 1 (or to represent any input value [wildcard] or X to represent a don t care output). ill out the next state truth table in order, i.e., the last row should begin with 1111 (with dashes replacing 1 s if possible). Q 2 Q 1 Q 0 X Q + 2 Q + + 1 Q 0 0 0 0 0 S W D B
Page 6/11 10 min [12%]. Draw a complete circuit diagram that implements the Koolio algorithmic state machine (ASM). his circuit diagram must include a J-K flip-flop for Q 1 and a flip-flop for Q 0 and a single EEPROM (of the smallest size possible). Specify the EEPROM size. You do not have to specify the EEPROM contents. he circuit should use no other components. Clearly label all signals, i.e., inputs, outputs and intermediate signals (including which ASM signals correspond to which address and data bits). An active-low asynchronous reset signal (Reset) should be included in the design. Everything else is active-high. SHOW ALL WORK! 00 0 Wait Recharge Call 1 Move Reset (asynchronous) 01 Go ind Bump 1 Backup 0 0 ound 1 11 Deliver Done 0 1 10 inished GoHome
Page 7/11 [12%] 5. Given two 2kx8 SRAM ICs and one kx8 ROM IC, design an 8kx8 memory module with 10 min kx8 SRAM and kx8 ROM. he SRAM address should start at address 0 and the ROM should immediately follow the RAM. he memory module should be safe to use by student programmers and must include a chip enable input. he 8kx8 memory module should have a R/~W input [R/~W=R(H)=W(L)], an 8-bit bi-directional data bus (D 7:0 ), the appropriate sized address bus (A?:0 ), and a chip enable (CE). Use any SSI gates you wish, but your solution must use a minimal number of components.
Page 8/11 [8%] 6. ill in the below (incomplete) voltage table based on the given (U-Beat South Carolina) 8 min circuit (with one NAND and one NOR gate). our copies are given for your possible use. I ll assume blanks left in the table indicate that the output has stabilized. U B SC B + SC + B ++ SC ++ B +++ SC +++ B ++++ SC ++++ L L L L L L L H L L H L L L H H L H L L L H L H L H H L L H H H H L L L H H L H
Page 9/11 [1%] 7. Complete the timing diagram for this ASM. Show small propagation delays. Assume that 10 min each of the flip-flops used are rising-edge triggered. his system has an asynchronous reset (Reset). Party Smile CLK Reset State Name? hirsty hirsty Reset Smile Drink Swim Bar S1 S2 Dry Drink Swim Swim hirsty Bar Leave
Page 10/11 [12%] 8. A block diagram of a system similar to your lab 6 is shown here. Note that registers A and B 8 min have been removed and register C has been added. Note also that MUX A and MUX B now have only two -bit wide inputs (instead of four). MSA/ Bus Selected as Input MSB to Combinatorial Logic 0 INPU Bus 1 REG C Bus MSA INPU Bus REGC Bus MUX A INPU Bus MUX B REGC Bus MSB MSC2:0 Action 000 A to REG C Bus 001 B to REG C Bus 010 complement of A to REG C Bus 011 A and B to REG C Bus 100 A minus B to REG C Bus 101 sum of A & B to REG C Bus 110 shift A left one bit to REG C Bus 111 shift A right one bit to REG C Bus Cin MSC2:0 3 CLK A Combinatorial Logic MUX C s REG C B REGC Bus Cout Complete the below table to execute the expression [ (5 plus 3) ] 1. If a signal does not matter (i.e., any value would be ok), use a dash ( ). ill out only the number of rows necessary. If this expression can not be implemented with the given architecture, write See NEX PAGE under the below table and describe why not on the BACK of the PREVIOUS page. Clock Cycle 0 1 2 3 5 6 7 8 Input Bus MSA MSB MSC2:0 Description (required for partial credit)
Page 11/11 [8%] 9. Complete the following problems about debouncing. (%) a) Draw a normal switch circuit (not a debounced switch circuit), with output X(H). Draw 3 min the switch in the true position. Draw a timing diagram of the bouncing that will occur on this non-debounced switch circuit as the switch goes from the true to false positions. H X(H) L (3%) b) Use one of the switches shown here and up to three NAND gates, min design a debounced switch circuit suitable for EEL-3701 lab use to produce debounced clock signal. (1%) c) Use one of the switches shown here and up to three NOR gates, 2 min design a debounced switch circuit suitable for EEL-3701 lab use to produce a debounced clock signal.