CS6C L5 Intro to SDS, State Elements I () inst.eecs.berkeley.edu/~cs6c CS6C : Machine Structures Lecture #5 Intro to Synchronous Digital Systems, State Elements I 28-7-6 Go BEARS~ Albert Chae, Instructor What are Machine Structures? Software Hardware Application (Netscape) Compiler Assembler Operating System (MacOS X) Processor Memory I/O system Datapath & Control Digital Design Circuit Design transistors 6C Instruction Set Architecture Coordination of many levels of abstraction ISA is an important abstraction level: contract between HW & SW CS6C L5 Intro to SDS, State Elements I (2) Below the Program High-level language program (in C) swap int v[], int k){ int temp; temp = v[k]; v[k] = v[k+]; v[k+] = temp; } Assembly language program (for MIPS) swap: sll $2, $5, 2 add $2, $4,$2 lw $5, ($2) lw $6, 4($2) sw $6, ($2) sw $5, 4($2) jr $3 Machine (object) code (for MIPS)... C compiler assembler 6C Levels of Representation High Level Language Program (e.g., C) Compiler Assembly Language Program (e.g.,mips) Assembler Machine Language Program (MIPS) Machine Interpretation Hardware Architecture Description (Logic, Logisim, etc.) Architecture Implementation Logic Circuit Description (Logisim, etc.) temp = v[k]; v[k] = v[k+]; v[k+] = temp; lw $t, ($2) lw $t, 4($2) sw $t, ($2) sw $t, 4($2) CS6C L5 Intro to SDS, State Elements I (3) CS6C L5 Intro to SDS, State Elements I (4) Synchronous Digital Systems Logic Design The hardware of a processor, such as the MIPS, is an example of a Synchronous Digital System Synchronous: Means all operations are coordinated by a central clock. - It keeps the heartbeat of the system! Digital: Mean all values are represented by discrete values Electrical signals are treated as s and s and grouped together to form words. CS6C L5 Intro to SDS, State Elements I (5) Next 4 weeks: we ll study how a modern processor is built; starting with basic elements as building blocks. Why study hardware design? Understand capabilities and limitations of hardware in general and processors in particular. What processors can do fast and what they can t do fast (avoid slow things if you want your code to run fast!) Background for more detailed hardware courses (CS 5, CS 52, EE 92) There is just so much you can do with processors. At some point you may need to design your own custom hardware. CS6C L5 Intro to SDS, State Elements I (6)
PowerPC Die Photograph Transistors Metal-Oxide-Semiconductor Field-Effect Transistor G Come in two types: - n-type NMOSFET p-type PMOSFET For n-type (p-type opposite) G S n-type If voltage not enough between G & S, transistor turns off (cut-off) and Drain-Source NOT connected If the G & S voltage is high enough, transistor turns on (saturation) and Drain-Source ARE connected Let s look closer S D MOSFET D p-type Side view www.wikipedia.org/wiki/mosfet CS6C L5 Intro to SD S, State Elements I (7) Chae, Summer 28 U CB Transistor Circuit Rep. vs. Block diagram CS6C L5 Intro to SD S, State Elements I (8) Chae, Summer 28 U CB Signals and Waveforms: Clocks Chips is composed of nothing but transistors and wires. Small groups of transistors form useful building blocks. (voltage source) a b c (ground) Block are organized in a hierarchy to build higher-level blocks: ex: adders. CS6C L5 Intro to SD S, State Elements I (9) Chae, Summer 28 U CB Signals and Waveforms CS6C L5 Intro to SD S, State Elements I () Signals When digital is only treated as or Is transmitted over wires continuously Transmission is effectively instant - Implies that any wire only contains value at a time CS6C L5 Intro to SD S, State Elements I () Chae, Summer 28 U CB Signals and Waveforms: Grouping Chae, Summer 28 U CB CS6C L5 Intro to SD S, State Elements I (2) Chae, Summer 28 U CB
CS6C L5 Intro to SDS, State Elements I (3) Signals and Waveforms: Circuit Delay Type of Circuits Synchronous Digital Systems are made up of two basic types of circuits: 2 3 4 5 3 4 5 6 5 7 9 Combinational Logic (CL) circuits Our previous adder circuit is an example. Output is a function of the inputs only. Similar to a pure function in mathematics, y = f(x). (No way to store information from one invocation to the next. No side effects) State Elements: circuits that store information. CS6C L5 Intro to SDS, State Elements I (4) Circuits with STATE (e.g., register) Peer Instruction A. SW can peek at HW (past ISA abstraction boundary) for optimizations B. SW can depend on particular HW implementation of ISA AB : FF : FT 2: TF 3: TT C. Timing diagrams serve as a critical debugging tool in the EE toolkit White is true C: T F CS6C L5 Intro to SDS, State Elements I (5) CS6C L5 Intro to SDS, State Elements I (6) Sample Debugging Waveform Administrivia Hw3 is due today Proj2 is due Friday Faux midterm today 6-9 Review session Thursday in lecture Extra MT OH? Midterm 7/2 7-p in 55 Dwinelle CS6C L5 Intro to SDS, State Elements I (7) CS6C L5 Intro to SDS, State Elements I (8)
CS6C L5 Intro to SDS, State Elements I (9) Uses for State Elements. As a place to store values for some indeterminate amount of time: Register files (like $-$3 on the MIPS) Memory (caches, and main memory) 2. Help control the flow of information between combinational logic blocks. State elements are used to hold up the movement of information at the inputs to combinational logic blocks and allow for orderly passage. Accumulator Example Why do we need to control the flow of information? Want: S=; for (i=;i<n;i++) S = S + X i Assume: Each X value is applied in succession, one per cycle. After n cycles the sum is present on S. CS6C L5 Intro to SDS, State Elements I (2) First try Does this work? Second try How about this? Feedback Nope! Reason # What is there to control the next iteration of the for loop? Reason #2 How do we say: S=? Rough timing Register is used to hold up the transfer of data to adder. CS6C L5 Intro to SDS, State Elements I (2) CS6C L5 Intro to SDS, State Elements I (22) Register Details What s inside? n instances of a Flip-Flop Flip-flop name because the output flips and flops between and, D is data, Q is output Also called d-type Flip-Flop What s the timing of a Flip-flop? (/2) Edge-triggered d-type flip-flop This one is positive edge-triggered On the rising edge of the clock, the input d is sampled and transferred to the output. At all other times, the input d is ignored. Example waveforms: CS6C L5 Intro to SDS, State Elements I (23) CS6C L5 Intro to SDS, State Elements I (24)
CS6C L5 Intro to SDS, State Elements I (25) What s the timing of a Flip-flop? (2/2) Edge-triggered d-type flip-flop This one is positive edge-triggered On the rising edge of the clock, the input d is sampled and transferred to the output. At all other times, the input d is ignored. Example waveforms (more detail): Accumulator Revisited (proper timing /2) Reset input to register is used to force it to all zeros (takes priority over D input). S i- holds the result of the i th - iteration. Analyze circuit timing starting at the output of the register. CS6C L5 Intro to SDS, State Elements I (26) Accumulator Revisited (proper timing 2/2) reset signal shown. Also, in practice X might not arrive to the adder at the same time as S i- S i temporarily is wrong, but register always captures correct value. In good circuits, instability never happens around rising edge of clk. Recap of Timing Terms Clock (CLK) - steady square wave that synchronizes system Setup Time - when the input must be stable before the rising edge of the CLK Hold Time - when the input must be stable after the rising edge of the CLK CLK-to-Q Delay - how long it takes the output to change, measured from the rising edge Flip-flop - one bit of state that samples every rising edge of the CLK Register - several bits of state that samples on rising edge of CLK or on LOAD CS6C L5 Intro to SDS, State Elements I (27) CS6C L5 Intro to SDS, State Elements I (28) Finite State Machines (FSM) Introduction You have seen FSMs in other classes. Same basic idea. The function can be represented with a state transition diagram. With combinational logic and registers, any FSM can be implemented in hardware. CS6C L5 Intro to SDS, State Elements I (29) Finite State Machine Example: 3 ones FSM to detect the occurrence of 3 consecutive s in the input. Draw the FSM Assume state transitions are controlled by the clock: on each clock cycle the machine checks the inputs and moves to a new state and produces a new output CS6C L5 Intro to SDS, State Elements I (3)
CS6C L5 Intro to SDS, State Elements I (3) Hardware Implementation of FSM Therefore a register is needed to hold the a representation of which state the machine is in. Use a unique bit pattern for each state. Combinational logic circuit is used to implement a function maps from present state and input to next state and output. + =? Hardware for FSM: Combinational Logic Next lecture we will discuss the detailed implementation, but for now can look at its functional specification, truth table form. CS6C L5 Intro to SDS, State Elements I (32) Truth table PS Input NS Output Peer Instruction A. HW feedback akin to SW recursion B. The minimum period of a usable synchronous circuit is at least the CLK-to-Q delay AB : FF : FT 2: TF 3: TT Peer Instruction A. It Answer needs base case (reg reset), way to step from i to i+ (use register + clock).true! B. If not, will loose data!true! C. How many states would it have? Say it s n. How does it know when n+ bits have been seen? False! C. You can build a FSM to signal when an equal number of s and s has appeared in the input. CS6C L5 Intro to SDS, State Elements I (33) White is true C: T F A. HW feedback akin to SW recursion A. HW feedback akin to SW recursion B. The minimum period of a usable B. We synchronous can implement circuit a is D-Q at flipflop least the as CLK-to-Q simple delay CL (And, Or, Not gates) C. You can build a FSM to signal when an equal number of s and s has appeared in the input. CS6C L5 Intro to SDS, State Elements I (34) ABC : FFF 2: FFT 3: FTF 4: FTT 5: TFF 6: TFT 7: TTF 8: TTT Conclusion ISA is very important abstraction layer Contract between HW and SW Clocks control pulse of our circuits Voltages are analog, quantized to / Circuit delays are fact of life Two types of circuits: Stateless Combinational Logic (&,,~) State circuits (e.g., registers) And In conclusion State elements are used to: Build memories Control the flow of information between other state elements and combinational logic D-flip-flops used to build registers Clocks tell us when D-flip-flops change Setup and Hold times important Finite State Machines extremely useful You ll see them again (5,52), 64, 72, 74, etc CS6C L5 Intro to SDS, State Elements I (35) CS6C L5 Intro to SDS, State Elements I (36)