How UV selectable illumination inspection tool and methodologies can accelerate learning curve of advanced technologies V. Twines, C. Archambuult, B. Hinschberger, E. Rouchouze ST Microelectronic Crolles 850 rue Jean Monner 38926 Crolles France {vinceni.turines, caroline.archambault, benoii. hinschberger, eric.rouchouze) @si.com S. Bos-Larenzo, 0. Moreuu KlA-Tencor France 32 ch. Du Vieux Ch&e 38240 Meylan France (Sandra. bos, olivier.moreau) @ kla-iencor. com Abstract As the microelectronic industry is simultaneously shrinking design rules to 0.13pm and below and integrating copper technology, new defectivity challenges appear. The requirements associated with these technology nodes include the efficient inspection of ever smaller features not only on known layers, but also in newer steps of the Cu damascene process, as well as the ability to characterize and monitor new lithography processes. In order to answer these needs, a brightfield UV inspection tool integrating advanced optical noise suppression and innovative image processing has been evaluated. This paper describes some recommendations for the capture of critical defects along with the inspection methodologies developed in order to characterize advanced technology modules. As an illustration, the defect detection strategies implemented on 3 different critical process steps (Shallow Trench Isolation (STIj Oxide Nitride removal, line litho after develop and Cu Chemical Mechanical Polishing (CMP)) are presented. In addition, a method qualifying the 193nm technology node process development is detailed, in which timeto-result was drastically decreased. Keywords UV wafer inspection tool, defect inspection methodologies, 193nm photolithography process, Cu damascene process 1. Introduction The transition to copper, low k dielectrics and small design rules is creating new challenges for semiconductor manufacturers. Defects that were non- critical for previous process technologies and design rules, are now becoming yield detractors. In addition, new processes in areas such as photolithography and CMP are leading to new defect type occurrences. An increasing need for wafer inspection tools that have the resolution, material contrast and noise suppression capabilities to capture these new killer defects has emerged. At the same time, the ability to deliver useful yield information in the shortest time scale is becoming more and more critical. The KLA-Tencor 2351 inspection tool provides a set of new hardware and software features to meet these technology challenges [1,2]. An evaluation has been performed on some of the most critical steps of advanced technologies (130nm and 90nm design rules) at ST Microelectronics Crolles, France, in order to determine the most appropriate inspection conditions. Four case studies (STl ON etch, line litho after develop, Cu CMP and a 193nm photo contact process monitoring) are presented hereafter. For each application, some recommendations for the capture of critical defects along with the Best Know Methods (BKMj developed in order to characterize these modules will be described. 2. Methodology Based upon the 21XX technology, the KLA- Tencor 2351 micro inspection tool features selectable W or visible illumination and 5 different pixel sizes to enable the resolution of pattern and defects for 130nm production and 90nm development applications. 2351 selectable band flexibility in a broad illumination spectrum (Broad Band (BB) W, Narrow Band (NBj W or Broad Band visible) 0-7803-7673-0/03/517.00 WO03 IEEE 225 2003 IEEHSEMI Advanced Manufacturing Conference
provides improved material contrast and resolution. Moreover the tool offers advanced additional optical modes (Edge Contrastm (EC) & Full Sky" (FS)) for improved sensitivity and defect capture on Front- End-Of-Line (FEOL) and Back-End-C)f-Line (BEOL) layers. Sophisticated image prwessing algorithms such as Wafer Inspection Sensitivity Enhancer (WISE), and the improved Auto-SAT (Segmented Auto Threshold) provide shorter lime to set-up and improved signal to noise ralio on challenging layers. Finally In-line Automated Defect Classification (iadc) gives accurate binning for faster analysis and real time defect classification during inspection thus reducing time to result [3]. Table 1 below is summarizing the improved 2351 hardware and software features. 2139-0.25um 2351-0.25pm EC Table 1: Hardware and software features provided hy the 2351 inspectian tool. Optid Resdution SignaVNoise enhancements COO enhancements FeatUl,es Pixel sizes 0.62pm, 0.39@m, 0.25pm, 0.20pm,O.ltjpm UV and visible illumination NB and BB spectrum in W I EC,FS I WISE, Auto-SAT ' I Increasedthroughput I iaix In order to maximize defect capturf! and determine the best inspection parameters to answer production needs, an evaluation has been petiormed across multiple critical steps of some advanced technologies (130nm and 90nm design rules) 011 logic type devices. The examples below have been si!lected because of gaps experienced with the current inspection capabilities. 3. Applications 3.1. STI Oxide Nitride removal (ON etch) Voids in STI might be a major yield detractors in the Front End of Line for advanced technology nodes. Some are due to particles landing on the wafer during Chemical Vapor Deposition (CVD) of the oxide in the trenches and then removed by the CMP process. They finally leave a small hole in the STI. These defects are known to generate leakage, yield or even reliability issues. However they can be difficult to detect with standard inspection tools due to their small size and low signal to noise ratio. Figure 1: Defect capture comparison between the 2139 and 2351 inspection tools run using the same pixel size. Use of EC mode enhances the sensitivity to defects of interest (DOI). CMF' p-scratch of the main defect types of 'I ON Etch The aim of 2351 trial on this layer was to improve in-line detection of these defects that have a low capture rate on the current 2139 inspection tools even with the most aggressive settings. Therefore, one wafer representative of the process was selected to perform a thorough comparison between an inspection at 0.25pm pixel size on 2139 and another one at 0.25pm visible EC on 2351. For comparison purposes a 0.25pm visible Brightfield (BF) inspection was set-up on 2351: it gave results similar to 2139 at twice the throughput. The wafer maps presented in Figure 1 highlights the difference in defect capture between the two 226 2003 IEEWSEMI Advanced Manufacturing Conference
inspections. The Normalized Defect Density (NDD) was calculated based on the manual defect classification of a random sample of defects performed on a Scanning Electron Microscope (SEMI review tool (SEM images of the main defect types are presented Figure 2). A clear gain in sensitivity is obtained for STI voids, CMF' micre scratches and extra active areas due to the use of EC mode rather than BF mode. Moreover, EC mode is less sensitive to previous layer defects and embedded particles, defects of less interest at that particular process step given that they would be detected at previous inspection steps in a typical Control Plan. Use case; STI pitting on pattern edges after ON Etch process step A new challenge was encountered during ON etch process tuning: pitting on the oxide layer was observed during manual SEM review, however, it was impossible to detect this problem on standard 2139 inspection tool or even with a 0.16pm W BF inspection on 2351. EC mode was instrumental for enhancing the detection of this critical defect due to improved contrast on pattern edges leading to a better S/N ratio. The resulting wafer map is presented Figure 3 along with SEM images of some of the defects (Figure 4). Using this new optical mode allowed not only to detect this pining problem, but also to visualize a wafer-level signature. This helped a lot for the identification of the defect root cause. Wafer center signature of pitting detected thanks to 0.25 pn Vis EC mode As a conclusion, relevant results were obtained in terms of detection of tiny voids in the oxide after STI ON Etch. Thanks to the EC mode, it has been possible to detect and track very small defects that until then were very difficult to capture on this specific level. On 2351, the 0.25pm pixel size using EC mode is the best production choice for killer defect capture at STI ON etch process step. In the production environment this is a key factor for reliable process control. 3.2.C~ CMP Copper CMF' level is a compulsory inspection step to identify BEOL yield detractors [4,5]. However this level can be impacted hy a lot of different defect types, sometimes with very high counts (Cu corrosion, scratches, surface particles). A lot of these defects are of low interest (either nuisance or defects of known origin). It is therefore mandatory to be able to focus on Defects Of Interest (DOI). In this respect, Wafer Inspection Sensitivity Enhancer (WISE) on 2351 has been evaluated. After an initial teaching phase, the WISE image-processing algorithm is able to identify a specific defect type based on its physical characteristics, and to filter it out at run time (Figure 5). The teaching phase is simply achieved with a manual classification of the corresponding defects hy the user at the time of initial recipe set-up. A worst-case scenario was selected specifically prepared wafers highly impacted by Cu voids were inspected. A 0.20pm BB UV inspection was used to minimize the effects of color variation and emphasize the capture of small defects at an acceptable throughput for a production line. Figure 3: The use of EC mode, combined with visible illumination, reveals a defect signature No nuisance fliter WISE nuisance filter Figure 5: Without WISE, the inspection has been aborted because a huge Cu voids density made it useless (left). With WISE, mostly DO1 are left, showing a clearer spatial signature (right). Figure 4: SEM pictures of pitting defects detected with EC mode only 221 2003 IEEWSEMI Advanced Manufacturing Conference
Figure 6: Defect Pareto of the wafer using WISE nuisance filter to reduce capture of Cu voids. Figure 6 represents the random defect distribution observed on the wafer after the inspection using WISE to filter out the void defect type. Though the main defect type is still Cu voids, other defects of high interest (deformed, missing or extra pattern, filling problems) are reported. Some of the main defect types are depicted in Figure 7. Deformed pattern Void 3.3.193nm lithography A critical milestone in the semiconductor industry is the introduction of 193nm photo resists. It is critical to ensure a smooth and fast implementation of this new material in order to meet the technology roadmap. Two case studies are presented hereafter to demonstrate the importance of both accelerating process integration and yield improvement with inline product wafer inspections, as well as monitoring process stability with short loop wafers. The selected inspection methodology is presented in both cases. Line After Develop Inspection (ADI) The ability to detect photolithography-related yield detractors before etching (such as resist poisoning and resist aging, or poor pattern resolution) is a success criteria in the achievement of challenging yield targets. The new narrow band W illumination available on the 2351 offers increased resolution along with enhanced sensitivity to current layer defects due to its small depth of focus (DOF). A comparison has been led between standard visible inspection conditions and UV Narrow Band illumination. Very convincing results were obtained: missing pattern defects were caught with W whereas they were not detected with visible mode on the 2351 tool. I] Corrosion CMP 11-scratch Figure 7: SEhl picture, of the main defect r.vpea reported after Cu CMP process step. Although the wafers were strongly impacted by defectivity caused by one main defect type, the: WISE feature enabled a more thorough defect analysis: some defects of high interest were highlighted with clearly visible wafer-level signatures. Figure 8: NDD comparison between defects captured with 0.20 NB UV BF and 0.39pm VIS BF inspections. As can be observed in Figure 8, UV Narrow Band mode allowed the capture of more current resist layer defects while king less sensitive to previous layer events. This is due to the combination of smaller DOF and enhanced optical resolution from UV illumination when compared to the previous generation visible spectrum. Being able to detect know killer defects is a must for any defect inspection strategy, but 228 2003 IEEWSEMI Advanced Manufacturing Conference
discovering new ones is key for yield improvement. Thanks to NB W mode, previously undetected killer defects that look lie missing vias (Figure 9) were captured during the evaluation. These defects might be due to local resist poisoning. Moreover, deformed vias, barely detectable with visible light, turned out to be numerous and located in a specific die region. Particle Scratch Stain Single missing / undersized contact Area of missing I undersized contact Deformed \,ia Figure 9: SEM pictures of nusrin: and ddormed via detected with W NB mode only The narrow band W illumination gave the best performances for after develop inspections. The 0.20pm pixel size associated with the resolution offered by the narrow band W light allowed the detection of killer defects. Figure 10: Optical images (patches) of the 5 iadc defect bins. Reliable automatic classification was achieved by training a classifier with various examples of each defect type. The performance of the classifier was then evaluated by its ability to match an expert manual classification: for the present study, both class accuracy and class purity were better than 80%. The contact lithography process was monitored periodically by inspecting PCMs over a period of several months (Figure 1 I). 193nm photo contact process monitoring The photo contact process step is identified as a yield-limiting step for the 90nm technology node, with an impact on yield that varies as a function of the density of missing or undersized contacts. In order to track these killer defects a Photo Cell Monitor (PCM) methodology was initiated. The PCM is a test wafer with patterned resist on silicon. It provides high signal-tcmoise ratio and allows early detection of problems that might not otherwise be identified before electrical testing on product wafers [61. A 0.20pm NB W inspection was set-up to allow the detection of low topography and very small defects such as stains, micro-bubbles, single, isolated missing or deformed contact. The in-line Automated Defect Classification (iadc) provided real time binning of defects into 5 classes enabling an easy implementation of excursion control by critical defect types. Figure 10 shows the distribution of the different defects into the iadc bins. Figure 11: Statistical Process Control (SPC) ch; showing how ial? can extract useful information by highlighting killer defect excursions. The total un-clustered defect density shows strong fluctuations, most of them are caused by non-killer defect twes. Setting a control limit on total defect density would therefore only result in false alarms or missed excursions. On the other hand, applying control limits to random missing or deformed contact 229 2003 IEEWSEMI Advanced Manufacturing Conference
defect density provides a more accurate 193nm photolithography process monitoring. By combining the detection capabilities of the narrow band W illumination mode with the power of iadc, the photo-cell monitoring technique offers a fast method for qualifying the 193nm technology node process development 4. Conclusion The studies performed on a few critical advanced process steps (STI ON etch, Cu CMP and line litho after develop) showed a strong capture rate improvement and revealed new defect types. Relevant methodologies and inspection modes on KLA-Tencor 2351 have been evaluated to ;acquire signiecant results in a short time range: extremely encouraging results were obtained with W illumination and EC mode for specific defect types that were previously hard to detect such ar oxide pitting and deformed vias after litho. In addition, the new WISE and iadc features allowed to fccus on defects of interest with a better wafer-level sijpature visibility. These promising results demonstrate the potentialities of this new inspection tool. For the applications evaluated in the study, the tool clearly fulells the needs of 130nm techno1og:y line monitoring as well as 90nm process development. It is well suited for the design rule shrink and can efficiently help in understanding defect mechanisms in newly intrduced processes. In this respect, it responded properly to the expectations of the evaluation. the SEMICON Europa Yield Management Solutions Seminar, April 2001 [3]. P.Y. Chiang, H.C. Chen, M. Lin The Applications of in-line Automatic Defect ClassiEcation (IADC) in a 300mm Foundry Proceedings of the SEMICON Taiwan Yield Management Solutions Seminar, August 2002 [4]. H. Chen at al Defect Reduction of Copper BEOL for Advanced ULSI Interconnect Proceedings of the IEEE 2001 Intemational, 2001, pp.21-23 [5]. S. Varadarajan, D. Kalakkad, T. Cacouris Understanding and Reducing Copper Defects Semiconductor Intemational, June 2002 [6]. I. Peterson, G. Thomson, T. Dibiase, S. Ashkenaz, R. Howland Pinto Reducing and Managing Yield Killers trough Photo Cell Monitoring Yield Management Solutions, V01.2, No 2, Spring 2000, pp.17-24 Acknowledgments The authors would like to thank FranGois Weisbuch, Pascal Bichebois of ST Microelectronics Crolles, France, Isabelle Soitout of Philips and RenC Ibloirin, Jean-Michel Vaca of KLA-Tencor for their contribution to this work. References [I]. M. Soucek, S. Trautman, J. Button, M. Reddy Utilization of the 2350 to minimize Risk to Process Qualification at TIDMOS6 Proceedings of the SEMICON West Yield Management Solutions Seminar, July 2001 [2]. Y.H. Kim Effect of W Inspection on Defect Management for Advanced Devices Proceedings of 230 2003 IEEWSEMI Advanced Manufacturing Conference