Nirma University Institute of Technology Electronics and Communication Engineering Department Course Policy B. Tech Semester - III Academic Year: 2017 Course Code & Name : Credit Details : L T P C 4 2 5 Course Co-ordinator : Prof. Ruchi Gajjar Contact No. & Email : Contact: 079-30642421 Email: ruchi.gajjar@nirmauni.ac.in Office : D-100 Faculty Room (1 st Floor) Course Faculty : 1. Prof. Ruchi Gajjar Visiting Hours: Wednesday 9:00 to 10:50 am 2. Prof. Hardik Joshi Email: hardik.joshi@nirmauni.ac.i n Contact No. 079-30642409 Office: D-207 Visiting Hours: Tuesday 2:00 to 4:00pm Odd Saturdays: 2:00 to 4:00 pm Odd Saturdays: 2:00 to 4:00 pm 3. Prof. Twinkle Bhavsar Email: twinkle.bhavsar@nirmau ni.ac.in Contact No. 079-30642422 Office: D-208 Visiting Hours: Friday 2:00 to 4:00 pm Odd Saturdays: 11:00 to 1:00 pm Course Blog : www.ec302tb@wordpress.com 4. Prof. Khyati Vachhani Email: khyati.vachhani@nirmauni. ac.in Contact No. 079-30642409 Office: D-206 Visiting Hours: Monday 1:15 to 2:00 pm Odd Saturdays: 2:00 to 4:00 pm 1. Introduction to Course 1.1 Importance of the course With the advancement of technology and increase in electronic devices, digital electronics is an essential element of digital ICs or micro controllers or computers or communication devices. Digital electronics serves as a backbone of all electronic gadgets and devices. The basic components which constitute the hardware of these devices are logic gates, flip flops, latches, ADCs, DACs, leading to combinational and sequential logic circuit design. This course teaches the Page 1 of 11
concepts of basic digital electronics required for understanding the functioning of various blocks inside a digital circuit. 1.2 Objective of the Course This course aims to provide the fundamentals of digital electronics and it will also emphasize on the design and analysis of different combinational and sequential digital circuit design. 1.3 Pre-requisite: Number systems like binary, decimal, octal and hexadecimal 2. Course Learning Outcomes (CLO)* CLOs are clear statements of the expectations for student achievements in the course. After successful completion of the course, a student will be able to 1. Apply the concepts of number base conversion and Boolean algebra for digital logic design. 2. Apply basic building blocks like logic gates and flip flops for digital logic circuit design. 3. Analyze and design basic combinational and sequential circuits. 4. Analyze the functioning of programmable logic, memories and data convertors. *Under-revision 3. Syllabus Number System: Decimal, Binary, Octal, Hexadecimal number system, Conversion of numbers from one number system to other, complement method of subtraction, 9 s and 10 s compliment method, 1 s and 2 s complement method, Floating point numbers. Binary Codes: Weighted and Non-weighted code, Self-complementing course, cyclic course, 8421 BCD code, XS-3 code, Gray code, Binary to Gray conversion, Gray to Binary conversion, Parity bit and its importance in error detecting. Logic Gates: AND, OR, NOR, NOT, NAND, X-OR, Inhibit circuits. Boolean Algebra: Axioms and laws of Boolean algebra, D morgans theorem, Duality, Reduction of Boolean expression, converting AND/OR/INVERT logic to NAND/NOR logic Simplification of Boolean expression using Karnaugh Map and Quine- Mcclusky Methods Expansion of a boolean expression to SOP and POS form, Minimization of POS and SOP expressions for 2 to 6 variables, Don t care conditions, Combinational logic, Quine- Mcclusky methods. Page 2 of 11
Combinational Circuits: The Half-adder, The Full-adder, The Half-subtractor, The Full Subtractor, Parallel Binary Adders, The Look-Ahead Carry Adder, IC Parallel Adders, Two s Complement Addition And Subtraction Using Parallel Adders, Serial Adders, BCD adder, Binary Multipliers, Code converters, Parity bit Generators/Checkers, Comparators, IC comparators, Decoders, BCD to 7-Segment Decoders, Display devices, Encoders, Keyboard Encoders, Priority Encoders, Multiplexers, Applications of Multiplexer, Demultiplexers Flip-Flops and Timing Circuits: S-R Flip-flop, JK Flip-flop, D Flip-flop, T Flip-flop, Edge Triggered Flip, flop, Master-slave Flip-flop, and Applications of Flip-flops. Shift Registers: Serial-in Serial-out Shift register, Serial-in Parallel-out Shift register, Parallel-in Serial-out Shift register, Parallel-in Parallel-out Shift register, Bi-directional shift register, Universal shift register, Dynamic shift register, Applications of shift registers. Counters: Asynchronous counter, Design of Asynchronous counter, Effect of Propagation Delay in Ripple counter, Decoding of Ripple counters, Integrated circuit Ripple counters, Synchronous counters, Design of Synchronous counter. MSI & LSI circuits and their Applications: Introduction, Examples of Useful Digital Circuits, Arithmetic Circuit, Comparators, Multiplexers, Code Converters, Wired Logic, Practical Aspects of Wired Logic and Bus Oriented Structures. Logic Families: Digital IC specification terminology, Logic families, TTL, Open collector gate, TTL subfamilies, IIL, ECL, MOS, CMOS, Dynamic MOS Logic Memories and Programmable Logic Devices: Memory types and terminology, Read Only memory, Semiconductor RAMs, Non-volatile RAMs, Sequential memories, Magnetic memories, Optical Disk memory, Charge coupled devices, Programmable Logic Devices PROM, PLA, PAL, CPLD, FPGA Analog To Digital And Digital To Analog Converters: Digital to Analog Conversion, R-2R ladder type DAC, Weighted resistor type DAC, Switched current source type DAC, Switched capacitor type DAC, Analog to Digital Conversion, Counter type A/D converter, Tracking type A/D converter, Flash-type A/D converter, Dual slope type A/D converter, Successive approximation type ADC. 3.1. Self-Study The self-study components of the syllabus will be declared at the commencement of the semester. Around 10% of the questions will be asked from self-study content. Topics/content for self-study are as listed below: 1. Review of different number system and their conversion 2. Magnetic memories, Optical Disk memory, Charge coupled devices Page 3 of 11
Students are expected to study above mentioned topics on their own. These topics will not be taught in the classroom. Students should refer to books available in the library for the same. 3.2. References 1. M. Morris Mano, Digital logic and computer Design, PHI 2. A. Anand Kumar, Fundamentals of Digital Circuits, PHI 3. R. P. Jain, Digital Electronics, TMH 4. B. Somanathan Nair, Digital Electronics and Logic Design, PHI 5. Thomas A. Demassa and Zack Ciccone, Digital Integrated Circuits, Wiley Publications 4. Laboratory details Laboratory experiments/ exercises should be completed as per the given schedule. It is expected that a student does the same with full understanding of the concept, procedure and application involved. Laboratory work will be based on above syllabus with following number experiments to be performed. Sr. No. Week No.# 1 2 2 3 3 4 4 5 5 7 6 8 7 9 List of Experiments Verification of basic logic gates and universal gates Schedule* Mapped CLO 17/7/17 21/7/17 2 Design and implement adders and subtractors using logic gates 24/7/17 28/7/17 1, 2, 3 Design and implement code converters using logic gates 31/7/17 4/8/17 1, 2, 3 Implement logic function using Multiplexer 7/8/17 11/8/17 1, 2, 3 Implement an encoder and decoder 21/8/17 25/8/17 1, 2, 3 Implement binary to seven segment display circuit 28/8/17 1/9/17 3 Verification of functionality of RS, D, JK and T flip flops 4/9/17 8/9/17 2, 3 8 10-11 Design and realize Modulo N Synchronous counter flip-flops. 11/9/17 15/9/17 25/9/17 28/9/17 1, 2, 3 Page 4 of 11
9 12 Design and implement shift registers. 2/10/17 6/10/17 2, 3 10 13-14 11 15 16 17 Logic Families: CMOS TTL (i) Interfacing of TTL and CMOS logic family (ii) Determine noise margin of TTL and CMOS logic family Design and implement a digital circuit based project * Schedule is based on academic calendar. 8/10/17 13/10/17 4 30/10/17 3/11/17 6/11/17 10/11/17 13/11/17 17/11/17 1, 2, 3 5. Innovative assignments details As a part of innovative assignment, students have to undertake a digital circiut design example or problem. The students should design any combinational or sequential circuit having a particular application by employing the concepts learned by them in this course. It is expected that the students formulate the design problem, identify the inputs and outputs required for that digital circuit, create a truth table for it, deduce a Boolean expression from it and finally design the logic diagram for the digital circuit. This could be implemented in hardware as a part of their project. Few sample topics (not limited to) are as under: Digital Counter Stop watch Traffic light system People counter Basic calculator Digital lock 6. Assessment Policy 6.1 Component wise Continuous Evaluation (CE), Laboratory and Project Work (LPW) & Semester End Examination (SEE) weightage Assessment scheme Component weightage Class Test 30% Sessional Exam 40% CE LPW SEE 0.4 0.2 0.4 Term Paper/ Innovative Assignment 30% Continuous Evaluation 75% Viva Voce 25% Page 5 of 11
6.2 Assessment Policy for Continuous Evaluation (CE) Assessment of Continuous Evaluation comprises of three components. 1. Class Test will be conducted as per academic calendar. It will be conducted online/ offline for the duration of 1 hour and will be of 30 marks. 2. Sessional Exam will be conducted as per academic calendar. It will be conducted offline for the duration of 1 hour and 15 minutes and will be of 40 marks. 6.3 Assessment Policy for Laboratory and Project Work (LPW) Assessment of Laboratory and Project Work comprises of two components. 1. Continuous assessment for laboratory experiments will be conducted. There will be 11 experiments, each carrying weightage of 10 marks. At the end of the course total marks obtained out of 110 will be converted according to weightage assigned. Assessment of Experiment will be carried out based on parameters like Completion of lab work file, understanding of the experiment performed, originality, involvement of the student, regularity, discipline etc. during the session. 2. A Viva voce examination for LPW component will be conducted as per academic calendar. It will carry a weightage of 25 marks. 6.4 Assessment Policy for Semester End Examination (SEE) A written examination of 3 hour duration will be conducted for the course as per academic calendar. It will carry 100 marks and marks obtained out of 100 will be converted as per weightage assigned. 7. Lesson Plan Session No. Topic Mapped CLO 1 Introduction to the course and course evaluation methods - 2 Number System: Decimal, Binary, Octal, Hexadecimal number 1 system 3 complement method of subtraction 1 4 9 s and 10 s compliment method 1 5 1 s and 2 s complement method, Floating point numbers 1 6 Binary Codes: Weighted and Non-weighted code, Selfcomplementing 1 code, Cyclic code 7 8421 BCD code, XS-3 code, Gray code, Binary to Gray conversion 1 8 Gray to Binary conversion, Parity bit and its importance in error detecting. 1 Page 6 of 11
9 Logic Gates: AND, OR, NOR, NOT, NAND, X-OR 2 10 Inhibit circuits. 2 11 Boolean Algebra: Axioms and laws of Boolean algebra 1 12 D morgans theorem, Duality, Reduction of boolean expression 1 13 Reduction of boolean expression 1 14 Converting AND/OR/INVERT logic to NAND/NOR logic 1 15 K-map and Minimization of POS and SOP expressions for 2 to 6 1 variables 16 K-map and Minimization of POS and SOP expressions for 2 to 6 1 variables 17 Don t care conditions, Combinational logic 1 18 Quine- Mcclusky methods. 1 19 Quine- Mcclusky methods. 1 20 Combinational Circuits: The Half-adder, The Full-adder 3 21 The Half-subtractor, The Full-Subtractor 3 22 Parallel Binary Adders, The Look-Ahead Carry Adder, IC Parallel 3 Adders 23 Two s Complement Addition And Subtraction Using Parallel 3 Adders, Serial Adders, BCD adder, Binary Multipliers 24 Code converters, Parity bit Generators/Checkers, Comparators, IC 3 comparators 25 Decoders, BCD to 7-Segment Decoders, Display devices 3 26 Encoders, Keyboard Encoders, Priority Encoders 3 27 Multiplexers 3 28 Applications of Multiplexer, Demultiplexers 3 29 Introduction to Sequential Circuits 2 Flip-Flops and Timing Circuits: S-R Flip-flop 30 JK Flip-flop 2 31 D Flip-flop, T Flip-flop 2 32 Edge Triggered Flip-flop, Master-slave Flip-flop 2 33 Applications of Flip-flops 2 34 Shift Registers: Serial-in Serial-out Shift register, Serial-in 3 Parallel-out Shift register 35 Parallel-in Serial-out Shift register, Bi-directional shift register, 3 Universal shift register 36 Dynamic shift register, Applications of shift registers. 3 37 Counters: Asynchronous counter 3 38 Design of Asynchronous counter, Effect of Propagation Delay in 3 Ripple counter 39 Decoding of Ripple counters, Integrated circuit Ripple counters 3 40 Synchronous counters 3 41 Design of Synchronous counter. 3 42 MSI & LSI circuits and their Applications: Introduction, 3 Examples of Useful Digital Circuits, Arithmetic Circuit 43 Comparators, Multiplexers, Code Converters 3 44 Wired Logic, Practical Aspects of Wired Logic and Bus Oriented Structures. 3 Page 7 of 11
45 Logic Families: Digital IC specification terminology, Logic 4 families 46 TTL, Open collector gate 4 47 TTL subfamilies, IIL 4 48 ECL, MOS 4 49 CMOS, Dynamic MOS Logic 4 50 Memories and Programmable Logic Devices: Memory types 4 and terminology, Read Only memory 51 Semiconductor RAMs, Non-volatile RAMs 4 52 Programmable Logic Devices PROM, PLA 4 53 PAL, CPLD 4 54 FPGA 4 55 Analog To Digital And Digital To Analog Converters: Digital to 4 Analog Conversion, R-2R ladder type DAC 56 Weighted resistor type DAC, Switched current source type DAC 4 57 Switched capacitor type DAC, Analog to Digital Conversion, 4 Counter type A/D converter 58 Tracking type A/D converter, Flash-type A/D converter 4 59 Dual slope type A/D converter, Successive approximation type 4 ADC. 60 Summarizing and doubt solving 4 8. Mapping of Session Learning Outcomes (SLO) with Course Learning Outcomes (CLO) Sessio n No. Session Learning Outcomes: After successful completion of the session, student will be able to Mapp ed CLO 1 Understand importance, scope and policy of the course - 2 Perform Number System based conversion 1 3 Apply complement method for subtraction 1 4 Apply 9 s and 10 s compliment method 1 5 Apply 1 s and 2 s complement method and perform Floating point 1 numbers arithmetic 6 Recognize and differentiate binary codes as Weighted and Nonweighted 1 code, Self-complementing code, Cyclic code 7 Interpret 8421 BCD code, XS-3 code, Gray code and perform Binary to 1 Gray conversion 8 Apply Gray to Binary conversion and recognize the importance of 1 Parity bit error detecting. 9 Identify the basic Logic Gates: AND, OR, NOR, NOT, NAND, X-OR 2 10 Interpret the logic behind Inhibit circuits 2 11 Identify Axioms and laws of Boolean algebra 1 12 Identify D morgans theorem and Duality 1 And apply Reduction of boolean expression 13 Apply reduction of boolean expression 1 14 Convert AND/OR/INVERT logic to NAND/NOR logic 1 Page 8 of 11
15 Apply K-map and Minimization of POS and SOP expressions for 2 to 6 1 variables 16 Apply K-map and Minimization of POS and SOP expressions for 2 to 6 1 variables 17 Apply Don t care conditions for Combinational logic 1 18 Apply Quine- Mcclusky methods for reduction 1 19 Apply Quine- Mcclusky methods for reduction 1 20 Design Combinational Circuits: The Half-adder, The Full-adder 3 21 Design Half-subtractor, The Full-Subtractor 3 22 Design Parallel Binary Adders, The Look-Ahead Carry Adder, IC Parallel 3 Adders 23 Design Two s Complement Addition And Subtraction Using Parallel 3 Adders, Serial Adders, BCD adder, Binary Multipliers 24 Design Code converters, Parity bit Generators/Checkers, Comparators, 3 IC comparators 25 Design Decoders, BCD to 7-Segment Decoders, Display devices 3 26 Design Encoders, Keyboard Encoders, Priority Encoders 3 27 Multiplexers 3 28 Identify applications of Multiplexer and design Demultiplexers 3 29 Identify flip-flops and Timing Circuits: S-R Flip-flop 2 30 Identify JK Flip-flop 2 31 Identify D Flip-flop, T Flip-flop 2 32 Analyze the functioning of Edge Triggered Flip-flop, Master-slave Flipflop 2 33 Apply Flip-flops for sequential logic design 2 34 Analyze Shift Registers: Serial-in Serial-out Shift register, Serial-in 3 Parallel-out Shift register 35 Analyze Parallel-in Serial-out Shift register, Bi-directional shift register, 3 Universal shift register 36 Analyze Dynamic shift register, Applications of shift registers. 3 37 Design Counters: Asynchronous counter 3 38 Design of Asynchronous counter, Effect of Propagation Delay in Ripple 3 counter 39 Design Ripple counters, Integrated circuit Ripple counters 3 40 Design Synchronous counters 3 41 Design of Synchronous counter. 3 42 Design MSI & LSI circuits and their Applications 3 43 Design Comparators, Multiplexers, Code Converters 3 44 Interpret Wired Logic, Practical Aspects of Wired Logic and Bus 3 Oriented Structures. 45 Interpret Logic Families: Digital IC specification terminology, Logic 4 families 46 Interpret the functioning of TTL, Open collector gate 4 47 Interpret the functioning of TTL subfamilies, IIL 4 48 Interpret the functioning of ECL, MOS 4 49 Interpret the functioning of CMOS, Dynamic MOS Logic 4 50 Interpret the functioning of Memories and Programmable Logic Devices: Memory types and terminology, Read Only memory 4 Page 9 of 11
51 Interpret the functioning of Semiconductor RAMs, Non-volatile RAMs 4 52 Analyze Programmable Logic Devices PROM, PLA 4 53 Analyze the functioning of PAL, CPLD 4 54 Analyze the functioning of FPGA 4 55 Interpret the working of Analog To Digital And Digital To Analog 4 Converters and Digital to Analog Conversion and working of R-2R ladder type DAC 56 Analyze the design of Weighted resistor type DAC, Switched current 4 source type DAC 57 Analyze the design of Switched capacitor type DAC, Analog to Digital 4 Conversion, Counter type A/D converter 58 Analyze the design of Tracking type A/D converter, Flash-type A/D 4 converter 59 Analyze the design of Dual slope type A/D converter, Successive 4 approximation type ADC. 60 Summarize topics covered in the course and express the linkages with other course/ s 9. Teaching-learning methodology 1. Lectures: Primarily Chalk and Black board will be used to conduct the course. However, where required, Power Point Presentations (PPTs), Video Lectures, Simulations / Animations etc. will be used to enhance the teaching-learning process. 2. Laboratory: Explanation of Experiment to be performed along with corelation with theory will be given. At the end of each session assessment will be carried out based on parameters like completion of lab work that includes observations, calculations, graphs and conclusions, individuality and involvement of the student, regularity, discipline etc. Students will be quizzed to check their understanding of the experiment/exercise conducted. 10. Active learning techniques Active learning is a method of learning in which students are actively or experientially involved in the learning process. Following active learning techniques will be adopted for the course. Make Them Guess: Introduce a new subject by asking an intriguing question, something that few will know the answer to (but should interest all of them). Accept blind guessing for a while before giving the answer to build curiosity. Muddiest Points: Ask students the most confusing point of the day at the end of the session Word of the Day: Select an important term and highlight it throughout the class Page 10 of 11
11. Course Material Following course material is uploaded on the course website: https://sites.google.com/a/nirmauni.ac.in//ec302-digital-circuits/ Course Policy Books / Reference Books / NPTEL video lectures Assignments, Lab Manuals Question bank Web-links, Blogs, Video Lectures, Journals Animations /Simulations, Softwares Advanced topics 12. Course Learning Outcome Attainment Following means will be used to assess attainment of course learning outcomes. Use of formal evaluation components of continuous evaluation, laboratory work, semester end examination Informal feedback during course conduction 13. Academic Integrity Statement Students are expected to carry out assigned work under Continuous Evaluation (CE) component and LPW component independently. Copying in any form is not acceptable and will invite strict disciplinary action. Evaluation of corresponding component will be affected proportionately in such cases. Turnitin software will be used to check plagiarism wherever applicable. Academic integrity is expected from students in all components of course assessment. Page 11 of 11