Zynq SoC / Analog Devices Software-Defined Radio Kit Simulink Demo

Transcription

1 Zynq SoC / Analog Devices Software-Defined Radio Kit Simulink Demo QPSK Digital Up/Down-Converter Demo for Zynq-7000/ Analog Devices Software-Defined Radio Kit using Model-Based Design with MathWorks and Simulink January 2013 Version 1.0 Copyright 2013 Avnet Inc. All rights reserved

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3 10. General. The terms and conditions set forth in the License Agreement or at will apply notwithstanding any conflicting, contrary or additional terms and conditions in any purchase order, sales acknowledgement confirmation or other document. If there is any conflict, the terms of this License Agreement will control. This License may not be assigned by Customer, by operation of law, merger or otherwise, without the prior written consent of Avnet and any attempted or purported assignment shall be void. Licensee understands that portions of the Licensed Materials may have been licensed to Avnet from third parties and that such third parties are intended beneficiaries of the provisions of this Agreement. In the event any of the provisions of this Agreement are for any reason determined to be void or unenforceable, the remaining provisions will remain in full effect. This constitutes the entire agreement between the parties with respect to the use of this Product, and supersedes all prior or contemporaneous understandings or agreements, written or oral, regarding such subject matter. No waiver or modification is effective unless agreed to in writing and signed by authorized representatives of both parties. The obligations, rights, terms and conditions shall be binding on the parties and their respective successors and assigns. The License Agreement is governed by and construed in accordance with the laws of the State of Arizona excluding any law or principle, which would apply the law of any other jurisdiction. The United Nations Convention for the International Sale of Goods shall not apply. Zynq-7000 SoC / Analog Devices SDR Kit Simulink Demo: 3

4 Simulink QPSK Digital Up/Down-Converter (DUC/DDC) Demo The Zynq-7000 SoC / Analog Devices SDR Kit base demonstration design provides a Linux-based framework for baseband and RF signal transmission and reception; a good starting point for integration of user-defined functionality for wireless communications. This demo uses model-based design techniques with MathWorks Simulink and Xilinx System Generator for system-level simulation of a QPSK symbol generator and digital up/down-converter signal chain, which will subsequently augment the base design of the SDR kit. A digital wireless transmitter will typically employ a digital up-converter (DUC) to interpolate the baseband symbols to a faster sampling rate to drive the DAC. Similarly, a receiver will employ a digital down-converter (DDC) to reduce the sampling rate from the ADC interface to baseband while respecting Nyquist for the incoming signal bandwidth. 1 This section demonstrates a QPSK generator and DUC/DDC with symbol timing recovery in Simulink. Figure 1 QPSK DUC/DDC with Symbol Timing Recovery 1 A practical introduction to multirate digital signal processing for wireless communications in Xilinx FPGAs can be found in application note XAPP1018 Zynq-7000 SoC / Analog Devices SDR Kit Simulink Demo: 4

5 Demo Requirements To complete the Zynq SoC / Analog Devices Software-Defined Radio Kit Simulink Demo, the following software and hardware setups are required. Software MathWorks MATLAB & Simulink R2012b DSP System Toolbox Signal Processing Toolbox MathWorks Free Trial Software mathworks.com/zynq-trial Xilinx ISE Design Suite 14.3 DSP Edition / or System Edition Free 30-day eval: Tera Term serial terminal program Avaliable on the SourceForge Japan page: Hardware Zynq SoC / Analog Devices Software-Defined Radio Kit HDMI display 1080P60 USB keyboard, mouse and hub Zynq-7000 SoC / Analog Devices SDR Kit Simulink Demo: 5

6 Downloading the Demo Files 1. Open a web browser to Avnet Design Resource Center 2. From the Support and Downloads tab, download the archive under Simulink Demo: Zynq-7000 SoC/Analog Devices Software-Defined Radio Kit 3. Extract the archive to a convenient directory. For the purposes of this demo, the C:\Zynq_SDR_Simulink_demo\ directory will be used. Once extracted, the directory structure should be: C:\Zynq_SDR_Simulink_demo\.\docs Zynq_SDR_Simulink_demo.pdf.\Simulink commtimrecresample_dsp_v23_baseband.slx.\sd_card.\fat32 boot.bin zimage devicetree.dtb Updates to factory-programmed 8 GB SD Card that ships with the Zynq SoC / Analog Devices SDR Kit Zynq-7000 SoC / Analog Devices SDR Kit Simulink Demo: 6

7 Section 1: QPSK DUC/DDC with Symbol Timing Recovery using Model- Based Design with MathWorks and Simulink 1. Launch MATLAB from Windows Start All Programs MATLAB R2012b 2. At the MATLAB command-line, change to the work directory by typing: cd C:\Zynq_SDR_Simulink_demo\Simulink or navigate with the Open menu item. Double click to open commtimrecresample_dsp_v23_baseband.slx. Figure 2 Setting MATLAB Work Directory and Opening the Model 3. Start simulation. Figure 3 Simulating the QPSK DUC/DDC with Symbol Timing Recovery Zynq-7000 SoC / Analog Devices SDR Kit Simulink Demo: 7

8 4. Allow the symbol timing recovery to lock, then stop simulation. The scatter plot displays paired I&Q symbol peaks as interpolated by the symbol timing recovery loop. The distance between the 4 (QPSK) point clusters and the extent to which each cluster is concentrated at the ideal constellation point is a measure of the quality of a digital receiver. Figure 4 - QPSK scatter plot Pulse-shaping filters are often distributed as a matched pair between transmitter and receiver. When the root-raised cosine response of the transmit-side pulse-shaping filter is convolved in the time domain with that of the receiver, the aggregate response is a raised cosine. 2 Figure 5 - Raised Cosine Response of Combined TX & RX Pulse-Shaping Filters 2 The composite response of linear systems in series, such as transmitter driving receiver, is the product of their transfer functions in the frequency domain. The term root raised cosine stands for the square-root of the raised cosine transfer function, or RC. Multiplying the RC transfer function of the transmit-side channel filter with that of the receiver yields a composite response 2 ( RC ) RC. Zynq-7000 SoC / Analog Devices SDR Kit Simulink Demo: 8

9 It is the raised cosine magnitude response that has the desirable quality of mitigating inter-symbol interference of PAM symbols in the time domain which would otherwise cause irreparable distortion, making it impossible for the symbol timing recovery loop at the receiver to achieve lock and retrieve the QPSK symbols. Figure 6 Pulse-Shaping Reduces ISI for Symbol Timing Recovery 5. At the MATLAB command line, display the impulse response of the aggregate transmitter - receiver matched pair of pulse-shaping filters: stem(conv(rrc_coef,rrc_coef)) 6. Observe the zero-crossings of the impulse response at 4 samples / symbol. It is this quality that reduces inter-symbol interference; an impulse into the system will produce a local maximum at the center-tap without affecting subsequent impulses. Figure 7 - Impulse response of matched pair of pulse-shaping filters Zynq-7000 SoC / Analog Devices SDR Kit Simulink Demo: 9

10 7. At the MATLAB command line, display the magnitude response of the aggregate transmitter - receiver matched pair of pulse-shaping filters: fvtool(conv(rrc_coef,rrc_coef),1) 8. Verify that the magnitude response in the spectrum scope at the DDC output matches the spectral mask specification: 80 db down from 20 MHz. Figure 8 - Magnitude response of matched pulse-shaping filters in simulation Figure 9 - Magnitude response of matched pulse-shaping filters / specifications We have demonstrated a QPSK symbol generator and digital up/down-converter signal chain using model-based design techniques with MathWorks Simulink and Xilinx System Generator for system-level simulation. In the next section we shall verify this functionality on the Zynq-7000 SoC / Analog Devices Software-Defined Radio Kit in stand-alone operation. Zynq-7000 SoC / Analog Devices SDR Kit Simulink Demo: 10

11 Section 2: Demo of DUC/DDC on Zynq-7000 SoC / Analog Devices SDR Kit The Zynq-7000 SoC / Analog Devices SDR Kit demonstration design provides a Linuxbased framework for baseband and RF signal transmission and reception. This section demonstrates the augmented base design with a QPSK symbol generator and digital up/down-converter signal chain from the Simulink model of the previous section. These functions have been pre-compiled into the proper format for non-volatile flash media to boot the SDR Kit and verify the DUC/DDC signal chain in stand-alone operation through a transmitter receiver loopback using the RF mod/de-mod of the AD-FMCOMMS1. 3 Figure 10 - Simulink DUC/DDC Integrated in Analog Devices SDR Demonstration Design 3 The symbol timing recovery block is not enabled in hardware for this demo. It is covered in Software- Defined Radio on Zynq AP SoC SpeedWay WorkShop Zynq-7000 SoC / Analog Devices SDR Kit Simulink Demo: 11

12 SD Card Update and Hardware Assembly Instructions: The Zynq-7000 SoC / Analog Devices SDR Kit ships with an SD card from the factory that enables the default base demonstration design. The present demo enables a modified version of the base design; this requires an update of the SD card contents. 9. Ensure ZedBoard is powered-down. Remove the SD card, insert it into the PC and wait for it to enumerate as a Windows drive. If prompted by Windows when inserting the SD card, select the Continue without scanning option. The Zynq BootROM is capable of interpreting the FAT32 file system for SD card boot mode. The SD card included with the SDR Kit is pre-loaded with the factory demo image for the board. It is advisable to preserve that for future use by copying the contents to a convenient folder on your PC hard drive before overwriting any of the files. 10. The QPSK generator and DUC/DDC have been integrated into the Analog Devices SDR demonstration design in Xilinx Platform Studio, compiled to bitstream and combined with 1 st & 2 nd stage bootloaders in the standard boot.bin. Copy boot.bin from the archive of this demo to the SD card, replacing the original factory version 4 : Figure 11 - Copying boot.bin to the SD card 4 Files zimage and devicetree.dtb need not be updated on the factory-programmed SD card Zynq-7000 SoC / Analog Devices SDR Kit Simulink Demo: 12

13 11. Remove the SD card from the PC and replace it into the SD card slot (J12) located on the underside of ZedBoard PCB. Ensure it is firmly in place. 12. Verify the ZedBoard boot mode (JP7-JP11) and MIO0 (JP6) jumpers are set to SD card mode as described in the Hardware Users Guide: Figure 12 ZedBoard Jumper Settings 13. IMPORTANT: Set the FMC IO voltage jumper JP18 to 2.5V. Otherwise, the AD FMCOMMS1-EBZ may be damaged. 14. Connect the USB-UART port of ZedBoard (J14) which is labeled UART to a PC using the MicroUSB cable. 15. Connect a micro USB dongle and USB hub to the USB-OTG connector. Ensure JP2 is closed (shorted) to enable 5V output to USB OTG connector. 16. Connect USB mouse, keyboard through a USB hub, and connect an HDMI display. Zynq-7000 SoC / Analog Devices SDR Kit Simulink Demo: 13

14 17. Insert AD FMCOMMS1-EBZ module into the FMC connector. Connect 2 SMA blade antennas. 18. Connect power supply to J Turn power switch (SW8) to the ON position. ZedBoard will power on and the Green Power Good LED (LD13) should illuminate. 20. The PC may pop-up a dialog box asking for driver installation. ZedBoard has a USB-UART bridge based on the Cypress CY7C64225 chipset. Use of this feature requires that a USB driver be installed on your Host PC. If Windows recognizes the USB-UART and loads the software driver, then amber LED D6 will light. Please skip ahead to the next section. However, if the host PC does not recognize the USB-UART and enumerate it as a COM port device refer to the USB-UART Setup Guide document in the link below for instructions on installing this driver. When driver installation is complete, continue to the next step. Zynq-7000 SoC / Analog Devices SDR Kit Simulink Demo: 14

15 21. After about 30 seconds from power-on, the blue Done LED (LD12) should illuminate indicating the bitstream has been downloaded to the Z7020. Use the Windows Device Manager to determine the COM Port. Figure 13 - Device Manager Showing Enumerated USB-UART as COM Open a serial terminal program on your PC. For this demo, Windows 7 was used which does not come with a built in terminal application such as HyperTerm. Tera Term was used in this example which can be downloaded from the Tera Term project on the SourceForge Japan page: Once Tera Term is installed, Tera Term can be accessed from the desktop or start menu shortcuts. 24. To configure baud rate settings, open the Serial Port Setup window from the Setup Serial port menu selection. Select the USB-UART COM port enumeration that matches the listing found in Device Manager. Also set the Baud rate option to , the Data width option to 8-bit, the Parity option to none, the Stop bit option to 1 bit, and the flow control to none. Finally, assign the transmit delay parameters to 10 msec/char and 100 msec/line, and then click OK. Zynq-7000 SoC / Analog Devices SDR Kit Simulink Demo: 15

16 Figure 14 - Tera Term Serial Port Setup Page 25. If the amber USB-Link Status (LD11) does not flicker during boot to indicate activity, check the driver installation to determine if the device driver is recognized and enumerated successfully and that there are no errors reported by Windows. 26. Power cycle the ZedBoard and monitor the Tera Term window. When the terminal output from U-Boot and a countdown is observed, allow the countdown to expire. Figure 15 ZedBoard U-Boot Booting Linux Zynq-7000 SoC / Analog Devices SDR Kit Simulink Demo: 16

17 27. When Linux has completed booting, you should see UBUNTU desktop In Network Scope, write value 0x00 to register 0x003 of the AD9122 to set the input data format of the DAC to 2's complement, as opposed to offset binary. Figure 16 Setting Input Data Format of the DAC to 2's Complement 5 ADC9643 contains programmable registers that control delays on its output data bus with pico-second resolution. Application software performs ADC auto-calibration by adjusting these delays such that ADC data arrives at the FPGA input pins with sufficient set-up and hold times relative to the edges of the ADC sampling clock. This ensures error-free ADC data capture into the FPGA at fast sampling rates. In the present application, AD9643will indicate failure of its pattern test in all but the first test. This is normal. At the time of this writing the Analog Devices IIO Scope application has not been updated to account for user modules in the signal chain if the ADC. Zynq-7000 SoC / Analog Devices SDR Kit Simulink Demo: 17

18 29. The ADI IIO Oscilloscope supports plotting of the captured data from AD- FMCOMMS1 in three different modes (time domain, frequency domain and constalation). The application also allows you to view and modify several settings of the AD-FMCOMMS1 RX and TX paths. From the RX Settings tab, set the decimation factor to 2 to account for the 2X decimation halfband filter in the receiver of the Simulink model from section 1. Figure 17 - Setting the Decimation Factor in IIO Scope Note: If the decimation factor option is absent under RX Settings, you may have a previous version of IIO Oscilloscope. To update to the latest version IIO Oscilloscope, open a terminal window from UBUNTU desktop and enter the following commands: > wget > tar -xjf osc.tar.bz2 > cd osc > make > sudo make install When prompted for a password, enter analog all lower case. Details on IIO Oscilloscope available at: Figure 18 Updating Analog Devices IIO Oscilloscope Zynq-7000 SoC / Analog Devices SDR Kit Simulink Demo: 18

19 30. In IIO Oscilloscope, select Frequency Domain and press capture. Observe the spectrum at the DDC output. Verify that the cut-off frequency and stop-band attenuation match the Simulink model as shown in Figure 8. Note that there may be RF noise in your local environment which was not modeled in the Simulink DUC/DDC model in section 1. Figure 19 - Spectrum at the DDC Output We have verified the integration of a QPSK DUC / DDC signal chain into the softwaredefined radio base demonstration design in stand-alone operation. To learn more about high-speed digital signal processing for wireless communications with Zynq SoC, attend Software-Defined Radio on Zynq AP SoC SpeedWay WorkShop. Details on next page. Revision History Date Version Revision Jan 27, Initial Release \ LL Zynq-7000 SoC / Analog Devices SDR Kit Simulink Demo: 19

20 Resources Avnet Design Resource Center Trial Software MATLAB, Simulink, and related products for Zynq mathworks.com/zynq-trial MathWorks DSP Design Package for Xilinx Kits AD-FMCOMMS1-EBZ HDL Reference Design AD-FMCOMMS1-EBZ Linux support ZedBoard Hardware User Guide Software-Defined Radio on Zynq AP SoC SpeedWay WorkShop This course combines the high-speed analog signal chain from RF to baseband with FPGA-based digital signal processing for wireless communications. Topics include high-speed analog signal chain, direct conversion radio architecture, high-speed data converter interface and FPGA-based digital signal processing for software defined radio. Attendees will work with the latest generation Analog Devices high-speed data converters, RF and clocking devices, along with the Xilinx Zynq-7000 SoC. Hands-on labs featuring Xilinx DSP design tools and IP, including MathWorks Simulink model-based design, will introduce attendees to system-level concepts that are both powerful and intuitive. Register through Zynq SpeedWay web page Zynq-7000 SoC / Analog Devices SDR Kit Simulink Demo: 20