FGD0801. FGD0801 Datasheet. Page 1 of 124. Datasheet

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2 . General Description The is a K-color, single-chip LCD driver for the TFT panel with RGB x 0 dots at maximum, which contains a gate driver, a source driver, power supply, timing controller circuit and internal RAM for graphics data of RGB x 0 dots at maximum. The supports five interfaces: 0-system -/-/-/-bit bus interface, -system -/-/-/-bit bus interface, serial data transfer interface, VSYNC interface (system interface + VSYNC) and RGB -/-/-bit bus interface (DOTCLOCK, VSYNC, HSYNC, ENABLE, -0). In RGB -/-/-bit bus interface and VSYNC interface mode, using window address function to display moving picture and still picture simultaneously can reduce the power consumption. The can be operated in low-voltage (.V) condition to the interface and integrated internal boosters that produce the liquid crystal voltage, breeder resistance and the voltage follower circuit for liquid crystal driver. The also supports various functions to reduce power consumption, such as -color display mode, sleep mode and standby mode. The A is suitable for any small portable battery-driven product and requiring long-term driving capabilities, such as digital cellular phones, small PDAs and bi-directional pagers.. Features Single chip solution to drive a TFT panel Internal operation circuit of liquid crystal display: Source channel: Gate line: 0 Internal graphics RAM capacity:,00 bytes RGB x 0 dots graphics display LCD controller/driver and K colors The K colors can be displayed at the same time with gamma correction Support interface: 0-system interface (-/-/-/-bit bus) -system interface (-/-/-/-bit bus) Serial data transfer interface VSYNC data transfer interface RGB interface (-/-/-bit bus) Low-power consumption architecture supports: VCI =. ~. V (internal analog power supply) VCC =. ~. V (internal digital power supply) IOVCC =. ~. V (internal I/O power supply) VLCD =.~.V (internal driving power supply) VDDD =.V (internal logic power supply) Power-saving functions -color mode Standby mode Sleep mode To write data in a window-ram address area by using a window-address function N-line inversion AC liquid-crystal drive Partial liquid crystal drive to display two screens at arbitrary positions Vertical scrolling function Internal oscillator and hardware reset function Page of

3 . Device Description. Block Diagram S~ IOVCC GND IM- IM0/ID Index Register (IR) Control Register (CR) Source driver NCS RS E_NWR RW_N SDI SDO SCL /PD~0 VSYNC DOTCLK NRESET TS~0 System_IF - -bit - -bit - -bit - -bit -Serial RGB-IF - -bit - -bit - -bit VSYNC_IF Read data latch Address Counter (AC) Write data latch M/AC circuit Latch circuit Grayscale voltage generator V0~ VGS VTESTOUT VCC Power regulator VDDD Graphic RAM,00bytes Gamma adjusting circuit OSC OSC RCOSC Timing generator Gate Driver G~0 VSSD VSSA LCD driving power circuit VGH/VGL VCI VGAMOUT VCI CA/CB VLCDC VLCD CA/CB VCLC VCL C~A C~B VGHC VGH VGLC VGL VCOMR VCOMH VCOML VCOM VCOMHI VCOMLI VMON Figure Block Diagram Page of

4 . Pin Description Table Pin description Input Parts Signals I/O Pin Number Connected with Descriptions Select the MPU interface mode as listed below IM0(ID) IM IM IM MPU interface mode pins bit interface, -system -, bit interface, -system bit interface, 0-system -, bit interface, 0-system - IM-0 I VSSD/IOVCC ID 0 0 Serial data transfer interface -0 * 0 Setting invalid bit interface, -system bit interface,-system bit interface, 0-system bit interface,0-system - * * Setting invalid - Note: if the serial data transfer interface was selected, IM0 pin is used like the ID setting for the device code in transfer data. NCS I MPU RS I MPU E_NWR I MPU RW_N I MPU Chip select signal. Low: chip can be accessed; High: chip cannot be accessed. Must be connected to VSSD if not in use. The signal for register index or register command select. Low: Register index or internal status (in read operation); High: Register command. Connect to IOVCC or VSSD level when serial data transfer interface is selected. In 0-system bus interface mode, serves as a write strobe signal. Write data at the low level. In -system Interface mode, serves as an ENABLE signal to control data read/write operation. Serves as a read signal and reads data at the low level in 0-system interface. Fix it to IOVCC or VSSD level when using serial data transfer interface. A data ENABLE signal in RGB I/F mode. Fix the unused pin to either the VSSD level or the IOVCC level. Low: Selected (access enabled) The polarity of the ENABLE signal is inverted by the EPL bit. ENABLE I MPU EPL ENABLE RAM write RAM address 0 0 Enable Update 0 Disable Keep 0 Disable Keep Enable Update Page of

5 Input Parts Signals I/O Pin Number Connected with Descriptions SDI I MPU Serial data transfer input in serial data transfer interface mode.data would be latched on the rising edge of the SCL signal. Fixed to either IOVCC or VSSD if not in use. SCL I MPU VSYNC I MPU HSYNC I MPU DOTCLK I MPU NRESET I VCOMR I VLCD I VGH I VGL I VCL I MPU or reset circuit Variable Resistor or open Stabilizing capacitor VLCDC Stabilizing capacitor Stabilizing capacitor Stabilizing capacitor A synchronizing clock signal in serial data transfer interface mode. Fixed to either IOVCC or VSSD if not in use. Frame synchronizing signal. The polarity of the VSYNC signal is selected by VSPL bit. Fix to the IOVCC level when not used. If VSPL=0: Start in the low level. If VSPL=: Start in the high level. Line synchronizing signal. The polarity of the HSYNC signal is selected by HSPL bit. Fix to the IOVCC level when not used. If HSPL=0: Start in the low level. If HSPL=: Start in the high level. Dot clock signal. Fix to the IOVCC level when not used. If DPL=0: Data are input on the falling edge of DOTCLK. If DPL=: Data are input on the rising edge of DOTCLK. Reset pin. Setting either pin low initializes the LSI. Must be reset after power is supplied. A VCOMH reference voltage. When adjusting VCOMH externally, set registers to halt the VCOMH internal adjusting circuit and place a variable resistor between VGAMOUT and VSSD. Otherwise, leave this pin open and adjust VCOMH by setting the internal register of the. A power supply for the source driver outputs. A reference voltage for step-up circuit. A power supply for the TFT LCD's gate driver. Connect to Stabilizing capacitor. Max VGH =.V A power supply for the TFT LCD's gate driver. Connect to Stabilizing capacitor. Min VGH = -.V A power supply for the VCOML level. Connect to Stabilizing capacitor. VCL=0~-.V TEST I VSSD A test pin. Make sure to fix it to the VSSD level. TEST I VSSD A test pin. Make sure to fix it to the VSSD level. VGS I VSSD or external resistor Connect to a variable resistor to adjusting internal gamma reference voltage for matching the characteristic of different panel use. VCI I Power supply For analog power supply. Connect to an external power supply.v~.v. VCILVL I Power supply Generates a reference voltage (VCIOUT, REGP) from the VCILVL level according to the ratio determined by the VC-0 bits. Connect to VCI on the FPC. VCC - Power supply A power supply for the internal logic. VCC =. ~.V IOVCC - Power supply Power supply for interface pin. IOVCC =. ~. V. Connect to VCC on the FPC, if IOVCC = VCC for preventing noise when using the COG method. VSSD - Power supply Ground for the logic side. VSSD = 0V VSSA - Power supply Analog ground. VSSA = 0V. When using the COG method, connect to VSSD on the FPC to prevent noise. Page of

6 Output Part Signals I/O Pin Number Connected with Description Serial data transfer output in serial data transfer interface mode. SDO O MPU Data would be output on the falling edge of the SCL signal. When SDO is not used, leave it open. Output voltages applied to the liquid crystal. The shift direction of segment signal outputs is changeable with the SS bit. For example, if SS=0, data in the S- O LCD RAM address"0000"is output from S. If SS=,the same data in the RAM address"0000" is output from S. S, S, S,... display red (R), S, S, S,... display green (G), S, S, S,... display blue (B) (SS = 0,BGR = 0). G-0 O 0 LCD Output signals from gate lines. VGH: the level to select the gate lines. VGL: the level not to select the gate lines. VCOM O VCOMH O VCOML O TFT common electrode Stabilizing capacitor Stabilizing capacitor or open FLM O MPU or open VLCDC O VLCD The power supply of common voltage in TFT driving. The voltage amplitude between VCOMH and VCOML is output. The alternation cycle can be set by the POL pin. Connect this pin to the common electrode in TFT panel. Connect this pin to the capacitor for stabilization. This pin indicates a high level of VCOM amplitude generated in driving the VCOM alternation. When the VCOM alternation is driven, this pin indicates a low level of VCOM amplitude. Connect this pin to a capacitor for stabilization. When the VCOMG bit is low, the VCOML output stops and a capacitor for stabilization is not needed. A frame head pulse (amplitude: IOVCC-VSSD). Use when writing data to RAM in synchronization with FLM. When FLM is not used, disconnect it. A power supply for the source driver outputs. A reference voltage for the step-up circuit. Connect to VLCD. VGHC O VGH A power supply for the TFT-LCD s gate driver. Connect to VGH. VGLC O VGL A power supply for the TFT-LCD s gate driver. Connect to VGL. VCLC O VCL TS0- O Open Test pins. Disconnect them. An output from the step-up circuit of - time the VCI level. VCLC= 0 ~.V VMON O Open A test pin. Disconnect it. IOVCCDUM O Input pin Internal IOVCC level outputs. When adjacent input pins are fixed to the IOVCC level, short-circuit them. IOGNDDUM~ O Input pin Internal VSSD level outputs. When neighboring input pins are fixed to the VSSD level, short-circuit them. VTESTOUT O - A test pin. Disconnect it. TVCOMHI O Stabilizing capacitor TVCOMLI I/O Open A test pin. Disconnect it. TVMAG O Stabilizing capacitor A reference voltage for VCOMH. Must be connected with the capacitor 0.uF. A reference voltage for VCOML. Must be connected with the capacitor 0.uF. VDDD O Stabilizing capacitor A stabilizing capacitor for logic power. Connect with the capacitor uf. Page of

7 Input/output Parts Signals I/O Pin Number Connected with Descriptions CA,CB I/O Step-up Capacitor Connect to the step-up capacitors according to the step-up factor. Leave this pin open if the internal step-up circuit is not used. CA,CB CA,CB CA,CB I/O Step-up Capacitor OSC,OSC I/O Oscillation Register Connect these pins to the capacitors for the step-up circuit, according to the step-up rate. When not using the step-up circuit, disconnect them. Connect an external resistor for generating internal clock by internal R-C oscillation. Or an external clock signal is supplied through OSC with OSC open. ~0 I/O MPU It is used liked an -bit bi-directional data bus. -bit bus: use - -bit bus: use - -bit bus: use - and - -bit bus: use -0 Connected unused pins to the IOVCC or VSSD level. REGP I/O Open A test pin for VGAMOUT. Disconnect it. VGAMOUT I/O Stabilizing Capacitor or power supply A reference voltage for VGAM between VSSD and VGL from the reference voltage between VCI and VSSD that is generated internally. VGAMOUT serves as a source driver grayscale reference voltage, and a VCOM amplitude reference voltage. Connect to a stabilizing capacitor. VGAMOUT=.0 (VLCDC-0.)V VCIOUT O Stabilizing capacitor TESTO, - Open Dummy pads. Disconnect them. An reference voltage for the step-up circuit. Connect to an external power supply of.v of less when not using an internal reference voltage. DUMMY - - Open Dummy pads. Disconnect them. DUMMYR- - Open Dummy pads. Disconnect them. Page of

8 . Interface The supports system interface for setting instructions/data and RGB interface for data transferring during animated display. The can select the appropriate interface for the display (moving or still picture) in order to transfer data efficiently or improve the display quality. As external display interface, the supports RGB interface and VSYNC interface, which enables data rewrite operation without flicker when displaying the animated pictures on the panel.. System interface The following kinds of system interface are available with the and the interface is selected by setting the IM-0 pins. The system interface is used for instruction setting and RAM access. The supports three system interfaces: an 0-System -/-/-/-bit bus interface, a -System -/-/-/-bit bus interface and a serial data transfer bus interface. The includes an index register (IR) storing index data of internal control register and RAM. There are two -bit bus control registers used to temporarily store the data written to or read from the GRAM. The IR will be indexed to these two control registers through data bus by setting RS=. When the data is written into the GRAM from the MPU, it is first written into the write data latch and then automatically written into the GRAM by internal operation. Data is read through the read-data latch when reading from the GRAM. Therefore, the first read data operation is invalid and the following read data operations are valid. Operations E_NWR RW_N RW RS Write Indexes into IR Read Internal Status 0 0 Write Data into Control Register or GRAM 0 0 Read Control Register or GRAM data 0 Table Register Selection (0/ system:-/-/-/-bit System Interface) Operations R/W RS Write Indexes into IR 0 0 Read Internal Status 0 Write Data into Control Register or GRAM 0 Read Control Register or GRAM data Table Register Selection (Serial Data Transfer Interface) Page of

9 .. 0/-System Interface ) system -bit bus Interface The 0-System -bit parallel data transfer can be used by setting IM-0 pins to. And the -system -bit parallel data transfer can be used by setting IM-0 pins to 00.The Figure is the example of interface with i0/m Microcomputer and the Figure is the data format of -bit system interface. MPU CSn A # WR# D-0 NCS RS WR_N E_NWR -0 Figure 0/-System -bit bus Interface Instruction Input 0 Instruction 0 Instruction code Input 0 Writer data register 0 GRAM R R R R R R0 G G G G G G0 B B B B B B0, colors are avaliable Figure Instruction /GRAM Data Write (-bit System Interface) Page of

10 ) system -bit bus Interface The 0-system -bit bus parallel data transfer can be used by setting IM-0 pins to 00. And the -system -bit bus parallel data transfer can be used by setting IM-0 pins to 0000.The data written to GRAM is expanded to -bit bus data automatically in the LSI. Unused pins (, 0) must be fixed to the IOVCC or VSSD level. MPU CSn A # NCS RS WR_N WR# E_NWR D-0 -,-,0 Figure 0/-System -bit Bus Interface Instruction Input Instruction Instruction code RAM data write ( transfers/pixel) TRI=0,DFM-0=00 Input.. Writer data register 0 GRAM R R RR R R R0 G G G G G G0 B B B B B B0, colors are avaliable Figure Instruction /GRAM Data Write (-bit System Interface) Page of

11 ) system -bit bus Interface The 0-system -bit bus parallel data transfer can be used by setting IM-0 pins to. And the -system -bit bus parallel data transfer can be used by setting IM-0 pins to 0.In 0/-system -bit bus parallel data transfer mode, the -bit bus instruction and GRAM write data are divided into lower and upper nine bits, and then the upper nine bits are transferred first. Unused pins (-0) must be fixed to the IOVCC or VSSD level. CSn A NCS RS MPU # WR_N WR# E_NWR D Figure 0/-System -bit Bus Interface Instruction Input st Transfer nd Transfer Instruction 0 Instruction code st Transfer nd Transfer Input Writer data register 0 GRAM R R R R R R0 G G G G G G0 B B B B B B0, colors are avaliable Figure Instruction /GRAM Data Write (-bit System Interface) Page of

12 ) system -bit bus Interface The 0-system -bit bus parallel data transfer can be used by setting IM-0 pins to 00. And the -system -bit bus parallel data transfer can be used by setting IM-0 pins to 000.The data format is same as -bit interface, Unused pins (-0) must be fixed to the IOVCC or VSSD level. CSn A NCS RS MPU # WR_N WR# E_NWR D Figure 0/-System -bit Bus Interface Instruction Input Instruction 0 Instruction code RAM data write( nd transfers/pixel) TRI=0,DFM-0=00 st Transfer nd Transfer Input.. Write Data Register 0 GRAM R R R R R R0 G G G G G G0 B B B B B B0, colors are avaliable Figure Instruction /GRAM Data Write (-bit System Interface) Page of

13 Write to the Graphic RAM NCS RS RW_N E_NWR -0 00h write to Index register Display data write to RAM Display data write to RAM nth pixel, Address=N (n+)th pixel, Address=N + Read the Graphic RAM NCS RS RW_N E_NWR h dummy read data st read data nth pixel, Address=N (n+)th pixel, Address=N + Write to the Register NCS RS RW_N E_NWR -0 index write to Index register command write to the register Read the Register NCS RS RW_N E_NWR -0 index write to Index register command read from the register Figure /-bit System Interface Timing (for i0 series MPU ) Page of

14 Write to the Graphic RAM NCS RS RW_N E_NWR - or - Read the Graphic RAM NCS 00 h h st write data nd write data st write data nd write data st write data { nth pixel, Address=N { (n+)th pixel, Address=N + nd write data { (n+)th pixel, Address=N + RS RW_N E_NWR - or - 00 h h st read data nd read data { { dummy read data nth pixel, Address=N Write to the Register NCS RS RW_N E_NWR - or - Read the Register 00 h index st write data nd read data { Index { command write NCS RS RW_N E_NWR - or - 00 h { Index index st read data nd read data { command read Figure /-bit System Interface Timing (for i0 series MPU ) Page of

15 Write to the display data RAM NCS RS RW_N E_NWR - st transfer data nd transfer data rd transfer data st transfer data nd transfer data rd transfer data nth pixel, Address=N (n+)th pixel, Address=N + Write to the display data RAM NCS RS RW_N E_NWR - upper -bit data lower -bit data upper -bit data lower -bit data upper -bit data lower -bit data nth pixel, Address=N (n+)th pixel, Address=N + (n+)th pixel, Address=N + Read the display data RAM NCS RS RW_N E_NWR - dummy data st read data nd read data rd read data st read data nd read data rd read data nth pixel (n+)th pixel Read the display data RAM NCS RS RW_N E_NWR - dummy data upper -bit data lower -bit data upper -bit data lower -bit data upper -bit data lower -bit data nth pixel (n+)th pixel (n+)th pixel Figure -bit System Interface Timing (for i0 series MPU ) Page of

16 Write to the Graphic RAM NCS RS RW_N E_NWR -0 00h write to Index register Display data write to RAM Display data write to RAM nth pixel, Address=N (n+)th pixel, Address=N + Read the Graphic RAM NCS RS RW_N E_NWR h dummy read data st read data nth pixel, Address=N (n+)th pixel, Address=N + Write to the Register NCS RS RW_N E_NWR -0 index write to Index register command write to the register Read the Register NCS RS RW_N E_NWR -0 index write to Index register command read to the register Figure /-bit System Interface Timing (for m series MPU ) Page of

17 Write to the Graphic RAM NCS RS RW_N E_NWR - or - Read the Graphic RAM NCS 00 h h st write data nd write data st write data nd write data st write data { nth pixel, Address=N { (n+)th pixel, Address=N + nd write data (n+)th pixel, { Address=N + RS RW_N E_NWR - or - 00 h h st read data nd read data { { dummy read data nth pixel, Address=N Write to the Register NCS RS RW_N E_NWR - or - Read the Register 00 h index st write data nd write data { Index { command write NCS RS RW_N E_NWR - or - 00 h { Index index st read data nd read data { command read Figure /-bit System Interface Timing (for m series MPU ) Page of

18 Write to the display data RAM NCS RS RW_N E_NWR - st transfer data nd transfer data rd transfer data st transfer data nd transfer data rd transfer data nth pixel, Address=N (n+)th pixel, Address=N + Write to the display data RAM NCS RS RW_N E_NWR - upper -bit data lower -bit data upper -bit data lower -bit data upper -bit data lower -bit data nth pixel, Address=N (n+)th pixel, Address=N + (n+)th pixel, Address=N + Read the display data RAM NCS RS RW_N E_NWR - dummy data st read data nd read data rd read data st read data nd read data rd read data nth pixel (n+)th pixel Read the display data RAM NCS RS RW_N E_NWR - dummy data upper -bit data lower -bit data upper -bit data lower -bit data upper -bit data lower -bit data nth pixel (n+)th pixel (n+)th pixel Figure -bit System Interface Timing (for m series MPU ) Page of

19 .. Serial Data Transfer Interface The supports the serial data transfer interface by setting IM- pins to 0. The data is transferred via chip select line (NCS), serial transfer clock line (SCL), serial data input line (SDI), and serial data output line (SDO). In serial interface operation, the IM0/ID pin functions as the ID pin, and the -0 pins, not used in this mode, must be fixed to either IOVCC or VSSD level. The recognizes the start of data transfer on the falling edge of NCS input and starts transferring the start byte. It recognizes the end of data transfer on the rising edge of NCS input. The is selected when the -bit chip address in the start byte transferred from the transmission unit and the -bit device identification code assigned to the are compared and both -bit data match. Then, the starts taking in subsequent data. The least significant bit of the device identification code is determined by setting the ID pin. Send "0 to the five upper bits of the device identification code. Two different chip addresses must be assigned to the because the seventh bit of the start byte is register select bit (RS). When RS = 0, either index register write or status read operation is executed. When RS =, either instruction write operation or RAM read/write operation is executed. The eighth bit of the start byte is R/W bit, which selects either read or write operation. The receives data when the R/W = 0, and transfers data when the R/W =. Transmitting Order Start Byte 0 0 ID RS RW Start Byte Format of Serial Interface Figure Start Byte Format of Serial Interface When the serial data transfer interface is enabled, the starts taking in start byte and subsequent data that is transferred with the MSB first. Further, the registers of -bit bus format can be dividing to the upper eight bits as the first byte and lower eight bits as second byte when are executed from the MSB after transferring two bytes. The executed the write data operation to the GRAM after two-byte and then automatically expanded to the -bit bus format. When the read status/register operation is executed, the prior byte after start byte is invalid, and then the starts to read correct status/register data from second byte. As well as, when the read GRAM data operation, the prior five bytes of GRAM read data after the start byte are invalid. The starts to read correct GRAM data from the sixth byte. RS R/W Function 0 0 Index Register Set 0 Status Read 0 Register or GRAM Data Write Register or GRAM Data Read Table RS and R/W set for serial interface Page of

20 Instruction Input st Transfer D D D D D D D D nd Transfer D D D D D D D D0 Instruction Input RAM data write ( transfers/pixel) TRI=0,DFM-0=00 st Transfer D D D D D D D D Instruction code nd Transfer.. 0 D D D D D D D D0 Writer data register 0 GRAM R R R R R R0 G G G G G G0 B B B B B B0, colors are avaliable RAM data write ( transfers/pixel) TRI=,DFM-0= st Transfer nd Transfer rd Transfer Input D D D D0 D D D D D D D D D D D D D D Writer data register 0 GRAM R R R R R R0 G G G G G G0 B B B B B B0, colors are avaliable Figure Instruction /RAM Data Write (Serial interface) Page 0 of

21 ) Basic data transfer via Serial interface 0 SCL(Input) NCS Start End SDI(Input) Device ID Code Start Byte RS RW D D D D D D D D D D D D D D D D0 Index Register Set, Instruction, RAM data Write SDO(Output) D D D D D D D D D D D D D D D D0 Start read, Instruction, RAM Data Read, ) Consecutive data transfer via Serial interface SCL(Input) 0 0 NCS Start End SDI(Input) Start Byte Instruction upper byte Instruction lower buye Instruction upper byte Instruction : execution time ) RAM data read transfer SCL(Input) NCS Start End SDI(Input) Start Byte SDO(Output) Dummy Read Dummy Read Dummy Read Dummy Read Dummy Read RAM read Upper byte RAM read Lower byte ) Status Read/ Instruction Read SCL(Input) NCS Start End SDI(Input) Start Byte Dummy Read Status read Upper byte Status read Lower byte SDO(Output) Note: One byte of the read data after the start byte is invalid. The starts to read the correct status or instruction data from the second byte Figure 0 Serial Interface Data Transfer Timing Page of

22 . VSYNC Interface The supports VSYNC interface, which enables displaying a moving picture via system interface by synchronizing the display operation with the VSYNC signal. VSYNC interface can realize moving picture display with minimum modification to the conventional system operation. When the VSYNC interface mode is selected, the interface displays a moving picture through system interface with minimum modification that rewrites display data to the internal GRAM. The VSYNC interface can be used by setting DM-0= and RM=0. MPU VSYNC CSn A VSYNC NCS RS # WR# D-0 WR_N E_NWR -0 Figure VSYNC Interface to MPU DM DM0 Operation Mode 0 0 System Interface 0 RGB Interface 0 VSYNC Interface Ignore Table DM-0 Set The VSYNC interface has some constraints in the internal clock and the RAM write speed via the system interface. It requires GRAM write speed more than the minimum value that system processed and calculated. The internal clock of VSYNC interfaces can be computed by the following formula that used some parameters with FP, BP and display lines duration (NL): Internal oscillator clock (f osc )[Hz] = Frame Frequency [NL + FP + BP] RTN frequency fluctuation The parameter of frequency fluctuation is ascribed to the external resistor or voltage variation, fabrication process condition, external temperature and humidity condition etc. The minimum speed for RAM can be computed by the following formula: NL fosc The Min. RAM Write Speed [Hz] [BP + NL - Margin Line] RTN The margin line means when operate in VSYNC interface mode, it must be remained the several lines in advance for protection between the actual line of the display operation and the line address for the RAM write data operation. The calculated value is the theoretical value that the starts the RAM write operation must be taken into account. In other words, the actual value of RAM write speed must be more than theoretical value that calculated from forward formula by getting a internal oscillator clock (f osc ) first. An example of internal oscillator clock (f osc ) and minimum speed for RAM writing set up in VSYNC interface mode is as following. Example Display size: RGB x 0 lines Lines of be used: 0 lines (0) FP: lines (00) BP: lines () Frequency fluctuation: Page of

23 Frame frequency: 0Hz Internal oscillator clock (f osc ) [Hz] = 0 [0 + +] (.0/0.) khz The Min. RAM Write Speed [Hz] 0 k /{ [ + 0 -] }.MHz In this example, the minimum RAM write speed of VSYNC interface is.mhz and then necessary to setting enough or more on the falling edge of guarantees the completion write operation before the initiate the display operation and make it possible to rewrite the display area set previously. Further, if the display area were different with the anterior example, the calculated result and margin setting would be revised. For example, if the display area is smaller than that, an extra will be created between the RAM write operation and display with regard to each line. When the make the transition with system interface mode and VSYNC interface mode, the difference between that is the used of signal VSYNC for synchronization. Therefore, both of them are used the internal oscillator to generate the reference clock. The Figure illustrates the process of VSYNC interface with internal clock and system interface with internal clock mode transition, which is shown by setting register set. VSYNC RS NCS NWR N rewrite a frame rewrite a frame RAM data Write via System interface Display operation Synchronized With interface clock Figure Moving picture data transfer via VSYNC interface Page of

24 System Interface Mode to VSYNC Interface Mode VSYNC Interface Mode to System Interface Mode System Interface Mode Set AM = 0 Set AD-0 Display operation in synchronization with internal clocks operation through VSYNC interface Mode Set DM-0=00, RM=0 for System interface mode Display operation in synchronizaion with VSYNC *DM-0, RM become enable after completion of displaying frame. Wait more than frame Set DM-0 =, RM = 0 for VSYNC interface mode *DM-0, RM become eneble after completion of displaying frame. System Interface Mode Display operation in synchronization with internal clocks Set index register to Rh Wait more than frame Display operation in synchronizaion with VSYNC Write data to RAM through VSYNC Interface Operation through VSYNC interface Mode Note: input VSYNC before setting DM-0, RM. Figure Exchange of VSYNC Interface and System Interface Mode When is set up on VSYNC interface mode, the partial display function, vertical scroll function and interlaced scan function are invalid function in VSYNC interface mode. Page of

25 . RGB Interface The supports RGB interface for moving picture display and incorporates RAM for storing display data, which provides the following advantages in displaying a moving picture. ) The window address function enables transferring data only within the moving picture area. ) It becomes possible to transfer only the data written over the moving picture area. ) By reducing data transfer, it can contribute to lowering the power consumption of the whole system. ) The data in still picture area (icons etc.) can be written over via system interface while displaying a moving picture via RGB interface. The RGB interface executes in synchronization with the frame synchronizing signal (VSYNC), line synchronizing signal (HSYNC) and dot clock (DOTCLK). The display data are transferred in pixel unit via -0 bits and according to the signal of data enable (ENABLE) be described on Table. The RGB interface can be used by setting DM-0=0 and RM=. In RGB interface mode, with use of a window address function, enables to display data in a moving picture area and makes it possible to transfer the display only by rewriting a screen with minimum data transfers. EPL ENABLE RAM Write RAM Address 0 0 Enable Update 0 Disable Keep 0 Disable Keep Enable Update Table EPL and ENABLE Set When the set up in RGB interface mode, a BP starts on the falling edge of VSYNC signal, which is made at the beginning by the display operation. Furthermore, the display duration (NL-0) mean the numbers of driving lines is the subsequent data of display operation. And then the FP starts. The FP period would be continued until the next input of the VSYNC signal. The supports two types of RGB interface mode, the difference between them is the RAM access using the RGB interface (-0) or system interface (-0). The data written to the internal GRAM are synchronized with DOTCLK inputs when ENABLE is setting low. Contrary to set ENABLE high, the data written to the GRAM would be entered to the process of using the system interface. Further, when select to use system interface, set ENABLE high to stop using the RGB interface for writing data, and then set the RAM access setting bit bus (RM) low to invert RAM access operation by using system interface. After that, set address AD-0 on falling edge of VSYNC and then set the index field of register (Rh) to access RAM via the system interface. The allows rewriting data in the still picture area by using the system interface when displaying a moving picture in RGB interface mode. When return to use RGB interface to access RAM, set address AD-0, RAM access setting bit bus (RM=) and the index field of register (Rh) before accessing RAM via RGB interface. The Figure is shown the process of RAM access via the system interface with rewriting still picture and then return to RGB interface while displaying a moving picture in RGB interface mode. Page of

26 0: pm Still Picture Area Moving Picture Area Updating screen Menu Names Updating screen VSYNC ENABLE DOTCLK PD-0 System Interface Set IR to R Set IR to R Set AD -0 Updating moving picture area Set RM=0 Updata display data in other than the moving picture area Set AD -0 Updating still picture area Set RM= Set IR to R Updating moving picture area Figure Update Still and Moving Picture When set up in RGB interface mode, GRAM address (AD-0) is set in the address counter for every frame on the falling edge of VSYNC. Furthermore, the FP period would be continues until the next input of the VSYNC signal. Such as VSYNC interface mode, partial screen display function, vertical scroll function and interlaced scan function are invalid function in VSYNC interface mode. Page of

27 When the make the transition with system interface mode and RGB interface mode, the sequence of switching process must be following as Figure. System Interface Mode to RGB Interface Mode RGB Interface Mode to System Interface Mode System Interface Mode RGB Interface operation RGB Interface mode Set HWM =, AM = 0 System interface mode Set system interface mode (DM-0=00, RM=0) Set AD-0 Set RGB interface mode* (DM-0=0, RM=) *DM-0, RM become eneble after completion of displaying frame. Wait more than frame System Interface Mode (Synchronized with VSYNC, HSYNC, DOTCLK) * DM-0, RM settings become enabled after compretion of displaying one frame Set index register to Rh Wait more than frame RGB Interface operation (Synchronized with VSYNC,HSYNC,DOTCLK) Write data to RAM through RGB Interface RGB Interface operation Figure Transition between System Interface Mode and RGB Interface Mode Page of

28 When operate in RGB interface and the RAM write data transfer through system interface, the sequence of switching process must be follow as Figure. Write data through RGB interface to write data through system interface RGB interface opeartion Write data through system interface to write data through RGB interface Set (DM-0=0, RM=0) with RGB interface mode Write data to RAM through system interface Set AD-0 Set AD-0 Set IR to Rh (RAM Data Write) Set RGB interface mode (DM-0=0, RM=0) Write data to RAM through system Interface Set IR to Rh (RAM Data Read) RGB interface opeartion Figure RAM Data Write Sequence during RGB Interface Mode The supports -/-/-bit bus RGB interface by setting register RIM-0 only through the system interface. ) -bit bus RGB interface The -bit interface can be used by setting RIM-0 bits to 00. The Figure is the example of -bit RGB interface with LCD Controller and. The display operations are executed in synchronization with the frame synchronizing signal (VSYNC), line synchronizing signal (HSYNC) and dot clock (DOTCLK). The display data are transferred in pixel unit via -0 bits and according to the signal of data enable (ENABLE). The Figure is the data format of -bit RGB interface. LCD Controller VSYNC HSYNC DOTCLK ENABLE -0 Figure -bit RGB Interface Page of

29 Input 0 GRAM R R R R R R0 G G G G G G0 B B B B B B0 Figure Data Format for -bit Interface (, colors) ) -bit bus RGB interface The -bit bus interface can be used by setting RIM-0 bits to 0. The display data are transferred in pixel unit via data bus (-, - bits) to the internal GRAM and according to the signal of data enable (ENABLE). The unused pins (, 0) must be fixed to the IOVCC or VSSD level. VSYNC HSYNC LCD Controller DOTCLK ENABLE -,-,0 Figure -bit RGB Interface Input.. GRAM R R R R R R0 G G G G G G0 B B B B B B0 Figure 0 Data Format for-bit Interface (, colors) Page of

30 ) -bit bus RGB interface The -bit bus interface can be used by setting RIM-0 bits to. The display data are transferred in pixel unit via data bus (- bits) to the internal GRAM and according to the signal of data enable (ENABLE). The unused pins (-0) must be fixed to the IOVCC or VSSD level. VSYNC HSYNC LCD Controller DOTCLK ENABLE - -0 Figure -bit RGB Interface st Transfer nd Transfer rd Transfer R R R R R R0 G G G G G G0 B B B B B B0 Figure Data Format for -bit Interface (, colors) Page 0 of

31 Back poch period frame Front poch period VSYNC HSYNC DOTCLK ENABLE -0 VLW>=H VSYNC HLW>=CLK H HSYNC clock DOTCLK ENABLE DTST>=CLK -0 Valid data VLW:VSYNC Low level HLW:HSYNC Low level DTST:Data transfer startup time Note: Use a high-speed write function (either HWM = or LHWM= )when writing display data to the Internal RAM via RGB Interface Figure /-bit RGB Interface Timing Page of

32 Back poch period frame Front poch period VSYNC HSYNC DOTCLK ENABLE - VLW>=H VSYNC HLW>=CLK H HSYNC clock DOTCLK ENABLE DTST>=CLK - Valid data VLW:VSYNC Low level HLW:HSYNC Low level DTST:Data transfer startup time Notes: Use a high-speed write function (either HWM = or LHWM= )when writing display data to the Internal RAM via RGB Interface. Transfer data for one pixel (-*) with DOTCLKs. Also, the cycle of each RGB Interface signal (VSYNC HSYNC ENABLE must contain a multiple of DOTCLKs. Figure -bit RGB Interface Timing Page of

33 . Function Description. Graphics RAM GRAM is graphics RAM, which can store a maximum,00-byte (RGB x 0 (dots) x (bits)/) pattern data using bits per pixel. The GRAM address map is listed as following: G pins S pins S S S S S S S S S S S S S S 0 S S S S GS= GS= G0 G 0000H 000H 000H DH 00EH 00FH G G 00H 0H 0H DH 0EH 0FH G G 000H 00H 00H DH 0EH 0FH G G 000H 00H 00H DH 0EH 0FH G G 000H 00H 00H DH 0EH 0FH G G 000H 00H 00H DH 0EH 0FH G G 000H 00H 00H DH 0EH 0FH G G 000H 00H 00H DH 0EH 0FH G G 000H 00H 00H DH 0EH 0FH G G 000H 00H 00H DH 0EH 0FH G G 00H 0H 0H DH EH FH G G 00H 0H 0H DH EH FH G G 00H 0H 0H DH EH FH G G 00H 0H 0H DH EH FH G G A00H A0H A0H ADH AEH AFH G G B00H B0H B0H BDH BEH BFH G G C00H C0H C0H CDH CEH CFH G G D00H D0H D0H DDH DEH DFH G G E00H E0H E0H EDH EEH EFH G G0 F00H F0H F0H FDH FEH FFH Table GRAM Address and Display Panel Position (SS = 0, BGR = 0 ) Page of

34 0-system/-system -bit bus interface GRAM Data 0 RGB Assignment R R R R R R0 G G G G G G0 B B B B B B0 Output pin S(n+) S(n+) S(n+) 0-system/-system -bit bus interface Note:n= lower eight bits of address (0 to ) GRAM Data RGB Assignment R R R R R R0 G G G G G G0 B B B B B B0 Output pin S(n+) S(n+) S(n+) Note:n= lower eight bits of address (0 to ) 0-system/-system -bit bus interface st Transfer nd Transfer GRAM Data RGB Assignment Output pin R R R R R R0 G G G G G G0 B B B B B B0 S(n+) S(n+) S(n+) Note:n= lower eight bits of address (0 to ) Figure GRAM Data and Display Data of -/-/ -bit Bus Interface (SS = 0, BGR = 0 ) Page of

35 0-system/-system -bit bus interface( transfers/pixel) st Transfer nd Transfer GRAM Data RGB Assignment R R R R R R0 G G G G G G0 B B B B B B0 Output pin S(n+) S(n+) S(n+) Note:n= lower eight bits of address (0 to ) 0-system/-system -bit bus interface( transfers,k colors: TRI=,DFM-0=) st Transfer nd Transfer rd Transfer GRAM Data RGB Assignment Output pin R R R R R R0 G G G G G G0 B B B B B B0 S(n+) S(n+) S(n+) Note:n= lower eight bits of address (0 to ) 0-system/-system -bit bus interface( transfers,k colors: TRI=,DFM-0=) GRAM Data st Transfer nd Transfer rd Transfer RGB Assignment Output pin R R R R R R0 G G G G G G0 B B B B B B0 S(n+) S(n+) S(n+) Note:n= lower eight bits of address (0 to ) Figure GRAM Data and Display Data of -bit Bus Interface (SS = 0, BGR = 0 ) Page of

36 Serial Date Transfer interface ( transfers/k colors: TRI=0) st Transfer nd Transfer GRAM Data D D D D D D D D D D D D D D D D0 RGB Assignment R R R R R R0 G G G G G G0 B B B B B B0 Output pin S(n+) S(n+) S(n+) Note:n= lower eight bits of address (0 to ) Serial Date Transfer interface ( transfers/k colors: TRI=,DFM-0=) st Transfer nd Transfer rd Transfer GRAM Data D D D D0 D D D D D D D D D D D D D D RGB Assignment Output pin R R R R R R0 G G G G G G0 B B B B B B0 S(n+) S(n+) S(n+) Note:n= lower eight bits of address (0 to ) Figure GRAM data and display data of Serial Data transfer interface (SS = 0,BGR = 0 ) Page of

37 -bit RGB Interface GRAM Data 0 RGB Assignment R R R R R R0 G G G G G G0 B B B B B B0 Output pin S(n+) S(n+) S(n+) Note:n= lower eight bits of address (0 to ) -bit RGB Interface GRAM Data RGB Assignment Output pin R R R R R R0 G G G G G G0 B B B B B B0 S(n+) S(n+) S(n+) -bit RGB Interface GRAM Data Note:n= lower eight bits of address (0 to ) st Transfer nd Transfer rd Transfer RGB Assignment Output pin R R R R R R0 G G G G G G0 B B B B B B0 S(n+) S(n+) S(n+) Note:n= lower eight bits of address (0 to ) Figure GRAM Data and Display Data of RGB Interface (SS = 0, BGR = 0 ) Page of

38 G pins S pins S S S S S S S S S GS=0 GS= G G0 00FH 00EH 00DH H 000H 0000H G G 0FH 0EH 0DH H 0H 00H G G 0FH 0EH 0DH H 00H 000H G G 0FH 0EH 0DH H 00H 000H G G 0FH 0EH 0DH H 00H 000H G G 0FH 0EH 0DH H 00H 000H G G 0FH 0EH 0DH H 00H 000H G G 0FH 0EH 0DH H 00H 000H G G 0FH 0EH 0DH H 00H 000H G G 0FH 0EH 0DH H 00H 000H S S S S S 0 S S S S G G FH EH DH H 0H 00H G G FH EH DH H 0H 00H G G FH EH DH H 0H 00H G G AFH AEH ADH A0H A0H A00H G G BFH BEH BDH B0H B0H B00H G G CFH CEH CDH C0H C0H C00H G G DFH DEH DDH D0H D0H D00H G G EFH EEH EDH E0H E0H E00H G0 G FFH FEH FDH F0H F0H F00H Table GRAM Address and Display Panel Position (SS =, BGR= ) Page of

39 0-system -bit bus interface GRAM Data 0 RGB Assignment Output pin R R R R R R0 G G G G G G0 B B B B B B0 S(-n) S(-n) S(-n) Note:n= lower eight bits of address (0 to ) 0-system -bit bus interface GRAM Data RGB Assignment Output pin R R R R R R0 G G G G G G0 B B B B B B0 S(-n) S(-n) S(-n) Note:n= lower eight bits of address (0 to ) 0-system -bit bus interface st Transfer nd Transfer GRAM Data RGB Assignment Output pin R R R R R R0 G G G G G G0 B B B B B B0 S(-n) S(-n) S(-n) Note:n= lower eight bits of address (0 to ) Figure GRAM Data and Display Data of -/-/ -bit Bus Interface (SS =, BGR = ) Page of

40 0-system -bit bus interface/ Serial Date Transfer Interface( transfers/pixel) GRAM Data st Transfer nd Transfer RGB Assignment R R R R R R0 G G G G G G0 B B B B B B0 Output pin S(-n) S(-n) S(-n) Note:n= lower eight bits of address (0 to ) 0-system/-system -bit bus interface( transfers,k colors: TRI=,DFM-0=) st Transfer nd Transfer rd Transfer GRAM Data RGB Assignment Output pin R R R R R R0 G G G G G G0 B B B B B B0 S(-n) S(-n) S(-n) Note:n= lower eight bits of address (0 to ) 0-system/-system -bit bus interface( transfers,k colors: TRI=,DFM-0=) GRAM Data st Transfer nd Transfer rd Transfer RGB Assignment Output pin R R R R R R0 G G G G G G0 B B B B B B0 S(-n) S(-n) S(-n) Note:n= lower eight bits of address (0 to ) Figure 0 GRAM Data and Display Data of -bit Bus Interface (SS =, BGR = ) Page 0 of

41 Serial Date Transfer interface ( transfers/k colors: TRI=0) st Transfer nd Transfer GRAM Data D D D D D D D D D D D D D D D D0 RGB Assignment R R R R R R0 G G G G G G0 B B B B B B0 Output pin S(-n) S(-n) S(-n) Note:n= lower eight bits of address (0 to ) Serial Date Transfer interface ( transfers/k colors: TRI=,DFM-0=) st Transfer nd Transfer rd Transfer GRAM Data D D D D0 D D D D D D D D D D D D D D RGB Assignment Output pin R R R R R R0 G G G G G G0 B B B B B B0 S(-n) S(-n) S(-n) Note:n= lower eight bits of address (0 to ) Figure GRAM data and display data of Serial Data transfer interface (SS =,BGR = ) Page of

42 -bit RGB Interface GRAM Data 0 RGB Assignment R R R R R R0 G G G G G G0 B B B B B B0 Output pin S(-n) S(-n) S(-n) Note:n= lower eight bits of address (0 to ) -bit RGB Interface GRAM Data 0 RGB Assignment Output pin R R R R R R0 G G G G G G0 B B B B B B0 S(-n) S(-n) S(-n) Note:n= lower eight bits of address (0 to ) -bit RGB Interface st Transfer nd Transfer rd Transfer GRAM Data RGB Assignment Output pin R R R R R R0 G G G G G G0 B B B B B B0 S(-n) S(-n) S(-n) Note:n= lower eight bits of address (0 to ) Figure GRAM Data and Display Data of RGB Interface (SS =, BGR = ) Page of

43 .. Window Address Function Data can be written consecutively without thinking a data wrap by those bit function through Window Address Function in. The contains a GRAM -bit bus address counter (AC), when the address setting instruction is written in the IR, the address information is sent from the IR to the AC. When the data is written to the internal GRAM, the AC is automatically incremented (plus one) or decremented (minus one), which is decided by the register (AM bit and I/D bits) setting. The window address function enables writing data only within the rectangular area specified in GRAM by setting. The window address area is decided by setting the horizontal address register (start: HSA-0, end: HEA-0) and the vertical address register (start: VSA-0, end: VEA-0). The window address must be within the GRAM address map area, and the AD-0 bits must be within the window address. The window address setting range: GRAM address setting range: 00H HSA-0 HEA-0 FH 00H VSA-0 VEA-0 FH HSA-0 AD-0 HEA-0 VSA-0 AD- VEA-0 Page of

44 . Display Function.. Scan Mode Setting The can set SM and GS bits to adapt various pins assignment of gate of different panels. The combination of SM and GS settings allows changing the different shift direction of gate outputs when connecting LCD panel. SM GS Scan direction odd-number G G TFT panel G G even-number 0 0 G to G G G G G0 G to G0 G, G, G,.G, G, G0 odd-number G G TFT panel G G even-number 0 G to G G G G G0 G0 to G G0, G, G.G, G, G odd-number G 0 G to G TFT panel G G G0 even-number G to G0 G, G, G G, G ; G, G, G G, G0 odd-number G to G TFT panel G G even-number G0 G0 to G. G0, G, G G, G ; G, G, G G, G Note: scan mode is determined by the layout and design of glass on the panel. Figure Scan Mode setting Page of

45 .. Partial Screen Display Function The can drive one or two partial screen to display. The position of display screen register (Rh and Rh) can be set at any position of the whole screen. The total numbers of display lines that display on the first and second screens must be less than total LCD-driving lines determined by register NL-0. The rest display area in the panel should be white if the type of LCD is normally white and should be black if the type of LCD is normally black. Therefore, the partial display can reduce the power consumption. As the below, the first screen start line from the SS(-0) and end line at SE(-0) are specified by the st Display Screen Driving Position Register(Rh), the second screen start line from SS(-0) and end line at SE(-0) are specified by nd Display Window Driving Position Register(Rh). And the second display screen display is valid when the SPT bit is set to. The number of the total selection driving lines included the st and nd display screen must be equal to or less than the total LCD Driving Lines (set by NL). FGD Welcome Notes: Number of Scan Line: NL (-0) = "0" (0 lines) st Screen Setting: SS (-0) ="0E"h, SE (-0) ="C"h nd Screen Setting: SS (-0) ="A"h, SE (-0) ="E"h, SPT= Figure Partial Screen Display Example in Two Windows Driving Page of

46 The conditions as following must be satisfied when using this function by setting the start line SS(-0) and end line SE(-0) of the st display window at register(rh) and the start line SS(-0) and end line SE(-0) of the nd display window at register(r). Note: That incorrect display may happen if the conditions are not satisfied. Condition: 0 SS (-0) SE (-0) NL Register Settings Display Operation SE(-0 ) SS(-0) + = NL 0 < SE (-) SS (-0) + < NL Whole Screen Display The area of SE (-0)-SS (-0) is normally displayed Partial Screen Display The area of SE (-0)-SS (-0) is normally displayed. The rest area is displayed refer to the output level based on the PT (R0h) setting (non-display area). Table Conditions on One Screen Driving (STP = 0) Note: The SS (-0) and SE (-0) settings are ignored. Condition: 0 SS (-0) SE (-0) < SS (-0) SE (-0) NL Register Settings Display Operation (SE (-0) SS (-0)+)+ (SE (-0) SS (-0)+)=NL 0 < (SE (-0) SS (-0)+)+ (SE (-0) SS (-0)+) < NL Whole-Screen Display The area of SE (-0)-SS (-0) is normally displayed Partial Screen Display The area of SE (-0)-SS (-0) and SE (-0) SS (-0) is normally displayed. The rest area is displayed refer to the output level based on the PT (R0h) setting (non-display area). Table Conditions on Two Screen Driving (STP = ) The source outputs for non-display area on partial display can be determined by the register PT. Set the values to match the characteristics of the panel. PT PT0 Source Output in Non Display Area Positive Polarity Negative Polarity Gate Output in Non Display Area VCOM Output 0 0 V V0 reference to PTG VCOMH-VCOML 0 ignore ignore reference to PTG VCOMH-VCOML 0 VSSD VSSD reference to PTG VCOMH-VCOML Hi-Z Hi-Z reference to PTG -- Table Source and Gate Output in Non-Display Area during Partial Display Note: The output on the source lines during the periods of the front and BP and blanking of the partial display is determined by PT-0. PTG PTG0 Gate output in non-display area 0 0 Normal scan 0 VGL (Fixed) 0 Interval scan Setting Disabled Table Gate Output in Non-Display Area in Partial Display Page of

47 Setting of the partial display should follow the flow chart shown as below Display Whole Screen PT-0 = 00 Set bits of SS and SE Partial Screen Display Setting flow Wait Frames or more If needed PT-0 = 0 or PT-0 = or PT-0 = Display Partial Screen Set bits of SS and SE Whole Screen Display Setting Flow Display Whole Screen Figure Partial Display Setting Flow Page of

48 .. -Color Display The supports an -color display mode. The grayscale level to be used is V0 and V which is selected by R, G, B decoding, and the other levels (V-V) are halted in order to reduce the power consumption. In -color display mode, the Gamma-micro-adjustment registers are invalid and only the upper bits of RGB are used for display. Graphics RAM (GRAM) R G B OP0 OP0 OP0 OP00 OP OP OP OP OP CP0 CP0 CP00 CP CP CP V0 Positive polarity Register MP0 MP0 MP00 MP MP MP MP MP MP0 MP MP MP0 -bit Grayscale D/A Converter -bit Grayscale D/A Converter -bit Grayscale D/A Converter MP MP MP0 MP MP MP0 Grayscale Voltage Generator Output Driver Output Driver Output Driver V ON0 ON0 ON0 ON00 ON ON ON ON ON CN0 CN0 CN00 CN CN CN R G B Display Whole Screen Negative polarity Register MN0 MN0 MN00 MN MN MN MN MN MN0 MN MN MN0 MN MN MN0 MN MN MN0 LCD Figure Grayscale Control in -Color Mode Page of