Semiconductor MSM80C85AHRS/GS/JS

Transcription

1 8-Bit CMO MICROPROCEOR E2O9--8 GENRAL ECRIPTION The MM8C8AH is a complete 8-bit parallel; central processor implemented in silicon gate C-MO technology and compatible with MM8C8A. It is designed with higher processing speed (max. MHz) and lower power consumption compared with MM8C8A and power down mode is provided, thereby offering a high level of system integration. The MM8C8AH uses a multiplexed address/data bus. The address is split between the 8-bit address bus and the 8-bit data bus. The on-chip address latch : of a MM8C- memory product allows a direct interface with the MM8C8AH. FEATURE Power down mode (HALT-HOL) Low Power issipation: mw(typ) ingle + 3 to + V Power upply to + 8 C, Operating Temperature Compatible with MM8C8A.8 ms instruction Cycle (V CC = V) On-Chip Clock Generator (with External Crystal) On-Chip ystem Controller; Advanced Cycle tatus Information Available for Large ystem Control Bug operation in MM8C8AH is fixed Four Vectored interrupt (One is non-maskable) Plus the 88A-compatible interrupt. erial, In/erial Out Port ecimal, Binary and ouble Precision Arithmetic Addressing Capability to K Bytes of Memory TTL Compatible -pin Plastic IP(IP-P--2.): (Product name: MM8C8AHR) -pin Plastic QFJ(QFJ-P--.2): (Product name: MM8C8AHJ) -pin Plastic QFP(QFP-P K): (Product name: MM8C8AHG-2K) 3

2 FUNCTIONAL BLOCK IAGRAM RT INTR INTA... TRAP I O Interrupt Control erial I/O Control 8-Bit Internal ata Bus Accumulator (8) Temporary Register (8) Flag () Flip Flops Instruction Register (8) Arithmetic Logic Unit ALU(8) Instruction ecoder And Machine Cycle Encoding B REG (8) C REG (8) REG (8) E REG (8) H REG (8) C REG (8) tack Pointer () Register Array Power upply +V GN Program Counter () Incrementer/ecrementer Address Latch () X X 2 Power own CLK GEN Timing And Control Control tatus MA Reset Address Buffer (8) ata/address Buffer (8) CLK OUT REAY R WR ALE IO / M HOL HLA REET IN REET OUT A - A 8 Address Bus A - A Address/ata Bus 3

3 PIN CONFIGURATION (TOP VIEW) pin Plastic IP I O 3 pin Plastic QFP REET OUT X 2 X NC V CC HOL HLA X X 2 REET OUT O I TRAP RT. RT. RT. INTR INTA A A A 2 A 3 A A A A GN V CC HOL HLA CLK(OUT) REET IN REAY IO/M R WR ALE A A A 3 A 2 A A A 9 A 8 TRAP 33 REAY RT. 32 IO/M RT. 3 RT. 3 R INTR 29 WR INTA 28 ALE A A 2 2 pin Plastic QFJ TRAP RT. RT REAY 38 IO/M 3 RT. INTR NC 2 INTA 3 3 R 3 WR 3 NC 33 ALE A NC A A A GN A I O REET OUT X 2 X NC V CC A A A A 3 29 A 3 A A A 9 A A A CLK(OUT) 3 REET IN A A 2 9 A A A 3 NC 23 A A A A A GN V CC A 8 A 9 A A NC HOL HLA CLK(OUT) REET IN 3

4 MM8C8AH FUNCTIONAL PIN EFINITION The following describes the function of each pin: ymbol A 8 - A (Output, 3-state) A - A (Input/Output) 3-state ALE (Output),, IO/M (Output) R (Output, 3-state) WR (Output, 3-state) REAY (Input) HOL (Input) HLA (Output) INTR (Output) INTA (Output) RT. RT. RT. (Input) TRAP (Input) Function Address Bus: The most significant 8-bits of the memory address or the 8-bits of the I/O address, 3-stated during Hold and Halt modes and during REET. Multiplexed Address/ata Bus: Lower 8-bits of the memory address (or I/O address) appear on the bus during the first clock cycle (T state) of a machine cycle. It then becomes the data bus during the second and third clock cycles. Address Latch Enable: It occurs during the first clock state of a machine cycle and enables address to get latched into the on-chip latch peripherals. The falling edge of ALE is set to guarantee setup and hold times for the address information. The falling edge ALE can also be used to strobe the status information ALE is never 3-state. Machine cycle status: IO/M tates Memory write Memory read I/O write I/O read Opcode fetch IO/M tates can be used as an advanced R/W status. IO/M, and become valid at the beginning of a machine cycle and remain stable throughout the cycle. The falling edge of ALE may be used to latch the state of these lines. REA control: A low level on R indicates the selected memory or I/O device is to be read that the ata Bus is available for the data transfer, 3-stated during Hold and Halt modes and during REET. WRITE control: A low level on WR indicates the data on the ata Bus is to be written into the selected memory or I/O location. ata is set up at the trailing edge of WR, 3-stated during Hold and Halt modes and during REET. If REAY is high during a read or write cycle, it indicates that the memory or peripheral is ready to send or receive data. If REAY is low, the cpu will wait an integral number of clock cycles for REAY to go high before completing the read or write cycle REAY must conform to specified setup and hold times. HOL indicates that another master is requesting the use of the address and data buses. The cpu, upon receiving the hold request, will relinquish the use of the bus as soon as the completion of the current bus transfer. Internal processing can continue. The processor can regain the bus only after the HOL is removed. When the HOL is acknowledged, the Address, ata, R, WR, and IO/M lines are 3-stated. And status of power down is controlled by HOL. HOL ACKNOWLEGE: Indicates that the cpu has received the HOL request and that it will relinquish the bus in the next clock cycle. HLA goes low after the Hold request is removed. The cpu takes the bus one half clock cycle after HLA goes low. INTERRUPT REQUET: Is used as a general purpose interrupt. It is sampled on during the next to the last clock cycle of an instruction and during Hold and Halt states. If it is active, the Program Counter (PC) will be inhibited from incrementing and an INTA will be issued. uring this cycle a RETART or CALL instruction can be inserted to jump to the interrupt service routine. The INTR is enabled and disabled by software. It is disabled by Reset and immediately after an interrupt is accepted. Power down mode is reset by INTR. INTERRUPT ACKNOWLEGE: Is used instead of (and has the same timing as) R during the instruction cycle after an INTR is accepted. RETART INTERRUP: These three inputs have the same timing as INTR except they cause an internal RETART to be automatically inserted. The priority of these interrupts is ordered as shown in Table. These interrupts have a higher priority than INTR. In addition, they may be individually masked out using the IM instruction. Power down mode is reset by these interrupts. Trap interrupt is a nonmaskable RETART interrupt. It is recognized at the same timing as INTR or RT. -.. It is unaffected by any mask or Interrupt isable. It has the highest priority of any interrupt. (ee Table.) Power down mode is reset by input of TRAP.... Interrupt Acknowledge Halt = 3-state Hold (high impedance) Reset = unspecified 38

5 ymbol REET IN (Input) REET OUT (Output) X, X 2 (Input) CLK (Output) I (Input) O (Output) V CC GN Function ets the Program Counter to zero and resets the Interrupt Enable and HLA flip-flops and release power down mode. The data and address buses and the control lines are 3-stated during REET and because of the asynchronous nature of REET IN, the processor's internal registers and flags may be altered by REET with unpredictable results. REET IN is a chmitt-triggered input, allowing connection to an R-C network for power-on REET delay. The cpu is held in the reset condition as long as REET IN is applied. Indicated cpu is being reset. Can be used as a system reset. The signal is synchronized to the processor clock and lasts an integral number of clock periods. X and X 2 are connected to a crystal to drive the internal clock generator. X can also be an external clock input from a logic gate. The input frequency is divided by 2 to give the processor's internal operating frequency. Clock Output for use as a system clock. The period of CLK is twice the X, X 2 input period. erial input data line. The data on this line is loaded into accumulator bit whenever a RIM instruction is executed. erial output data line. The output O is set or reset as specified by the IM instruction. + Volt supply Ground Reference. Name TRAP RT. RT. RT. INTR Table Interrupt Priority, Restart Address, and ensitivity Priority 2 3 Address Branched To () When Interrupt Occurs 3CH 3H 2CH (2) Type Trigger 2H Rising edge and high level unit sampled. Rising edge (latched). High level unitl sampled. High level until sampled. High level until sampled. Notes: () The processor pushes the PC on the stack before branching to the indicated address. (2) The address branched to depends on the instruction provided to the cpu when the interrupt is acknowledged. 39

6 FUNCTIONAL ECRIPTION The MM8C8AH is a complete 8-bit parallel central processor. It is designed with silicon gate C- MO technology and requires a single + volt supply. Its basic clock speed is MHz, thus improving on the present MM8C8A's performance with higher system speed and power down mode. Also it is designed to fit into a minimum system of two IC's: The CPU (MM8C8AH), and a RAM/IO (MM8C-) The MM8C8AH has twelve addressable 8-bit register pairs. ix others can be used interchangeably as 8-bit registers or -bit register pairs. The MM8C8AH register set is as follows: Mnemonic ACC or A PC BC, E, HL P Flags or F Register Accumulator Program Counter General-Purpose Registers; data pointer (HL) tack Pointer Flag Register Contents 8-bits -bit address 8-bit or -bits 3 -bit address flags (8-bit space) The MM8C8AH uses a multiplexed ata Bus. The address is spilt between the higher 8-bit Address Bus and the lower 8-bit Address/ata Bus. uring the first T state (clock cycle) of a machine cycle the low order address is sent out on the Address/ata Bus. These lower 8-bits may be latched externally by the Address Latch Enable signal (ALE). uring the rest of the machine cycle the data bus is used for mamory or I/O data. The MM8C8AH provides R, WR,,, and IO/M signals for bus control. An Interrupt Acknowledge signal (INTA) is also provided. Hold and all Interrupts are synchronized with the processor's internal clock. The MM8C8AH also provides erial Input ata (I) and erial Output ata (O) lines for a simple serial interface. In addition to these features, the MM8C8AH has three maskable, vector interrupt pins, one nonmaskable TRAP interrupt and power down mode with HALT and HOL. INTERRUPT AN ERIAL I/O The MM8C8AH has interrupt inputs: INTR, RT. RT., RT., and TRAP. INTR is identical in function to the 88A INT. Each of the three RETART inputs,.,., and., has a programmable mask. TRAP is also a RETART interrupt but it is nonmaskable. The three maskable interrupts cause the internal execution of RETART ( saving the program counter in the stack branching to the RETART address) it the interrupts are enable and if the interrupt mask is not set. The nonmaskable TRAP causes the internal execution of a RETART vector independent of the state of the interrupt enable or masks. (ee Table.) There are two different types of inputs in the restart interrupt. RT. and RT. are high levelsensitive like INTR (and INT on the 88A) and are recognized with the same timing as INTR. RT. is rising edge-sensitive.

7 For RT., only a pulse is required to set an internal flip-flop which generates the internal interrupt request. The RT. request flip-flop remains set until the request is serviced. Then it is reset automatically, This flip-flop may also be reset by using the IM instruction or by issuing a REET IN to the MM8C8AH. The RT. internal flip-flop will be set by a pulse on the RT. pin even when the RT. interrupt is masked out. The interrupts are arranged in a flixed priority that determines which interrupt is to be recognized if more than one is pending, as follows: TRAP-highest priority, RT., RT., RT., INTRlowest priority. This priority scheme does not take into account the priority of a routine that was started by a higher priority interrupt. RT. can interrupt an RT. routine if the interrupt are reenabled before the end of the RT. routine. The TRAP interrupt is useful for catastrophic evens such as power failure or bus error. The TRAP input is recognized just as any other interrupt but has the highest priority. It is not affected by any flag or mask. The TRAP input is both edge and level sensitive. The TRAP input must go high and remain high until it is acknowledged. It will not be recognized again until it goes low, then high again. This avoids any false triggering due to noise or logic glitches. Figure 3 illustrates the TRAP interrupt request circuitry within the MM8C8AH. Note that the servicing of any interrupt (TRAP, RT., RT., RT.,INTR) disables all future interrupts (except TRAPs) until an El instruction is executed. The TRAP interrupt is special in that it disables interrupts, but preserves the previous interrupt enable status. Performing the first RIM instruction following a TRAP interrupt allows you to determine whether interrupts were enabled or disabled prior to the TRAP. All subsequent RIM instructions provide current interrupt enable status. Performing a RIM instruction following INTR or RT.-. will provide current interrupt Enable status, revealing that Interrupts are disabled. The serial I/O system is also controlled by the RIM and IM instructions. I is read by RIM, and IM sets the O data. External TRAP Interrupt Request TRAP Inside the MM8C8AH REET IN REET chmitt Trigger + V CLK Q F/F Clear Internal TRAP F.F TRAP Acknowledge TRAP Interrupt Request Figure 3 Trap and REET IN Circuit

8 RIVING THE X AN X 2 INPU You may drive the clock inputs of the MM8C8AH with a crystal, or an external clock source. The driving frequency must be at least MHz, and must be twice the desired internal clock frequency; hence, the MM8C8AH is operated with a MHz crystal (for 3 MHz clock). If a crystal is used, it must have the following characteristics: Parallel resonance at twice the clock frequency desired C L (load capacitance) 3 pf C (shunt capacitance) pf R (equivalent shunt resistance) ohms rive level: mw Frequency tolerance: ±.% (suggested) Note the use of the capacitors between X, X 2 and ground. These capacitors are required to assure oscillator startup at the correct frequency. Figure shows the recommended clock driver circuits. Note in B that a pull-up resistor is required to assure that the high level voltage of the input is at least V. For driving frequencies up to and including MHz you may supply the driving signal to X, and leave X 2 open-circuited (Figure B). To prevent self-oscillation of the MM8C8AH, be sure that X 2 is not coupled back to X through the driving circuit. A. Quartz Crystal Clock river B. - MHz Input Frequency External Clock rive Circuit X MM8C8AH C C 2 X 2 C INT = pf V IH >.8 V CC High time > ns Low time > ns * X X 2 33 pf Capacitor required for crystal frequency to.2 MHz pf Capacitor required for crystal frequency.2 to MHz pf Capacitor required for crystal frequency < MHz Note: ince the constant values may vary depending on oscillator, consult the manufacturer of the oscillator used when designing a circuit. Figure Clock river Circuits * X 2 Left Floating 2

9 BAIC YTEM TIMING The MM8C8AH has a multiplexed ata Bus. ALE is used as a strobe to sample the lower 8-bits of address on the ata Bus. Figure shows an instruction fetch, memory read and I/O write cycle (as would occur during processing of the OUT instruction). Note that during the I/O write and read cycle that the I/O port address is copied on both the upper and lower half of the address. There are seven possible types of machine cycles. Which of these seven takes place is defined by the status of the three status lines (IO/M,, ) and the three control signals (R, WR,and INTA). (ee Table 2.) The status line can be used as advanced controls (for device selection, for example), since they become active at the T state, at the outset of each machine cycle. Control lines R and WR become active later, at the time when the transfer of data is to take place, so are used as command lines. A machine cycle normally consists of three T states, with the exception of OPCOE FETCH, which normally has either four or six T states (unless WAIT or HOL states are forced by the receipt of REAY or HOL inputs). Any T state must be one of ten possible states, shown in Table 3. Table 2 MM8C8AH Machine Cycle Chart Machine Cycle Opcode Fetch (OF) Memory Read (MR) O Memory Write (MW) O I/O Read (IOR) I/O Write (IOW) Acknowledge of INTR (INA) Bus Idle (BI): A ACK. OF RT, TRAP HALT tatus O O O O Control IO/M R WR INTA 3

10 tatus & Buses Control Machine tate, IO/M A 8 A A A R, WR INTA ALE T () T 2 T WAIT T 3 T (2) T (2) T T REET T HALT T HOL Table 3 MM8C8AH Machine tate Chart (2) = Logic "" = Logic "" = High Impedance = Unspecified Notes: () ALE not generated during 2nd and 3rd machine cycles of A instruction. (2) IO/M = during T - T of INA machine cycle. CLK A 8- T M M 2 M 3 T 2 T 3 T T T 2 T 3 T T 2 T 3 T PC H (High Order Address) (PC+) H IO Port A - ALE PC L (Low Order Address) ata from Memory (Instruction) (PC+) L ata from Memory (I/O Port Address) IO Port ata to Memory or Peripheral R WR IO/M TATU (Fetch) (Read) Write Figure MM8C8AH Basic ystem Timing

11 POWER OWN Mode The MM8C8AH is compatible with the MM8C8A in function and POWER OWN mode. This reduces power consumption further. There are two methods available for starting this POWER OWN mode. One is through software control by using the HALT command and the other is under hardware control by using the pin HOL. This mode is released by the HOL, REET, and interrupt pins (TRAP, RT., RT. RT., or INTR). (ee Table.) ince the sequence of HALT, HOL, REET, and INTERRUPT is compatible with MM8C8A, every the POWER OWN mode can be used with no special attention. Table POWER OWN Mode Releasing Method tart by means of Halt command tart by means of HOL pin Released by using pins REET and INTERRUPT (not by pin HOL) Released by using REET and HOL pins (not by interrupt pins) () tart by means of HALT command (ee Figures and.) The POWER OWN mode can be started by executing the HALT command. At this time, the system is put into the HOL status and therefore the POWER OWN mode cannot be released even when the HOL is released later. In this case, the POWER OWN mode can be released by means of the REET or interrupt. (2) tart by means of HOL pin (ee Figure 8.) uring the execution of commands other than the HALT, the POWER OWN mode is started when the system is put into HOL status by means of the HOL pin. ince no interrupt works during the execution of the HOL, the POWER OWN mode cannot be released by means of interrupt pins. In this case, the POWER OWN mode can be released either by means of the REET pin or by releasing the HOL status by means of HOL pin.

12 T M M 2 T T 2 M T 2 T 3 T T T HLT T REET CLK (OUT) ALE A - Address H Address Address CPU MOE Run Power own Run REET IN Figure tarted by HALT and Released by REET IN M M 2 M T T 2 T T 2 T 3 T T T HLT CLK (OUT) ALE RT. CPU MOE Run Power own Run Figure tarted by HALT and Released by RT. M M T T 2 T T 2 T 3 T T HOL CLK (OUT) ALE HOL HLA CPU MOE Run Power own RUN Figure 8 tarted and Released by HOL

13 ABOLUTE MAXIMUM RATING Parameter ymbol Condition MM8C8AHR Limits MM8C8AHG Units MM8C8AHJ Power upply Voltage V CC. - V With respect Input Voltage V IN. - V CC +. V to GN Output Voltage V OUT. - V CC +. V torage Temperature T TG - + C Power issipation P Ta = 2 C... W OPERATING RANGE Parameter ymbol Limits Unit Power upply Voltage V CC 3 - V Operating Temperature T OP - +8 C RECOMMENE OPERATING CONITION Parameter ymbol. Typ. Max. Unit Power upply Voltage V CC.. V Operating Temperature T OP C "L" Input Voltage V IL V "H" Output Voltage V IH 2.2 V CC +.3 V REET IN "L" V ILR Input Voltage "H" REET IN Input Voltage V IHR 3. V CC +.3 V V C CHARACTERITIC Parameter ymbol Conditions. Typ. Max. Unit "L" Output Voltage V OL I OL = 2. ma. V "H" Output Voltage V OH I OH = 2. ma 3. V I OH = ma V CC -. V Input Leak Current I LI V IN V CC V CC =. V -. V ma Output Leak Current I LO V OUT V CC Ta = C - +8 C ma T cyc = 2 ns 2 ma C L = pf at reset Operating upply I CC Current T cyc = 2 ns ma C L = pf at power down mode

14 AC CHARACTERITIC (Ta = C ~ 8 C, V CC =. V ~. V) Parameter ymbol Condition. Max. Unit CLY Cycle Period t CYC 2 2 ns CLY Low Time t ns CLY High Time t 2 ns CLY Rise and Fall Time t r, t f 3 ns X Rising to CLK Rising t XKR 2 2 ns X Rising to CKK Falling t XKF 3 ns A 8 ~ Valid to Leading Edge of Control () t AC ns A ~ Valid to Leading Edge of Control t ACL ns A ~ Valid ata in t A 3 ns Address Float After Leading Edge of R INTA t AFR ns A 8 ~ Valid Before Trailing Edge of ALE () t AL ns A ~ Valid Before Trailing Edge of ALE t ALL ns REAY Valid from Address Valid t ARY ns Address (A 8 ~ ) Valid After Control t CA ns Width of Control Law (R, WR, INTA) t CC 23 ns Trailing Edge of Control to Leading Edges of ALE t CL 2 ns ata Valid to Trailing Edge of WR t W 23 ns HLA to Bus Enable t HABE ns Bus Float After HLA t HABF t CYC =2 ns ns HLA Valid to Trailing Edge of CLK t HACK CL= pf ns HOL Hold Time t HH ns HOL tep Up Time to Trailing Edge of CLK t H 2 ns INTR Hold Time t INH ns INTR, RT and TRAP etup Time to Falling Edge of CLK t IN ns Address Hold Time After ALE t LA ns Trailing Edge of ALE to Leading Edge of Control t LC ns ALE Low uring CLK High t LCK ns ALE to Valid ata uring Read t LR 2 ns ALE to Valid ata uring Write t LW ns ALE Width t LL 8 ns ALE to REAY table t LRY 3 ns Trailing Edge of R to Re-enabling of Address t RAE 9 ns R (or INTA) to Valid ata t R ns Control Trailing Edge to Leading Edge of Next Control t RV 22 ns ata Hold Time After R INTA () t RH ns REAY Hold Time t RYH ns REAY etup Time to Leading Edge of CLK t RY ns ata Valid After Trailing Edge of WR t W ns LEAING Edge of WR to ata Vaild t WL 2 ns 8

15 Notes: () A 8 - A address pecs apply to IO/M, and. (2) Test condition: t CYC =2 ns C L = pf (3) For all output timing where C L = pf use the following correction factors: 2 pf C L < pf :.ns/pf pf < C L 2 pf : +.3ns/pF () Output timings are measured with purely capacitive load. () All timings are measured to output voltage V L =.8 V, V H =2.2 V, and. V with ns rise and fall time on inputs. () To calculate timing specifications at other values of t CYC use Table. () ata hold time is guaranteed under all loading conditions. Input Waveform for A.C. Tests: Test Points.8.8 Table Bus Timing pecification as a T CYC ependent (Ta = - C - +8 C, V CC =. V -. V, C L = pf) MM8C8AH t AL (/2)T - t LA (/2)T - t LL (/2)T - 2 t LCK (/2)T - t LC t A t R (/2)T - (/2+N)T - (3/2+N)T - Max Max t RAE (/2)T - t CA (/2)T - t W (3/2+N)T - t W (/2)T - t CC (3/2+N)T - t CL (/2)T - t ARY (3/2)T - 2 Max t HACK (/2)T - t HABF (/2)T + Max t HABE (/2)T + Max t AC (2/2)T - 8 t (/2)T - t 2 (/2)T - 3 t RV (3/2)T - 8 t LR (2+N)T -3 Max Note: N is equal to the total WAIT states. T = t CYC 9

16 X INPUT CLK OUTPUT t XKR t t XKF t r t 2 t f t CYC Figure Clock Timing Waveform REA OPERATION T T 2 T 3 T CLK t LCK t CA A 8 -A Address A -A Address t A t RH ata In t RAE t LL t LA ALE t AFR t LR t CL t AL t R R / INTA t LC t CC t AC WRITE OPERATION T T 2 T 3 T CLK t LCK A 8 -A Address t LW t CA A -A Address ata Out ALE t LL t LA t WL t W t W t AL WR t AC t LC t CC t CL

17 Read operation with Wait Cycle (Typical) same REAY timing applies to WRITE operation CLK T T 2 T WAIT T 3 T t LCK t CA A 8 ~A Address A ~A Address t A t RH ata In t RAE t LL t LA ALE t AFR t LR t R t CL t AL R / INTA t CL t CC t AC t ARY t RY t RYH REAY t LRY Note: REAY must remain stable during setup and hold times. Figure MM8C8AH Bus Timing, With and Without Wait HOL OPERATION CLK T 2 T 3 T HOL T HOL T HOL HLA t H t HH t HACK t HABF t HABE BU (Address, Controls) Figure 8 MM8C8AH Hold Timing

18 T T 2 T T T T HOL T T 2 A 8- A - ALE Call Inst Bus Floating () R INTA t HABE INTR t IN t INH HOL HLA t H t HACK t HH t HABF NOTE: () IO/M is also floating during this time. Figure 9 MM8C8AH Interrupt and Hold Timing 2

19 Table 8 Instruction et ummary Mnemonic escription MOVE, LOA, AN TORE MOVr r2 Move register to register MOV M r Move register to memory MOV r M Move memory to register MVI r Move immediate register MVI M Move immediate memory LXI B Load immediate register Pair B & C LXI Load immediate register Pair & E LXI H Load immediate register Pair H & L LXI P Load immediate stack pointer TAX B tore A indirect TAX tore A indirect LAX B Load A indirect LAX Load A indirect TA tore A direct LA Load A direct HL tore H & L direct LHL Load H & L direct XCHG Exchange & E H & L registers TACK OP PUH B PUH PUH H PUH PW POP B POP POP H POP PW XTHL PHL JUMP JMP JC JNC JZ JNZ JP JM JPE JPO PCHL CALL CALL CC CNC CZ CNZ CP CM CPE CPO Push register Pair B & C on stack Push register Pair & E on stack Push register Pair H & L on stack Push A and Flags on stack Pop register Pair B & C off stack Pop register Pair & E off stack Pop register Pair H & L off stack Pop A and Flags off stack Exchange top of stack H & L H & L to stack pointer Jump unconditional Jump on carry Jump on no carry Jump on zero Jump on no zero Jump on positive Jump on minus Jump on parity even Jump on parity odd H & L to program counter Call unconditional Call on carry Call on no carry Call on zero Call on no zero Call on positive Call on minus Call on parity even Call on parity odd Instruction Code () Clock (2) 3 2 Cycles / / / / / / / / 8 9/8 9/8 9/8 9/8 9/8 9/8 9/8 9/8 3

20 Table 8 Instruction et ummary cont'd Mnemonic RETURN RET RC RNC RZ RNZ RP RM RPE RPO escription Return Return on carry Return on no carry Return on zero Return on no zero Return on positive Return on minus Return on parity even Return on parity odd Instruction Code () Clock (2) 3 2 Cycles RETART RT Restart A A A 2 INPUT/OUTPUT IN OUT Input Output INCREMENT AN ECREMENT INR r Increment register CR r ecrement register INR M Increment memory CR M ecrement memory INX B Increment B & C registers INX Increment & E registers INX H Increment H & L registers INX P Increment stack pointer CX B ecrement B & C CX ecrement & E CX H ecrement H & L CX P ecrement stack pointer A A r AC r A M AC M AI ACI A B A A H A P UBTRACT UB r BB r UB M BB M UI BI Add register to A Add register to A with carry Add memory to A Add memory to A with carry Add immediate to A Add immediate to A with carry Add B & C to H & L Add & E to H & L Add H & L to H & L Add stack pointer to H & L ubtract register from A ubtract register from A with borrow ubtract memory from A ubtract memory from A with borrow ubtract immediate from A ubtract immediate from A with borrow /2 /2 /2 /2 /2 /2 /2 /2

21 Table 8 Instruction et ummary cont'd Mnemonic escription Instruction Code () Clock (2) 3 2 Cycles LOGICAL ANA r XRA r ORA r CMP r ANA M XRA M ORA M CMP M ANI XRI ORI CPI Add register with A Exclusive Or register with A Or register with A Compare register with A And memory with A Exclusive Or Memory with A Or memory with A Compare memory with A And immediate with A Exclusive Or immediate with A Or immediate with A Compare immediate with A ROTATE RLC RRC RAL RAR Rotate A left Rotate A right Rotate A left through carry Rotate A right through carry PECIAL CMA TC CMC AA Complement A et carry Complement carry ecimal adjust A CONTROL EI I NOP HLT RIM IM Enable Interrupts isable Interrupts No-operation Halt (Power down) Read Interrupt Mask et Interrupt Mask Notes: () or. B. C.. E. H. L. Memory. A. (2) Two possible cycle times, (/2) indicate instruction cycles dependent on condition flags. Precautions for operation () When the oscillation circuit is to be used, keep the RE input low until the oscillation is sufficiently stabilized after power is turned on. (2) When power is turned on, the output level (O etc.) is unknown before the equipment is reset. (3) Bug of MM8C8A 2 at power down has fixed. () Because pike Noise would be output on HLA, REET OUT and CLK pins, depending on the customers condition of usage; please take into account this issue at ystem Board design.

22 UPPLEMENTARY EXPLANATION () IM instruction: The execution of the IM instruction uses the contents of the accumulator to mask MM8C8AH interrupts. Accumulator etting Value Bit 3 2 R. ME M. M. M. R. (Reset interrupt. Flip-flop): When this bit is set to, the edge detecting flip-flop of RT. interrupt is reset. ME (Mask et Enable): When this bit is set to, the interrupt mask bits are valid. M. (Mask RT.): When this bit is set to and ME bit is set to, RT. interrupt is masked. M. (Mask RT.): When this bit is set to and ME bit is set to, RT. interrupt is masked. M. (Mask RT.): When this bit is set to and ME bit is set to, RT. interrupt is masked. (2) RIM instruction: When the contents of the accumulator are read out after RIM instruction has been executed, MM8C8AH interrupt status can be known. Accumulator Reading Value Bit IE M. M. M.. (Pending RT.): When RT. interrupt is pending, "" is read out.. (Pending RT.): When RT. interrupt is pending, "" is read out.. (Pending RT.): When RT. interrupt is pending, "" is read out. IE (Interrupt Enable Flag): When interrupt is Enable, "" is read out. M. (Mask RT.): When RT. interrupt is masked, "" is read out. M. (Mask RT.): When RT. interrupt is masked, "" is read out. M. (Mask RT.): When RT. interrupt is masked,"" is read out.