Logic Design ( Part 3) Sequential Logic (Chapter 3)

Transcription

1 o Far: Combinational Logic Logic esign ( Part ) equential Logic (Chapter ) Based on slides McGraw-Hill Additional material 24/25/26 Lewis/Martin Additional material 28 oth Additional material 2 Taylor Additional material 2 Farmer Additional material 24 Narahari Combinational Logic: Always gives the same output for a given set of inputs Aka state-less (i.e., no state or memory ) equential Logic: Its output depends on its inputs & its last output! Forms the basis for state or memory for a computer Combinational vs. equential Combinational Circuit always gives the same output for a given set of inputs ex: adder always generates sum and carry, regardless of previous inputs equential Circuit stores information output depends on stored information (state) plus input so a given input might produce different outputs, depending on the stored information example: elevator Current floor increases when you go up output depends on previous state and inputs (request for current floor) useful for building memory elements and state machines Finite tate Machines The behavior of sequential circuits can be expressed using characteristic tables or finite state machines (FMs). FMs consist of a set of nodes that hold the states of the machine and a set of arcs that connect the states. irected graph to represent a FM Moore and Mealy machines are two types of FMs that are equivalent. They differ only in how they express the outputs of the machine. Moore machines place outputs on each node/state Associate an output with each state Mealy machines present their outputs on the transitions.

2 Example: A Vending Machine Accept user input (coins), when total is at least 75 cents dispense output (soda) Input valid coins: (25cents) () or N (5) What should it keep track of? current total Is it 75 cents or more? When it reaches 75 or more: Generate output esign a Counter: counts from to 7 tates of the machine? Finite tate Machine epresentation of Counter eset Bubbles represent all possible states for the machine (aka your flip-flop based circuit) tate Machine type of sequential circuit Combines combinational logic with storage emembers state, and changes output (and state) based on inputs and current state tate Machine Arrows show movement from one state to the next Inputs Combinational Logic Circuit Outputs Transitions occur at pulse of the clock torage Elements 2

3 equential Logic Where do we start: Build a device, using combinational logic devices, to store a value Latch (also called Latch) concept of memory Build it using the devices we have thus far How? Use feedback circuit What is the methodology behind design of sequential logic circuits Finite tate Machines Example of Vending machine Feedback Circuits What happens if we feed the output of a combinational logic circuit to an input in the circuit? This is the key to circuits that can store values! table circuit Output point of circuit retains value indefinitely Unstable circuit tate that remains constant only for a duration of a few gate delays Combine sequential and combinational logic devices to assemble a simple processor! Feedback circuits download equential Circuits: sequential.cdl Open in Cedar Logic Page of equential Circuits: Example How do the two circuits behave? Feedback Circuits To retain their state values, sequential circuits rely on feedback. Feedback in digital circuits occurs when an output is looped back to the input. A simple example of this concept is shown below. If is it will always be, if it is, it will always be. Why?

4 Latches and Flip-Flops Latch: basic circuit for storage Operate on changes in Level (i.e., or ) Flip-flop: equential circuits take input from output of storage Latches that work on change of level can lead to unstable sequential circuits As level changes the outputs change --- inputs change! Flip-Flop circuits designed to operate properly when they are part of a sequential circuit Most Basic equential Logic Circuit: - Latch Most fundamental unit for static memory Has the ability to store its last output - Latch Cross-Coupled NAN gates Output of each NAN gate serves as input to the other Two inputs: (ET) & (EET) Two outputs: and NOT() ecall: NOT()= ~ = = Called a Latch because it can Latch onto data coming in ~ - Latch The - latch is a bi-stable circuit which means that it can happily exist in either of two stable states. Just like a see-saw. You can push the latch from one state to another by setting or resetting it with the - signals The logic levels are maintained because of the feedback paths from outputs to inputs. Most Basic equential Logic Circuit: - Latch Most fundamental unit for static memory Has the ability to store its last output - Latch Cross-Coupled NAN gates Output of each NAN gate serves as input to the other Two inputs: (ET) & (EET) Two outputs: and NOT() ecall: NOT()= ~ = = Called a Latch because it can Latch onto data coming in ~ Another common way of drawing the same circuit 4

5 Latch Page 2 of equential Circuits: Example Figure on top of page (with one circuit) First, set =, = What is the output? Next, set =, = What is the output? Next, set =, = What is the output? Next, set =, = What is the output? Most Basic equential Logic Circuit: - Latch First, recall truth table for a NAN gate: - Latch Operation: Best place to start is =, = = ~ = A B C X Next, look at top NAN gate Its inputs are: and Blue, comes from lower NAN Produces a at its output Therefore, when =, = The output of latch is: =, ~= -8 Most Basic equential Logic Circuit: - Latch First, recall truth table for a NAN gate: - Latch Operation: = ~ = A B C Truth Table for - Latch: ACTION ~ EET Called the EET action, as is set to Also, notice: and ~ opposite Most Basic equential Logic Circuit: - Latch Truth table for a NAN gate: - Latch Operation: = ~ = A B C Truth Table for - Latch: ACTION ~ ET EET HOL HOL HOL s last value on its outputs! -2 OUTPUT depends on input and last output 5

6 Most Basic equential Logic Circuit: - Latch Truth table for a NAN gate: A B C Most Basic equential Logic Circuit: - Latch Truth table for a NAN gate: A B C - Latch Operation: Next input case is called the ET, when inputs are: =, = = ~ = X st look at upper NAN gate Its inputs are: and X (anything) Produces a at its output Lower NAN gate Inputs are: and Produces a at its output - Latch Operation: = ~ = Truth Table for - Latch: ACTION ~ ET EET -22 ETs LATCH to have a at the output Most Basic equential Logic Circuit: - Latch Truth table for a NAN gate: A B C Most Basic equential Logic Circuit: - Latch Truth table for a NAN gate: A B C - Latch Operation: Last valid input case is the HOL =, = If we have just ET Latch, we will have =, ~=, already on outputs = ~ = Upper NAN gate Has = & former value of ~= Produces a at its output (same ~ as when it started) Lower NAN gate Inputs are: and Produces a at its output (same ) - Latch Operation: = ~ = Truth Table for - Latch: ACTION ~ ET EET HOL HOL s value we ET last -24 6

7 torage - Cross-Coupled NANs (- Latch) Using multiple latches ~ Figure on Page : Multiple latches. What is this circuit doing? tore bit number! What happens with = and =? hort answer: confusion eal circuits depend on both and ~ trange things may happen if both are ACTION ~ ILLEGAL ET EET HOL HOL -Latches shows a way to prevent the Latch from ever getting == as its input torage - Cross-Coupled NANs (- Latch) How does this device store data? Each latch can store -bit of information, Latches, holds -bits Let s assume we wish to store the number 5 ( 2 in binary): ET HOL Gated -Latch: Preventing Illegal tate of Latch Add logic to an - latch Create a more convenient interface, prevent = && = Two inputs: (data) and (write enable) When =, latch is set to value of = NOT(), = EET 5 HOL 5 ET etting the data we wish to store HOL Holding the data we set in the last phase = && = o = 7

8 What to do about the illegal inputs in latch can we make the latch simpler? Page Place an input at, set = What happens to output set =, set input at What happens to output We have a latch simplest way to store a bit If Write Enable = then input is stored IF write enable =, previous value remains in storage Gated -Latch: Preventing Illegal tate of Latch Add logic to an - latch Create a more convenient interface, prevent = && = Two inputs: (data) and (write enable) When =, latch is set to value of = NOT(), = When =, latch continues to hold previous value = = (hold condition for latch) Extra logic does not allow =, = case to occur was held from last state no longer follows, when = -Latch Timing iagram The diagram below is called a Timing iagram Our -Latch is previous-state dependent We can think of this as a time dependency Moving to the right on diagram, represents forward moving time The inputs & outputs to our -Latch are on left Inputs/Outputs can be either HIGH (logic ) or LOW (logic ) Think of this as a time-dependent truth table -Latch Timing iagram When the signal is high the latch is said to be open and the output signal,, follows the input signal,. As in any combinational circuit there will be a small delay between the time that the input changes and the time that the output follows suit. When latch is OPEN (=): Notice, follows Logic level = Logic level = open open time time 8

9 -Latch Timing iagram When the signal is low the latch is closed and the output signal, retains its value. When latch is CLOE (=): Notice, doesn t follow (Instead, has previous value) open closed time open -Latch Timing iagram etup / Hold Times The input signal should () be stable a certain amount of time before the signal is set to CLOE (=) This is referred to as the ETUP time In addition, the input signal () must be stable for a time after the is set to CLOE (=) This is referred to as HOL time Why? Time must be given for inputs to propagate through NAN gates! Gates are not instantaneous! Logic level = open Logic level = closed time open Next torage evices Ok we now have a device ( -Latch) that can store a bit Page 4 Use 4 latches Use this to build real storage devices. Temporary storage in a computer? Where are variables stored before being sent to the arithmetic unit for operations on them? egister Can we build an n-bit register using latches? What about main memory isk Later et input (from keypad) and set = What gets stored et =, try entering inputs 4-bit register 9

10 egister A register stores a multi-bit value. We use a collection of -latches, all controlled by a common. When =, n-bit value is written to register. Multi Bit -Latch A collection of -latches, controlled by a common When =, n-bit value is written to the outputs 2 2 ecall: A Basic Model of a Computer Address ata 2 PC -2 A, -2, $ A,, $ 2 UB $, $, $ 2-7 MPY $, $4, $5 8 4 A $, $5, $ 4 5 IV $, 5, $ Memory We know how to store m-bit number in a register How about many m-bit numbers? Bank of registers? How to fetch a specific m-bit number? addressing 5 9 Memory CPU Instructions Essential Part of Computer! Basic Components: Address: Looks up data Note: both are in binary

11 Memory Now that we know how to store bits, we can build a memory a logical k by m array of stored bits Address pace: number of locations (usually a power of 2) k = 2 n locations Addressability: number of bits per location (e.g., byte-addressable) m bits Memory Interface There are two basic operations on a memory electing one of the memory locations to read from electing one of the memory locations to write to Interface signals A n-bit address lines to select a location out Contents of selected location during read (m bits) in Value to be stored during write (m bits) If = write operation, =, read operation A in n m Memory (2 n by m-bit) m out Memory Looking from the outside, what do we need? Memory Looking from the outside, what do we need? A IN OUT

12 Memory A large number of addressable fixed size locations Address pace n bits allow the addressing of 2 n memory locations. Example: 24 bits can address 2 24 = 6,777,26 locations (i.e. 6M locations). If each location holds byte (= 8 bits) then the memory is 6MB. If each location holds one word (2 bits = 4 bytes) then it is 64 MB. Memory Addressability Computers are either byte or word addressable - i.e. each memory location holds either 8 bits ( byte), or a full standard word for that computer (6 bits for the LC-, more typically 2 bits, though now many machines use 64 bit words). Normally, a whole word is written and read at a time: If the computer is word addressable, this is simply a single address location. If the computer is byte addressable, and uses a multi-byte word, then the word address is conventionally either that of its most significant byte (big endian machines) or of its least significant byte (little endian machines). Memory Given address, fetch contents at that address elect or enable one of many locations Page 6 If we want output to come from one of many locations Multiplexer Control lines to Multiplexer = Address A IN OUT How about writing into one of many locations Enable one out of many locations ecoder Control lines to ecoder = Address 2

13 2 2 by -bit memory ead operation A 2 elects address to read ecall : The ecoder n inputs, 2 n outputs ONLY one AN gate outputs a for each possible input pattern But how do we select/enable ONE of the -latches? Given 2 bit address, elect ONE latch 2 2 or 4 registers 2 MUX out 2-bit decoder Think of it like this: put a binary # on AB, turns on the corresponding output wire! Ex: AB=, rd wire turns high, all the other are low 2 2 by -bit memory Write operation A 2 in 2 2 by -bit memory - Multiple Ports Independent ead/write 2 A W Limitation: You can only read or write at any given time ecoder 2 MUX out A W 2 You can read from one address and write to another with this arrangement (notice address line for address line for W) ecoder 2 MUX

14 2 2 by -bit memory - Multiple ead Ports 2 A 2 A 2 W A W ead from 2 locations At once, Write to a third! (notice address lines) (We will use this later In something called the: register file for the CPU) 2 ecoder 2 2 An Efficient 2 2 by -bit Memory - ingle Port address write enable latch (not flip-flop) address decoder word select output bits word input bits mux What is different? -latch Makes this memory writeable when clock is HIGH, More Memory etails This is still not the way actual memory is implemented eal memory: fewer transistors, denser, relies on analog properties But the logical structure is similar Address decoder Word select line, word write enable Bit line Two basic kinds of AM (andom Access Memory) tatic AM (AM) - 6 transistors per bit Fast, maintains data as long as power applied ynamic AM (AM) - transistor per bit enser but slower, relies on capacitance to store data, needs constant refreshing of data to hold charge on capacitor Also, non-volatile memories: OM, POM, flash, ynamic AM Information stored as charge on capacitors. Capacitors leak so values have to be refreshed continually As memory chips get larger, access times tend to increase. The processor spends more time waiting for data. This is a major issue limiting computer systems performance 4

15 Example Intel Core i5 Processor Clock rates approx 2.5GHz, Clock period approx.4 ns PC2-5 O-IMM 2 GB Memory Can deliver at most 64-bit word every.5 ns Mismatch between processor speed and memory speed Memory Hierarchy Modern computers try to mitigate memory delays by exploiting locality of reference through caches. maller, faster memory stores are placed closer to the CPU and bulk transfers from slower memory are used CPU Cache Memories Main Memory torage in MegaBytes, access times single clock cycles torage in GigaBytes, access time s of clock cycles isks Magnetic, Flash etc. torage in TeraBytes, access time s of clock cycles Memory Hierarchy Will return to this at the end of the course.! Are we ready to design sequential circuits and finite state machines? Is something missing? When do states change in a machine? o we let states change at arbitrary times? What do you think happens in a computer? 5

16 Clocked Flip-Flops/Circuits ubsystem in a computer consists of a large number of combinational and sequential devices Each sequential device is like latch which is in one of two states As machine executes its cycle, the states of all sequential devices change with time To control large collection of devices in an orderly (synchronized) fashion, machine maintains a clock equires all devices to change their states at the same time Clock generates sequence of pulses Clock Page 7 Input to latch can be written only when clock is high Much easier to design, debug, implement, and test How do we change latches so that they allow change in state synchronized with the clock? equential logic circuits require a means by which events can be sequenced..clock! Attaching Clock to -Latch Let s attach CLOCK to the on -Latch clock We create windows of time that we can store data into latch When the CLOCK is HIGH -latch is open When the CLOCK is LOW -latch is closed We have to prepare what we wish to store, right before latch closes open closed open CLOCK time Introducing - The Clock! A clock controls when stored values are updated Electrical waveform sends pulses through a circuit Oscillating global signal with fixed period One Cycle time The clock will act as the heartbeat of our system The number of cycles per second is the clock frequency measured in cycles per second or Hertz (Hz) The clock period refers to the duration of one clock cycle. The period and frequency are inversely related. Typical clock frequency: 2.5GHz = 2.5 x 9 Hz o corresponding clock period = /(2.5 x 9 ) =.4x -9 sec That would be:.4 nanoseconds 6

17 Let s Try to Build a Counter using the -Latch clock -bit -latch What is a counter? Counter increments value by at each cycle of clock Example: time =, counter = time =, counter = time = 2, counter =... time = 7, counter = + imple 2-bit Counter count from to 2 bit encoding A,B of states:,,, Counts functions: A,B current state A*, B* next state A* = (A B) + (A B ) = A XO B B* = (A B ) + (AB ) = B A B A* B* Let s Try to Build a Counter using the -Latch clock -bit -latch We can t use a -latch to build a counter Why not? Let s say at time=, -latch has: >This is the input to incrementer, so output = >Now is input to the -latch Problem: >We can t guarantee the clock will be low in time to store this new value into the -latch + Flip-Flop (or master-slave flip-flop) Flip-Flop is a pair of latches tupid name, but it stuck Isolates next state from current state Latch # inter 2 Latch #2 Clock Two phases: Clock = : =: Latch # closed, 2 =: Latch #2 open Clock = : =: Latch # open, 2 =: Latch #2 closed 7

18 Flip-Flop timing iagram Latch # inter Latch #2 Flip-Flop vs. -Latch We refer to the flip flop as an edge-triggered device. = ONLY when changes from to Clock inter 2 L -closed L -open L 2 -open L 2 -closed Clock L -closed L -open L 2 -open L 2 -closed This differs from latch, which is: level-triggered = anytime equals Timing iagram for FF: -7-7 Flip-Flop vs. -Latch We refer to the flip flop as an edge-triggered device. = ONLY when changes from to This differs from latch, which is: level-triggered = anytime equals Timing iagram for -Latch: Flip-Flop We can think of the Flip-Flop as a bit storage container with an input,, and an output,. The flip-flop takes a clock input (often denoted with a triangle) A set of flip-flops can be grouped together with common Clock and inputs to form a register. A key component in our processor Flip-Flop Clock 8

19 torage evices Latch tores Bit, Level-Triggered - forbidden input: =, = -Holds ata when = Working Counter Use a clocked register (made of flip-flops) Clock -ff + -Latch tores Bit, Level-Triggered -No forbidden inputs (fixes Latch) -= when = -Holds ata when = FF CLK -Flip-Flop tores Bit, Edge-Triggered -No forbidden inputs -= when (CLK) transitions from to -Holds ata for = or = -Except when transitions from to Counter Timing iagram Incrementer (+) computes the next value of the state register Clock -ff + Finite tate Machine epresentation of Counter eset Bubbles represent all possible states for the machine (aka your flip-flop based circuit) Clock Arrows show movement from one state to the next Transitions occur at pulse of the clock 9

20 Truth Table epresentation of Counter Present tate Next tate 2 (t) (t) (t) 2 (t+) 2 (t+) (t+) Finite tate Machine The counter we designed is an example of a finite state machine. In general a Finite tate Machine consists of An n-bit register which stores the state of the machine A block of logic that computes the next state as a function of the current state and the inputs, if any A block of logic which computes the output based on the current state. Combinational Clock Logic Blocks Inputs Next tate Function tate egister Output Function Outputs One Last Thing Flip-Flop with Additional Write Enable From previous slides, we attached clock to of the -flip-flop Now, we add another line to the flip flop Just holds onto data already stored in FF Give it the ability to ignore the clock! Next. Procedure for designing equential circuits (to implement Finite tate Machine) torage evice to store state: flip flop Logic to implement next state: combinational gates/devices How to derive the logic: truth tables FF Clock Flip-Flop w/ Clock 2