100 Hz Chassis 28 CTV

Transcription

1 SERVICE MANUAL 100 Hz Chassis 28 CTV

2 Contents Technical Data Recommendation for service repairs Component description Scart pin descriptions Exploded views Specifications of the connector Block diagram Video - Board Circit Description Component Descriptions TDA4780 (RGB video processor) TDA4665 (Base band delay - line) TDA9143 (I 2 C-Bs Controlled) SAA4961 (Mltistandard Comb Filter) TDA4470B (Mltistandard video - IF and qasi parallel sand processing) TDA9151B (Programmable deflection controller) TDA8540 (4x4 video switch matrix) TDA8351 (DC-copled vertical deflection circit) TDA9875A (Digital TV sond processor) TDA2616 (2x12W Hi-Fi adio power) TDA4605 (Control IC for SMPS) TDA6111Q (Video otpt amplifier) M27C2001 (2 megabit UV eprom) ST24C16 (Serial 16K eeprom) SAA7710 (Dolby Pro Logic Srrond) SAA7053A (Stereo BTL adio otpt) SDA5250 (Microcontroller nit) Oscilloscope signals

3 TECHNICAL DATA CRT PANEL Visible Pictre Deflection Angle Vertical Freqency Horizontal Freqency 66 cm 110 o 100Hz Hz ELECTRONIC Program Nmber Teletext Tner TV System Msic Power 100+2AV +SVHS 8 pages fast text (Top text optional) PLL Eropean CCIR system 2x8Watt Rms 10% distortion CONNECTIONS Ero AV Socket SVHS Inclde Inclde MAIN STAGE Mains Voltage Mains Freqency Power Consmption In Stby Mode VAC 50Hz 145W 2W

4 RECOMMENDATION FOR SERVICE REPAIRS 1- Use only original spare parts. Only se components with the same specifications for replacement. 2- Original fse vale only shold be sed. 3- Main leads and connecting leads shold be checked for external damage before connection. Check the inslation. 4- Parts contribting to the safety of the prodct mst not be damaged or obviosly nsitable. This is valid especially for inslators and inslating parts. 5- Thermally loaded solder pads are to be scked off and re-soldered. 6- Ensre that the ventilation slots are not obstrcted. 7- Potentials as high as 31 KV are present when this receiver is operating. Operation of the receiver otside the cabinet or with back cover removed involve a shock hazard from the receiver. Servicing shold not be attempted by anyone who is not thoroghly familiar with the precations necessary when working on high voltage eqipment. Perfectly discharge the high potential of the pictre tbe before handling the tbe. The pictre tbe is highly evacated and if broken. Glass fragments will be violently expelled. Always discharge the pictre tbe anode to the receiver chassis to keep of the shock hazard before removing the anode cap. 8- Keep wire away from the high voltage or high temperatre components. 9- When replacing a wattage resistor in circit board, keep the resistor 10 mm away from circit board. 10) Discharging of the pictre tbe is effected only by the connection point of the aqadaq coating the pictre tbe. 11) When carrying ot repairing process at control nit do not approach too near to the pictre tbe in order to avoid any charge transfer. 12) Measrements within the primary circit of the switched mode power spply are allowed to be carried ot only when sing potential-free measring eqipment. Voltages indicated for this circit are based on mains voltage reference level. 13) The defined local radiation dosage according to the x-ray radiation reglation is given by the specific type of the pictre tbe and the maximm permissible EHT voltage. The EHT voltage mst not exceed the maximm vale of 31kv. 14) When the repair process is carried ot 12 V line voltage shold not be interrpted becase video otpt stage is endangered by the interrption of 12 V line voltage. HANDLING OF MOS CHIP COMPONENTS MOS circit reqires special attention with regard to static charges. Static charges may occr with any highly inslating plastics and can be transferred to persons wearing clothes and shoes made of synthetic materials. Protective circits on the inpts and otpts of mos circits give protection to a limited extend only de to time of reaction. Please observe the following instrctions to protect the components against damage from static charges. 1- Keep mos components in condctive package ntil they are sed. Most components mst never be stored in styropor materials or plastic magazines. 2- Persons have to rid themselves of electrostatic charges by toching MOS components. 3- Hold the component by the body toching the terminals. 4- Use only gronded instrments for testing and processing prposes. 5- Remove or connect MOS ICs when operating voltage is disconnected.

5 X-RAY RADIATION PRECAUTION 1- Excessive high voltage can be prodce potentially hazardos X-RAY radiation. To avoid sch hazard, the high voltage mst not be above the specified limit. The vale of the high voltage of this receiver is 30KV at zero beam crrent (minimm brightness) nder 220V AC power sorce. The high voltage mst not nder any circmstance, exceed 31.5KV. It is recommended the reading of the high voltage be recorded as a part of the service record. It is important to se an accrate and reliable high voltage meter. 2- The primary sorce of X-RAY radiation in this TV receiver is the pictre tbe. For contined X- RAY radiation protection, the replacement tbe mst be exactly the same type tbe as specified in the part list. SOLDERING PROCESS 1) SMD Components (Srface Monted Device) Desoldering: Heat p the component from its terminals for 2 or 3 seconds with a soldering iron and afterwards take ot the component careflly by means of the tweezers. Remove sperflos solder at the solder srfaces of the components place at pcb by means of desoldering strand or sction de-solder eqipment. Never force the component for removing withot heating the terminals sfficiently. Unsoldered components shold not be sed for once more. Soldering: Place the component properly to its position by means of tweezers and solder one side of the component. Then check ot the position of the component and be sre if it is soldered to the right place and then solder other side of the component. Terminals of the SMD components mst not contact directly to the soldering iron. 2)PLCC Components Desoldering: Heat p the terminals of PLCC component for 3 or 5 seconds by means of SMD soldering iron and PLCC desoldering pair (angle 90 0 C, Leg: 24mm). Take ot PLCC component careflly by slightly trning of desoldering tweezers. Soldering: Remove sperflos solder at the solder srfaces of the components placed on pcb by means of de-soldering iron or sction de-solder eqipment. Apply flx with low grease content. Place PLCC device on the soldering srface and take care for its correct placement. Secre diagonally by means of two soldering joints. Apply soldering paste along PLCC pins. Short circits which may occre dring soldering process have to be removed immediately with a soldering iron.

6

7 SPECIFICATIONS OF THE CONNECTOR (EURO SCART) I- Adio otpt 1. right channel 0.5 VRMS/<1 k 0 2- Adio inpt 1. right channel 0.5 VRMS (connected to No.6) 3- Adio otpt 2. left channel 0.5 VRMS (connected to No.1) 4- GND (adio) 5- GND 6- Adio inpt 2. left channel 0.5 VRMS/>10k 0 7- RGB inpt, ble (B) 8- Switch signal video (stats) 9- GND 10- Reserved for clock signals (not connected) 11- RGB inpt, green (G) 12- Reserved for remote control (not connected) 13- GND 14- GND switch signal RGB 15- RGB inpt, red (R) 16- Switch signal RGB 17- GND (video) 18- GND 19- Video otpt 1 Vpp/75 ohm 20- Video inpt 1 Vpp/75 ohm 21- Shield

8 BLOCK DIAGRAM

9 VIDEO BOARD

10 CIRCUIT DESCRIPTION 1- MAIN SUPPLY UNIT A-General Description In order to obtain 2W power at standby mode, two separate circits are sed. One for standby power spply and another for switched-mode power spply. The standby spply nit consists of a psh-pll converter (Q803 and Q804) prodcing the reqired 5V operating voltage by fll wave rectification. This voltage is stabilised by means of D807 and D808. This voltage rns the µp (SDA 5250) and IR receiver. When the standby nit is operating, the nder-crrent relay is plled p and capacitor C806 which acts as a capacitive series resistor becomes parallel to C807 providing an additional crrent flow. To assre the EMC this mains voltage is filtered by mltiple choking the feed lines. Dring standby state the main switched-mode power spply and the degassing coil are flly disabled by nder-crrent relay. Switching back into the operating state is enabled by the starting-p voltage coming from µp (1701). The main switched-mode power spply nit inclding a fly back converter controlled by an optoelectronic copler consists the driving IC TDA and the switching transistor BUZ91. The following operating voltages are delivered by the transformer of the switched-mode power spply after their rectification. 145Vdc 33VDC +16Vdc +12Vdc : +B Line is a direct otpt voltage. : +F Delivered from 145vdc : +H Horizontal driver voltage. : +I Derived from +H Spply of the CRT board and the protection circit. +8Vdc : +C Delivered from +I. Spply of the deflection processor, switched matrix, RGB decoder etc. +5Vdc : +D (digital 5v). Spply of the digital part of featre box, µp, DSP (digital sond processor) etc. +5Vdc : +A Spply of the analog part of featre box, µp, DSP (digital sond processor) headphone amplifier etc. B-Pin Descriptions of the TDA PIN 1 Control inpt signal by comparing the control voltage across control winding 7-9 (SMPS) with an internal reference voltage, the width of the otpt plse at pin 5 of the secondary load and the existing mains voltage are matched with each other. The control of the SMPS at pin1 achieved as follows: R102 as a part of control voltage driver (R102, R103 and R104) is variably bypassed by means of the transistor resistance of the opto-copler which depends on the respective horizontal voltage. PIN2 Terminal for primary crrent rise simlation, where an RC network is connected. The voltage rise at pin 2 (sawtooth voltage cased by the charging of C106 throgh R106 and fast discharging throgh pin 2) simlates the crrent rise in the primary winding of the SMPS transformer when the transistor is condcting. When the voltage level reaches the level that is derived from the control voltage at pin 1, the otpt terminal is set to the grond level terminating the condctivity of Q101. The correct definition of the RC network elements will reslt a maximm power at the overload. PIN3 : PIN4 PIN5 PIN6 PIN7 PIN8 Primary voltage detector I101, compares the otpt voltage at pin3 of the TDA which is divided by R106 and R107, with an internal reference voltage and disables the SMPS in case of nder voltage (mains approx. 150VAc). If this voltage is greater than the threshold vale compensation controlled by pin 2 occrs. :GND Switching plse otpt, provide control plses for switching of Q101. This pin provides an otpt of +/-1A. Spply voltage pin. A stable internal reference voltage as well as the switching threshold for the spply voltage detector are derived from the spply voltage. When the system is switched on the crrent that is needed is spported throgh R125 by the transformer winding 7-9. Soft start terminal where C104 is connected. The short plses becase of this capacitor will case the starting-p to be softly. Zero crossing detector-in the transient state voltage cases a positive otpt plse to emerge at pin 5 at every zero transition of the feedback voltage (falling edge).

11 C-Starting Voltage After switching on the receiver with the mains btton, approximately 320V is present on the charging capacitor C109. Throgh the resistor R125 the spply voltage of I101 (pin 6) rises to 12 V. Also 5 Vstby spply from the standby power the spply stage is present. D-Power Spply The power spply for the receiver employs a freernning switched mode power spply stage with a switching freqency of 35KHz at maximm and I90KHz at minimm load and with a maximm power of 200W. For this reason, a Power Field Effect Transistor is reqired for the high voltage transistor Q101. The I101 is responsible for driving the MOS power transistor Q101 and also for all control and monitoring fnctions in the power spply. At Standby mode, the switched mode power spply circit is switched off. The power consmption is approximately 2W. In this mode, only the µp stage and tning modle is fed with +5Vstby from the standby power transformer. E-Operation At pin 2 of I101, a saw tooth signal is present and this has a lower reversal point at approx. 1,1V and an pper reversal point at 2,2V. This saw tooth signal is compared by a comparator with the inpt crrent at pin1. If the saw tooth signal exceeds the level at pin1, the comparator switches off the high voltage transistor Q101. In order to switch on the transistor again, there mst be a zero-cross over signal at pin8. This pin is connected to the transformer winding 2/4 to identify the zero cross-over. F-The Control If the transformer is overloaded, all voltages redce. For controlling the voltage drop, diode D101 is sed. Like the voltages when the transformer is loaded, also the voltage on diode D101 decreases reslting a decreased inpt crrent of I101-(pin 1). In this case the condction time of the transistor Q101 increases. As the operating spply for the line otpt stage effects the line width, it is necessary for the +B voltage (operating spply for the line otpt stage) to be stable. Rising in +B cases the voltage of the optocopler I102 to decrease. The LED in the optocopler becomes brighter and the internal transistor between pins 4 and 5 becomes less resistive. This cases the voltage of I101-(pin1) to increase and the condcting time of the high voltage transistor compared with the sawtooth on pin 2 shorter. As a reslt the +B spply redces. G-Overcrrent Protection The Ics (I101) internal circit monitors the driving plses of the switching transistor Q101 by means of the voltage the sawtooth signal at pin 2 of I1O1. The saw tooth voltage on I101 -(pin2), spplies the monitoring of the driving plses to the switching transistor Q101. If too mch crrent flows throgh the Power- MOS transistor dring an over-load of the power spply, the I101 atomatically switches the power spply off. 2- CONTROL UNIT: A-General Description The infra-red receiver decodes the infra-red bi-phase signals for µp I701, the master processor. Also the IRprocessor can switch the power spply on or off. The master processor is responsible for the control of the whole system of TV receiver. The set-p data and the settings are stored in the EEPROM I703 and the system control programme is stored in the EPROM I702. The control and command fnctions are carried ot by the 8bit microcontroller SDA5250 co-operating with the EEPROM I703 and EPROM I702. Since the microcontroller itself does not inclde a ROM space, the reqired operating system will be obtained by sing an external EPROM I702. External EP- ROM contains the specific software program which corresponds to the system of the TV set. The power spply of the microcontroller is realised by the standby power spply nit (50mA). The low active reset pin 28 is kept as low level for at least 10ms by means of trigger circit Q701 and Q702 when the mains voltage is applied by switching on the TV set. 18 MHz qartz device X701 acts as a clock generator. Q708, Q709, Q710 and Q711 act as a bffer for spporting all of the IIC BUS ICs. Q704, Q705, Q706 and Q707 are bffer transistors for OSD. B- Service and Special Fnctions Using RC (Remote control) A) When the EPROM I702 is ot of work and shold be changed, the service technician shold order a new EPROM according to the version nmber which is written on the IC. EPROM incldes the system software (BIOS) for TV.

12 B) When the EEPROM I703 is ot of work and shold be changed, the service technician shold follow the below steps in order to spply the necessary adjstments. Men inclding the deflection and color data can be loaded via remote controller. Factory Set Vales: M btton at RC Move the crsor to Service linc with P+/- btton This fnction provides the ser fast programming withot sing the mens. This fnction is especially for the prodction line at the factory. Move the crsor to this line Press OK TV will atomatically switch to the *** line. If the TV is switched off and switch on again it will atomatically switch from the Atomatic Search Mode. Dring the prodction process at the factory setting this fnction is the last step before the packing of the set, so the ser can have the Atomatic Program Search very qickly for the very first time. (See the related section at the User Manal) Press OK btton *** Enter code nmber to the line for athorized dealer as 089 The service men will appear as follows: Factory Set Vales Geometry Video Tner Parameters V-Shift E/W Amplitde E/W- Shape E/W- Tilt : steps:0-7 : steps:0-63 : steps:0-63 : steps:0-7 Yo shold store these set vales by moving the crsor to the memorize line. Video: This fnction provides the operator at the factory or the service technician to adjst the White Balance parameters. Red Gain : Red adjstment at max. Beam crrent Green Gain : Green adjstment at max. Beam crrent Ble Gain Red Level : Ble adjstment at max. Beam crrent : Red adjstment at min. Beam crrent Green Level : Green adjstment at min. Beam crrent Ble Level Peak White Grid 2 Adj : Ble adjstment at min. Beam crrent : It is for the screen adjst ment : This adjstment is sed at the factory dring the prodction. Yo shold store these set vales by moving the crsor to the memorize line. Tner Parameters : These vales are fixed vales and shold not be changed. EHT Compensation: 17 AGC Adjst :This vale shold be kept as it is, nless the EEPROM is changed. Otherwise it shold be adjsted ntil not having a snowy pictre. Geometry : This fnction provides the service technician to adjst the geometry parameters very qickly in any repair process. These parameters and their step ranges are as follows. H-Shift : steps:0-63 H-Amplitde S-Correction V-Amplitde : steps:0-63 : steps:0-63 : steps:0-63

13 C) Featre Box Featre Box is completely shielded as it is the most important and sensitive part of 100 Hz Chassis. The YUV signals which are for 50Hz are converted to 100Hz signals by means of sampling and scanning twice of each sampled signal. Inside of the featre box there are Analog-to-Digital converter, Clock Synchronisation Generator, Memory Synchronisation Generator, Digital-to-Analog Converter and Seqential Access Memory. The inpt signals to the Featre Box are Horizontal Sync, Vertical Sync, CVBS and YUV signals, SDA, SCL and LLC as well as 5V spply and grond. Analog YUV signals are converted to the digital signals at ADC by means of the synchronisation plses from SDA9257 which ses analog CVBS signal for providing the necessary sync plses. The ADC conversion are processed at SDA9205. SDA9220 is responsible for driving the SDA9254 (TV- Seqential Access Memory) and generating sync signals. Together with the other devices of the Featre Box it enhances pictre qality. SDA9254 is a combination of the TV seqential access memory and an adaptive filter which is sed to enhance noisy inpt signals. SDA9280 is a Display Processor which accepts for different data inpt formats. These are IIC, Y, B-Y, R-Y. The inpt data are digital bt the otpt are analog. This IC is the last step at the featre box. 3- DEFLECTION UNIT The programmable deflection processor TDA9151B provides the driving plses reqired for driving the horizontal and vertical otpt stages operating according to the 100Hz deflection principle. Apart from these, the above mentioned processor is also sed for controlling the east-west circit, carrying ot a switch-off fnction (protection circit) and providing the sper sand castle plse (SSC100) for the video signal amplifier. This processor is controlled via an I 2 C BUS and receives the synchronisation plses from the IPQ- BOX (as well as LLC-signal (line locked signal)). PIN 1: Horizontal Flyback Inpt Inpt pin for retrace plses having an amplitde of 100Vpp by means of capacitive divider C208/C209. The retrace plse is needed for the phase control of the driving plse and the SSC plse. PIN 2: Display Sper Sand Castle Inpt /Otpt From this terminal a doble-level SC plse is provided. The first level i.e. 2.5V is for horizontal and vertical blanking where as the second level i.e. 4,5V is sed for video clamping. Frther more at pin2 the vertical deflection process is monitored. That means, in case of missing vertical plses from I202( pin8), pin2 will be locked to 2,5V and the video channel will be controlled to black level. PIN 6: EAST-WEST GEOMETRY OUTPUT Otpt for east-west geometry provides the adjstment of horizontal deflection amplitde, pictre width, parabolic east-west correction, east-west pin cshion correction and also parabolic correction of trapezim distortions. PIN 7: EHT COMPENSATION EHT compensation pin is an inpt for keeping the pictre size constant althogh the vale of EHT voltage changes (delivered from aqadac coating of the pictre tbe). ***The EHT voltage transformer provides following voltages: EHT voltage 30KVDc. Focsing and G2 voltage. Filament voltage for pictre tbe. +17Vdc +40Vdc +220Vdc. In order to be able to adjst the horizontal amplitde of the pictre (pictre width) and the raster correction independently from the EHT voltage, the line otpt stage is connected to a diode modlator. One branch of the bridge consists of C211 and C212, another one consists of deflection coil, linearity coil, C213, and the bridge coil L207. At the diagonal branch C215 is placed where as part of the trace capacitance it simltaneosly contribtes to the internal pincshion correction. The control circit of the EAST-WEST correction is connected via L204. PIN 8: Pin8 is designed to determine the reference crrent for the complete vertical deflection crrent. PIN 9: Pin 9 is for flash over protection and is not sed at this chassis, PIN 10: This pin represents the otpt terminal for the vertical synchronisation. Plse is the drive inpt of the differential amplifier stage belonging to the vertical otpt. PIN 11: At this IC via I 2 CBUS, it is possible to adjst the following vales: Amplitde of vertical deflection signal 80%, tangential correction from 0 to 16%, vertical shift centering in 7 steps from - 1,5% to +1,5% and 16/9 change-over. Pin 12: VA Inpt The vertical synchronisation inpt coming from the Featre Box PIN 13: HA Inpt Horizontal synchronisation inpt coming from the Featre Box. PIN 14: LLC Inpt This signal is for the line and vertical oscillator. Withot LLC signal (27MHz) this IC can not operate.

14 COMPONENT DESCRIPTIONS 1) TDA4780 2) TDA4665 3) TDA9143 4) SAA4961 5) TDA4470 6) TDA9151 7) TDA8540 8) TDA8351 9) TDA9875-A 10) TDA ) TDA ) TDA6111Q 13) M27C ) ST24C16 15) SAA ) TDA7053 A 17) SDA5250

15 TDA4780 RGB Video Processor with Atomatic Ct-off control and Gamma Adjst GENERAL DESCRIPTION The TDA4780 is a monolithic integrated circit with a lminance and a color difference interface for video processing in TV receivers. Its primary fnction is to process the lminance and color difference signals from a color decoder which is eqipped e.g. with the mltistandard decoder TDA4655 or TDA9160 pls delayline TDA4661 or TDA4665 and the Pictre Signal Improvement (PSI) IC TDA467X or from a featre modle. Two sets of analog RGB color signals can also inserted, e.g. one from a peritelevision connector (SCART plg) and the other one from an On-Screen Display (OSD) generator. The TDA4780 has I 2 C-bs control of all parameters and fnctions with atomatic ct-off control of the pictre tbe cathode crrents. It provides RGB otpt signals for the video otpt stages. In clamped otpt mode it can also be sed as an RGB sorce. The reqired inpt signals are: Lminance and negative color difference signals 2 or 3-level sandcastle plse for internal timing plse generation I 2 C-bs data and clock signals. FEATURES Gamma adjst Dynamic black control (adaptive black) All inpt signals clamped on black-levels Atomatic ct-off control, alternative: otpt clamping on fixed levels Three adjstable reference voltage levels via I 2 C- bs for atomatic ct-off control Lminance/color difference interface Two lminance inpt levels allowed Two RGB interfaces controlled by either fast switches or by I 2 C-bs Two peak drive limiters, selection via I 2 C-bs Ble stretch, selection via I 2 C-bs Lminance otpt for scan velocity modlation (SCAVEM) Extra lminance otpt; same pin can be sed as he control otpt e.g. for the TDA4650 and TDA4655 Non standard operations like 50 Hz/32 khz are also possible Either 2 or 3 level sandcastle plse applicable High bandwidth for 32 khz application White point adjsts via I 2 C-bs Average beam crrent and improved peak drive limiting Two switch-on delays to prevent discoloration dring start-p All fnctions and featres programmable via I 2 C- bs PAL/SECAM or NTSC matrix selection. FSW 2 U 1 28 SCL R 2 G 2 B 2 V P -(B - Y) -(R - Y) SDA YHUE C R R 0 C G G 0 Y 8 21 G B GND 9 20 B O R CI G C PDST B C L FSW C PDL SC BCL Pin Connections

16 PINNING SYMBOL PIN DESCRIPTION FSW 2 1 fast switch 2 inpt R 2 2 red inpt 2 G 2 3 green inpt 2 B 2 4 ble inpt 2 V p 5 spply voltage (B - Y) 6 color difference inpt (B - Y) (R - Y) 7 color difference inpt (R - Y) Y 8 lminance inpt GND 9 grond R 1 10 red inpt 1 G 1 11 green inpt 1 B 1 12 ble inpt 1 FSW 1 13 fast switch 1 inpt SC 14 sandcastle plse inpt BCL 15 average beam crrent limiting inpt C PDL 16 storage capacitor for peak limiting CL 17 storage capacitor for leakage crrent compensation C PDST 18 storage capacitor for peak dark CI 19 ct-off measrement inpt B 0 20 ble otpt C B 21 ble ct-off storage capacitor G 0 22 green otpt C G 23 green ct-off storage capacitor R 0 24 red otpt C R 25 red ct-off storage capacitor YHUE 26 Y-otpt/he adjst otpt SDA 27 I 2 C-bs serial data inpt/acknowledge otpt SCL 28 I 2 C-bs serial clock inpt QUICK REFERENCE DATA SYMBOL PARAMETER Min. Typ. Max. Unit V P spply voltage (pin5) V I P spply crrent (pin5) ma V 8(p-p) lminance inpt (peak-to-peak vale) (C)VBS / V V 6(p-p) (B - Y) inpt (peak-to-peak vale) V V 7(p-p) (R - Y) inpt (peak-to-peak vale) V V 14 three-level sandcastle plse H+V V H V BK V two-level sandcastle plse H+V V BK V V i RGB inpt signals at pins 2,3,4,10,11 and 12(black-to-white vale) V V o(p-p) RGB otpt at pins 24, 22 and 20(black-to-white vale) V T amb operating ambient temperatre o C

17 Block diagram

18 FUNCTIONAL DESCRIPTION Signal inpt stages The TDA4780 contains 3 sets of inpt signal stages for: 1.Lminance/color-difference signals: a) Y: 0.45 V (p-p) VBS or 1.43 V (p-p) VBS, selectable via I2C-bs. b) -(R - Y): 1.05 V (p-p). c) -(B - Y): 1.33 V (p-p). The capacitively copled signals are matrixed to RGB signals by either a PAL/SECAM or NTSC matrix (selected via I 2 C-bs). 2.(RGB) 1 signals (0.7 V (p-p) VB), capaci tively copled (e.g. from external sor ce). 3.(RGB) 2 signals (0.7 V (p-p) VB), capaci tively copled (e.g. videotext, OSD). All inpt signals are clamped in order to have the same black levels at the signal switch inpt. Displayed signals mst be synchronos with the sandcastle plse. Signal switches Both fast signal switches can be operated by switching pins (e.g. SCART facilities) or set via the I 2 C-bs. With the pin FSW 1 the Y-CD signals or the (RGB) 1 signals can be selected, with pin FSW 2 the above selected signals or the (RGB) 2 signals are enabled. Dring the vertical and horizontal blanking time an artificial black level eqal to the clamped black level is inserted in order to clip off the sync plse of the lminance signal and to sppress hm dring the ct-off measrement time and eliminate noise dring these intervals. Satration, contrast and brightness adjst Satration, contrast and brightness adjsts are controlled via the I 2 C-bs and act on Y, CD as well as on RGB inpt signals. Gamma acts on the lminance content of the inpt signals. Gamma adjst The gamma adjst stage has a non-linear transmission characteristic according to the formla y = x gamma, where x represents the inpt and y the otpt signal. If gamma is smaller than nity, the lower parts of the signal are amplified with higher gain. Atomatic ct-off control Dring leakage measrement time the leakage crrent is compensated in order to get a reference voltage at the ct-off measrement info pin. This compensation vale is stored in an external capacitor. Dring ct-off crrent measrement times for the R, G and B channels, the voltage at this pin is compared with the reference voltage, which is individally adjstable via I 2 C-bs for each color channel. The control voltages that are derived in this way are stored in the external feedback capacitors. Shift stages add these voltages to the corresponding otpt signals. The atomatic ct-off control may be disabled via the I 2 C-bs. In this mode the otpt voltage is clamped to 2.5 V. Clamping periods are the same as the ct-off measrement periods. Adaptive black (ADBL) The adaptive black stage detects the lowest voltage of the lminance component of the internal RGB signals dring the scanning time and shifts it to the nominal black level. In order to keep the nominal white level the contrast is increased simltaneosly. Ble stretch (BLST) The ble stretch channel gets additional amplification if the ble signal is greater than 80% of the nominal signal amplitde. In the event the white point is shifted towards higher color temperatre so that white parts of a pictre seem to be brighter. Measrement plse and blanking stage Dring the vertical and horizontal blanking time and the measrement period the signals are blanked to an ltra black level, so the leakage crrent of the pictre tbe can be measred and atomatically compensated for. Dring the ct-off measrement lines (one line period for each R, G or B) the otpt signal levels are at ct-off measrement level. The vertical blanking period is timed by the sandcastle plse. The measrement plses (leakage, R, G and B) are triggered by the negative going edge of the vertical plse of the sandcastle plse and start after the following horizontal plse. The IC is prepared for 2f H (32 khz) application. Otpt amplifier and white adjst potentiometer The RGB signals are amplified to nominal 2 V (p-p), the DC-levels are shifted according to ct-off control.

19 The nominal signal amplitde can be varied by ±50% by the white point adjstment via the I 2 C-bs (individally for RGB respect). Signal limiting The TDA4780 provides two kinds of signal limiting. First, an average beam limiting, that redces signal level if a certain average is exceeded. Second, a peak drive limiting, that is activated if one of the RGB signals even shortly exceeds a via I 2 C-bs adjsted threshold. The latter can be either referred to the ct-off measrement level of the otpts or to grond. When signal limiting occrs, contrast is redced, and at minimm contrast brightness is redced additionally. Sandcastle decoder and timer A 3-level detector separates the sandcastle plse into combined line and field plses, line plses, and clamping plses. The timer contains a line conter and controls the ct-off control measrement. Application with a 2-level 5 V sandcastle plse is possible. Switch on delay circit After switch on all signals are blanked and a warm p test plse is fed to the otpts dring the ct-off measrement lines. If the voltage at the ct-off measrement inpt exceeds an internal level the ct-off control is enabled bt the signal remains still blanked. In the event of otpt clamping, the ct-off control is disabled and the switch on procedre will be skipped. Y otpt and he adjst The TDA4780 contains a D/A converter for he adjst. The analog information can be fed, e.g. to the mltistandard decoder TDA4650 or TDA4655. This otpt pin may be switched to a Y otpt signal, which can be sed for scan velocity modlation (SCAVEM). The Y otpt is the Y inpt signal or the matrixed (RGB) inpt signal according to the switch position of the fast switch. I 2 C-bs The TDA4780 contains an I 2 C-bs receiver for control fnction. ESD protection The Pins are provided with protection diodes against grond and spply voltage (see Chapter "internal pin configrations"). I 2 C-bs inpt pins do not shnt the I 2 C-bs signals in the event of missing spply voltage. EMC The pins are protected against electromagnetic radiation.

20 TDA4665 Baseband Delay Line GENERAL DESCRIPTION The TDA4665 is an integrated baseband delay line circit with one line delay.. It is sitable for decoders with color-difference signal otpts ±(R-Y) and ±(B-Y) FEATURES The comb filters, sing the switched-capacitor techniqe, for one line delay time (64 µs) Adjstment-free application No crosstalk between SECAM color carriers (diaphoty) Handles negative or positive color-difference inpt signals Clamping of AC-copled inpt signals ±(R-Y) and ±(B-Y)) VCO withot external components 3 MHz internal clock signal derived from a 6MHz CCO, line-locked by the sandcastle plse (64 µs line) Sample - and - hold circits and low-pass filters to sppress the 3 MHz clock signal Addition of delayed and non-delayed otpt signals Otpt bffer amplifiers Comb filtering fnctions for NTSC color-difference signals to sppress cross-color) PINNING SYMBOL PIN DESCRIPTION V P2 1 +5V spply voltage for digital part n.c. 2 not connected GND2 3 grond for digital part (0V) i.c. 4 internally connected SAND 5 sandcastle plse inpt n.c. 6 not connected i.c. 7 internally connected i.c. 8 internally connected V P1 9 +5V spply voltage for analog part GND1 10 grond for analog part (0V) V 0(R-Y) 11 ±(R Y) otpt signal V 0(B-Y) 12 ±(B Y) otpt signal n.c. 13 not connected V i(b-y) 14 ±(B Y) inpt signal n.c. 15 not connected V i(r-y) 16 ±(R Y) inpt signal V P2 U 1 16 V i(r-y) n.c. GND 2 i.c. SAND n.c. i.c. i.c TDA n.c. V i(b-y) n.c. V 0(B-Y) V 0(R-Y) GND V P1 Pin configration

21 QUICK REFERENCE DATA SYMBOL PARAMETER Min. Typ. Max. Unit V P1 analog spply voltage (pin9) V V P2 digital spply voltage (pin1) V I P(tot) total spply crrent ma V i(p-p) ±(R - Y) inpt signal PAL/NTSC(peak-to-peak vale; pin 16) mv ±(B - Y) inpt signal PAL/NTSC(peak-to-peak vale; pin 14) mv ±(R - Y) inpt signal SECAM (peak-to-peak vale; pin 16) V ±(B - Y) inpt signal SECAM (peak-to-peak vale; pin 14) V G v gain V o /V i of color-difference otpt signals V 11 / V 16 for PAL and NTSC db V 12 / V 14 for PAL and NTSC db V 11 / V 16 for SECAM db V 12 / V 14 for SECAM db Block diagram ±(R-Y) color-difference inpt signals ±(B-Y) V P1 sandcastle plse inpt SIGNAL CLAMPING SIGNAL CLAMPING analog spply SANDCASTLE DETECTOR pre-amplifiers FREQUENCY PHASE DETECTOR LINE MEMORY LINE MEMORY DIVIDER BY 192 SAMPLE AND-HOLD SAMPLE AND-HOLD 3 MHz shifting clock LP LP 11 addition otpt stages bffers 12 2 TDA ±(R-Y) color-difference inpt signals ±(B-Y) n.c. n.c. n.c. n.c. LP 6 MHz CCO DIVIDER BY 2 7 i.c. 10 digital spply 1 3 4,8 GND1 V P2 GND2 LIMITING VALUES In accordance with the Absolte Maximm Rating System (IEC 134). Grond pins 3 and 10 connected together. SYMBOL PARAMETER Min. Max. Unit V P1 analog spply voltage (pin9) V V P2 digital spply voltage (pin1) V V 5 voltage on pin V P V V n voltage on pins 11, 12, 14 and V P V T stg storage temperatre o C T amb operating ambient temperatre 0 70 o C V ESD electrostatic handling for all pins; - ±500 V

22 CHARACTERISTICS SYMBOL PARAMETER CONDITIONS Min. Typ. Max. Unit Spply V P1 analog spply voltage (pin9) V V P2 digital spply voltage (pin1) V I P1 analog spply crrent ma I P2 digital spply crrent ma Color-difference inpt signals V i(p-p) inpt signal (peak-to-peak vale) ±(R - Y) PAL and NTSC (pin 16) mv ±(B - Y) PAL and NTSC (pin 14) mv ±(R - Y) SECAM (pin 16) V ±(B - Y) SECAM (pin 14) V V i(max)(p-p) maximm symmetrical inpt signal (peak-to-peak vale) ±(R - Y) or ±(B - Y) for PAL and NTSC before clipping V ±(R - Y) or ±(B - Y) for SECAM before clipping 2 - V R 14, 16 inpt resistance dring clamping kω C 14, 16 inpt capacitance pf V 14, 16 inpt clamping voltage proportional to Vp V Color-difference otpt signals V o(p-p) otpt signal (peak-to-peak vale) ±(R - Y) on pin 11 all standards V ±(B - Y) on pin 12 all standards V V 11, V 12 ratio of otpt amplitdes at eqal inpt signals V i(14,16)(p-p) = 1.33 V db V 11, 12 DC otpt voltage proportional to Vp V R 11, 12 otpt resistance Ω G v gain for PAL and NTSC ratio V 0 /V i db gain for SECAM ratio V 0 /V i db V 0/ V 0+1 ratio of delayed to non-delayed otpt V i(14,16)(p-p) = 1.33 V; db signals (pins 11 and 12) SECAM signals V n(rms) noise voltage (RMS vale pins 11 and 12) V i(14,16) = 0 V; note mv V (11, 12)(p-p) nwanted signals (line - locked) V i(14,16) = 0 V; active (peak-to-peak vale) video; Rs = 300 Ω meander mv spikes mv S/N(W) weighed signal-to-noise ratio (pins 11 and 12) V 0(p-p) = 1 V db t d time difference between non-delayed and µs delayed otpt signals (pins 11 and 12) t d delay of non-delayed signals ns t tr transient time of delayed signal on pins ns transient of ns respectively 12 SECAM signal transient time of non-delayed signal on pins ns transient of ns respectively 12 SECAM signal Color-diff f BK brst-key freqency/sandcastle freqency khz V t5 top plse voltage V p V V slice internal slicing level V V V I 5 inpt crrent µa C 5 inpt capacitance pf

23 TDA9143 I 2 C-BUS controlled, alignment-free PAL/NTSC/SECAM Decoder / Sync Processor GENERAL DESCRIPTION The TDA9143 is an 1 2 C-bs controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor with blanking facilities for PALpls and EDTV-2 signals. The TDA9143 has been designed for se with baseband chrominance delay lines, and has a combined sbcarrier freqency/comb filter enable signal for commnication with a PAL/NTSC comb filter. The IC can process both CVBS inpt signals and Y/C inpt signals. The inpt signal is available on an otpt pin, in the event of a Y/C signal, it is added into a CVBS signal. The sync processor provides a two-level sandcastle, a horizontal plse (CLP or HA plse, bs selectable) and a vertical (VA) plse. When the HA plse is selected, a line-locked clock (LLC) signal is available at the otpt port pin (6.75 MHz or MHz). A fast switch can select either the internal Y signal with the UV inpt signals, or YUV signals made of the RGB inpt signals. The RGB inpt signals can be clamped with either the internal or an external clamping signal. Two pins with an inpt/otpt port and an otpt port of the I 2 C-bs are available. The I 2 C-bs address of the TDA9143 is hardware programmable. FEATURES Mlti-standard color decoder and sync processor for PAL, NTSC and SECAM PALpls helper blanking and EDTV-2 blanking I 2 C-bs controlled I 2 C-bs addresses hardware selectable Pin compatible with TDA9141 Alignment free Few external components Designed for se with baseband delay lines Integrated video filters Adjstable lminance delay Noise detector with I 2 C-bs read-ot Norm/no norm detector with I2C-bs read-ot CVBS or Y/C inpt, with atomatic detection possibility CVBS otpt, provided I 2 C-bs address 8A is sed Vertical divider system Two-level sandcastle signal VA synchronization plse (3-state) HA synchronization plse or clamping plse CLP inpt/otpt Line-locked clock otpt (6.75 MHz or MHz) or stand-alone I 2 C-bs otpt port Stand-alone I 2 C-bs inpt/otpt port Color matrix and fast YUV switch Comb filter enable inpt/otpt with sbcarrier freqency Internal bypass mode of external delay line for NTSC applications Low power standby mode with 3-state YUV otpts Fast blanking detector with I 2 C-bs read-ot Blanked or nblanked sync on Y ot by I 2 C-bs bit BSY Internal MACROVISION gating for the horizontal PLL enabled by bs bit EMG.

24 PINNING SYMBOL PIN DESCRIPTION -(R-Y) 1 otpt signal for -(R Y) -(B-Y) 2 otpt signal for -(B-Y) U in 3 chrominance U inpt V in 4 chrominance V inpt SCL 5 serial clock inpt SDA 6 serial data inpt/otpt V cc 7 positive spply voltage DEC 8 digital spply decopling DGND 9 digital grond SC 10 sandcastle otpt VA 11 vertical acqisition synchronization plse Y ot 12 lminance otpt V ot 13 chrominance V otpt U ot 14 chrominance U otpt I/O PORT 15 inpt/otpt port OPORT/LLC 16 otpt port/line-locked clock otpt CLP/HA 17 clamping plse/ha synchronization plse inpt/otpt F 18 fast switch select inpt B 19 BLUE inpt G 20 GREEN inpt R 21 RED inpt ADDR(CVBS) 22 I 2 C-bs address inpt (CVBS otpt) Fscomb 23 comb filter stats inpt/otpt HPLL 24 horizontal PLL filter C 25 chrominance inpt Y/CVBS 26 lminance/cvbs inpt AGND 27 analog grond FILT ref 28 filter reference decopling CPLL 29 color PLL filter XTAL 30 reference crystal inpt XTAL2 31 second crystal inpt SEC ref 32 SECAM reference decopling -(R-Y) -(B-Y) U in V in SCL SDA V cc DEC DGND SC VA Y ot V ot U ot I/O PORT OPORT/LLC U TDA Pin Configration SEC ref XTAL2 XTAL CPLL FILT ref AGND Y/CVBS C HPLL Fscomb ADDR(CVBS) R G B F CLP/HA

25 QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS Min. Typ. Max. Unit V CC positive spply voltage V I CC spply crrent ma V CVBS(p-p) CVBS inpt voltage (peak-to-peak vale) top sync-white V V Y(p-p) lminance inpt voltage (peak-to-peak vale) top sync-whit V V C(p-p) chrominance brst inpt voltage V (peak-to-peak vale) V Y(ot) lminance black-white otpt voltage V V U(ot)(p-p) U otpt voltage (peak-to-peak vale) standard color bar V V V(ot)(p-p) V otpt voltage (peak-to-peak vale) standard color bar V V SC(bl) sandcastle blanking voltage level V V SC(clamp) sandcastle clamping voltage level V V VA(bl) VA otpt voltage V V HA(bl) HA otpt voltage V V LLC(p-p) LLC otpt voltage amplitde mv (peak-to-peak vale) V R, G, B(p-p) RGB inpt voltage (peak-to-peak vale) 0 to 100% satration V V clamp(i/o) clamping plse inpt(otpt voltage V V sb(p-p) sbcarrier otpt voltage amplitde mv (peak-to-peak vale) V OPORT port otpt voltage V FUNCTIONAL DESCRIPTION The TDA9143 is an I 2 C-bs controlled, alignment-free PAL/NTSC/SECAM color decoder/sync processor which has been designed for se with baseband chrominance delay lines. For PALpls and EDTV-2 (60 Hz) signals blanking facilities are inclded. In the standard operating mode the I 2 C-bs address is 8A. If the address inpt is connected to the positive spply rail the address will change to 8E. Inpt switch CAUTION The voltage on the chrominance pin mst never exceed 5.5 V. If it does, the IC enters a testmode. The TDA9143 has a two pin inpt for CVBS or Y/C signals which can be selected via the I 2 C-bs. The inpt selector also has a position in which it atomatically detects whether a CVBS or Y/C signal is on the inpt. In this inpt selector position, standard identification first takes place on an added Y/CVBS and C inpt signal. After that, both chrominance signal inpt amplitdes are checked once and the inpt with the strongest chrominance brst signal is selected. The inpt switch stats is read ot by the I 2 C-bs via otpt bit YC. The ato inpt detector indicates YC = 1 for a VBS inpt signal (no chrominance component). CVBS otpt In the standard operating mode with I 2 C-bs address 8A, a CVBS otpt signal is available on the address pin, which represents either the CVBS inpt signal or the Y/C inpt signal, added into a CVBS signal. RGB color matrix CAUTION The voltage on the Ui, pin mst never exceed 5.5 V. If it does, the IC enters a test mode. The TDA9143 has a color matrix to convert RGB inpt signals into YUV signals. A fast switch, controlled by the signal on pin F and enabled by I2C-bs via EFS (enable fast switch), can select between these YUV signals and the YUV signals of the decoder. Mode FRGB = 1 (forced RGB) overrles EFS and switches the matrixed RGB inpts to the YUV otpts. The Y signal is internally connected to the switch. The -(R-Y) and -(B-Y) otpt signals of the decoder first have to be delayed in external baseband chrominance delay lines. The otpts of the delay lines mst be connected to the UV inpt pins. If the RGB signals are not synchronos with the selected decoder inpt signal, clamping of the RGB inpt signals is possible by I 2 C-bs selection of ECL (external RGB clamp mode) and by feeding an external clamping signal to the CLP pin. Also in external RGB clamp mode the VA otpt will

26 be in a high impedance OFF-state. The YUV otpts can be pt in 3-state mode by bs bit LPS (low power standby mode). Standard identification The standards which the TDA9143 can decode depend pon the choice of external crystals. If a 4.4 MHz and a 3.6 MHz crystal are sed then SECAM, PAL 4.4/3.6 and NTSC 4.4/3.6 can be decoded. If two 3.6 MHz crystals are sed then only PAL 3.6 and NTSC 3.6 can be decoded. Which 3.6 MHz standards can be decoded depends pon the exact freqencies of the 3.6 MHz crystals. In an application where not all standards are reqired only one crystal is sfficient; in this instance the crystal mst be connected to the reference crystal inpt (pin 30). If a 4.4 MHz crystal is sed it mst always be connected to the reference crystal inpt. Both crystals are sed to provide a reference for the filters and the horizontal PLL, however, only the reference crystal is sed to provide a reference for the SECAM demodlator. To enable the calibrating circits to be adjsted exactly, two bits from I 2 C-bs sbaddress 00 are sed to indicate which crystals are connected to the IC. The standard identification circit is a digital circit withot external components. The decoder (via the I 2 C-bs) can be forced to decode either SECAM or PAL/NTSC (bt not PAL or NTSC). Crystal selection can also be forced. Information concerning standard and which crystal is selected and whether the color killer is ON or OFF is provided by the read ot. Using the forced-mode does not affect the search loop, it does however prevent the decoder from reaching or staying in an nwanted state. The identification circit skips impossible standards (e.g. SECAM when no 4.4 MHz crystal is fitted) and illegal standards (e.g. in forced mode). To redce the risk of wrong identification, PAL has priority over SECAM. Only line identification is sed for SECAM. For a vertical freqency of 60 Hz, SECAM can be blocked to prevent wrong identification by means of bs bit SAF. Integrated filters All chrominance bandpass and notch filters, inclding the lminance delay line, are an integral part of the IC. The filters are gyrator-capacitor type filters. The resonant freqency of the filters is controlled by a circit that ses the active crystal to tne the SECAM Cloche filter dring the vertical flyback time. The remaining filters and the lminance delay line are matched to this filter. The filters can be switched to either 4.43 MHz, 4.29 MHz or 3.58 MHz. The switching is controlled by the standard identification circit. The lminance notch sed for SECAM has a lower Q-factor than the notch sed for PAL/NTSC. The notches are provided with a little preshoot to obtain a symmetrical step response. In Y/C mode the chrominance notch filters are bypassed, to preserve fll signal bandwidth. For a CVBS signal the chrominance notch filters can be bypassed by bs selection of bit TB (trap bypass). The delay of the color difference signals -(R-Y) and -(B-Y) in the chrominance signal path and the external chrominance delay lines when sed, can be fitted to the lminance signal by I 2 C-bs in 40 ns steps. The typical lminance delay can be calclated: delay 90 + SAK. SBK { (FRQTB)} + 160(YD3) + 160(YD2) + 80(YD1) + 40(YD0) [ns]. Color decoder The PAL/NTSC demodlator employs an oscillator that can operate with either crystal (3.6 MHz or 4.4 MHz). If the I 2 C-bs indicates that only one crystal is connected, it will always connect to the crystal on the reference crystal inpt (pin 30). The He signal which is adjstable by I 2 C-bs, is gated dring the brst for NTSC signals. The SECAM demodlator is an ato-calibrating pll demodlator which has two references. The reference crystal, to force the PLL to the desired free-rnning freqency and the bandgap reference, to obtain the correct absolte vale of the otpt signal. The VCO of the PLL is calibrated dring each vertical blanking period, when the IC is in search mode or in SECAM mode. If the reference crystal is not 4.4 MHz the decoder will not prodce the correct SECAM signals. Especially for NTSC applications an internal bypass mode of the external baseband delay line (for instance TDA4665) is added, controlled by bs bit BPS (bypass mode) and with a gain of 2. The bypass mode is not available for SECAM. Comb filter interfacing The freqency of the active crystal is fed to the Fscomb otpt, which can be connected to an external comb filter IC (e.g. SAA4961). When bs bit ECMB is LOW, the sbcarrier freqency is sppressed and its DC vale is LOW. With ECMB HIGH, the DC vale is HIGH with the sbcarrier freqency present, and I 2 C- bs otpt bit YC and the inpt switch are always forced in the Y/C mode, nless an external crrent sink (e.g. from the comb filter) prevents this, as pin Fscomb also acts as inpt pin. In this event the sbcarrier freqency is still present on the same DC HIGH level. PALpls and EDTV-2 helper blanking For blanking of PALpls or EDTV-2 helper lines, the helper blanking can extend the vertical blanking of the Y, R-Y and B-Y otpts. Additional helper blanking bits (HOB, HBC) and norm/not norm (NRM) indication determine whether the helper signal has to be blanked or conditionally blanked depending on the signal-tonoise ratio bit SNR. Table 1 is valid in a 50 Hz or 60 Hz mode.

27 Helper blanking modes HOB HBC SNR HELPER BLANKING 0 X X OFF 1 O X ON OFF ON For PALpls (50 Hz, 625 lines) otside the letter box area blanking is possible and takes place on lines 275 to 371 and 587 to 59. For EDTV-2 (system M, 60 Hz, 525 lines) otside the letter box area blanking is possible and takes place on lines 230 to 312 and 493 to 49 Provided a NORM sync condition is present, with bs bit HBO = 1 and HBC = 0 blanking is activated. Conditional blanking is possible with HBO = 1 and HBC = 1 and SNR = 1. The black level of the lminance signal is internally clamped with a large time constant to an internal reference black level. This black level is sed as fill-in vale for the Y signal dring blanking. Fast blanking detector To detect the presence of a fast blanking signal, a circit is added which indicates this event if in more than one line per field a blanking plse is present at the fast blanking inpt (F). More than one line per field is chosen to prevent switching-off at every spike detected on the fast blanking inpt. The detector otpt FBA (fast blanking active) can be read-ot by the I 2 C-bs. Blanked/nblanked sync By means of the I2C-bs bit BSY (blanked sync) otpt signal Yot will be presented with or withot its composite sync part. At BSY = 0 the composite sync is present on Yot When activated, helper blanking takes place only dring helper lines scan. At BSY = 1 the black level is filled in dring the line blanking interval and vertical blanking interval. When activated, the helper blanking extends the vertical blanking. Sync processor (ϕ 1 loop) The main part of the sync circit is an oscillator rnning at 440 x f H (6.875 MHz), provided that I 2 C-bs address 8A is sed or 432 x fh (6.75 MHz) for 8E. Its freqency is divided by 440 or 432 to lock the ϕ 1 loop to the incoming signal. The time-constant of the loop can be selected by the I 2 C-bs (fast, ato or slow). In the fast mode the fast time-constant is chosen independent of signal conditions. In the ato mode the medim time-constant is present with a fast time constant dring the vertical retrace period ( field boost ). If the noise detector indicates a noisy video signal the time-constant switches to slow with a smaller field boost, which is also the time-constant for the slow mode. In case of a slow time constant sync gating takes place in a 6 µs window arond the separated sync plse. In case of no sync lock, both the ato and the slow mode have a medim time constant, to ensre reliable catching. The noise content of the video signal is determined by a noise detector circit. This circit measres the noise at top sync dring a 15 line period every field (65 lines after start VA plse). When the noise level spersedes the detector threshold in two consective fields, noise is indicated and bs bit SNR is set. The free-rnning freqency of the oscillator is determined by a digital control circit that is locked to the active crystal. When a power-on-reset plse is detected the freqency of the oscillator is switched to a freqency of abot 10 MHz (23 khz horizontal freqency) to protect the horizontal otpt transistor. The oscillator freqency is calibrated to MHz or 6.75 MHz after receiving data on sbaddress 01 for the first time after power-on-reset detection. To ensre that this procedre does not fail it is absoltely necessary to send sbaddress 00 before sbaddress 01. Sbaddress 00 contains the crystal indication bits and when sbaddress 01 is received the line oscillator calibration will be initiated (for the start-p procedre after power-on-reset detection, see the I 2 C- bs protocol). The calibration is terminated when the oscillator freqency reaches MHz or 6.75 MHz. The ϕ 1 loop can be opened sing the I 2 C-bs. This is to facilitate On Screen Display (OSD) information. If there is no inpt signal or a very noisy inpt signal, the ϕ 1 loop can be opened to provide a stable line freqency, and ths astable pictre. The sync part also delivers a two-level sandcastle signal, which provides a combined horizontal and vertical blanking signal and a clamping plse for the display section of the TV. MACROVISION sync gating A dedicated gating signal for the separated sync plses, starting 11 lines after the detection of a vertical sync plse ntil pictre scan starts, can be sed to improve the behavior of the horizontal PLL with respect to the nwanted distrbances cased by the psedo-sync plses in video signals with MACROVISI- ON anti-copy gard signals. This sync gating excldes the psedo-sync plses and can only take place in the ato and fast ϕ 1 time constant mode, provided I 2 C-bs bit SNR = 0 and I 2 C-bs bit EMG = 1. I 2 C-bs bit EMG = 1 enables and EMG = 0 disables this sync gating in the horizontal PLL. Vertical divider system The vertical divider system has a flly integrated vertical sync separator. The divider can accommodate both 50 Hz and 60 Hz systems; it can either determine the field freqency atomatically or it can be forced to the desired system via the I 2 C-bs. A block diagram of the vertical divider system is illstrated in the following figre.

28 The divider system operates at twice the horizontal freqency. The line conter receives enable plses at this freqency, thereby conting two plses per line. A state diagram of the controller is shown in Fig.5. Becase it is symmetrical only the right-hand part will be described. LINE COUNTER CONTROLLER NORM COUNTER TIMING GENERATOR Block diagram of the vertical divider system. Depending on the previosly fond vertical freqency, the controller will be in one of the COUNT states. When the line conter has conted 488 plses (i.e. 244 lines of the video inpt signal), the controller will move to the next state depending on the otpt of the norm conter. This can be either NORM, NEAR_NORM or NO_NORM, depending on the position of the vertical sync plse in the previos fields. When the controller is in the NORM state it generates the vertical sync plse (VSP) atomatically and then, when the line conter is at LC = 626, moves to the WAIT state. In this condition it waits for the next plse of the doble line freqency signal, and then moves to the COUNT state of the crrent field freqency. When the controller retrns to the COUNT state, the line conter will be reset half a line after the start of the vertical sync plse of the video inpt signal. The NORM window normally looks within one line width and a sdden half line delay of the vertical sync plse change can therefore be neglected. When the controller is in the NEAR_NORM state it will move to the COUNT state if it detects the vertical sync plse within the NEAR-NORM window (i.e. 622 < LC < 628). If no vertical sync plse is detected the controller will move back to the COUNT state when the line conter reaches LC = 628. The line conter will then be reset. When the controller is in the NO_NORM state, it will move to the COUNT state when it detects a vertical sync plse and reset the line conter. If a vertical sync plse is not detected before LC = 722 (if the ϕ 1 loop is locked in forced mode) it will move to the COUNT state and reset the line conter. If the ϕ 1 loop is not locked the controller will retrn to the COUNT state when LC = 628. The forced mode option keeps the controller in either the left-hand side (60 Hz) or the right-hand side (50 Hz) of the state diagram. Figre 6 illstrates the state diagram of the norm conter which is an p/down conter that increases its conter vale by 1 if it finds a vertical sync plse within the selected window. If not, it decreases the conter vale by 1 (or 2, see Fig.6). In the NEAR_NORM and NORM states the first correct vertical sync plse after one or more incorrect vertical sync plses is processed as an incorrect plse. This procedre prevents the system from staying in the NEAR - NORM or NORM state if the vertical sync plse is correct in the first field and incorrect in the second field. In case of no sync lock (SLN = 1) the norm conter is reset to NO_NORM (wide search window), for fast vertical catching when switching between video sorces. Fast switching between different channels however can still reslt in a continos horizontal sync lock sitation, when the channel is changed before the norm conter has reached the NORM state. To provide faster vertical catching in this case, measres have been taken to prevent the norm conter to cont down to zero before reaching the NO_NORM state. Bs bit FWW (forced wide window) enables the norm conter to stay in the NO_NORM state if desired. The norm/no_norm stats is read ot by bs bit NRM. Otpt port and in/otpt port Two stand-alone ports are available for external se. These ports are I2C-bs controlled, the otpt port by bs bit OPB and the inpt/otpt port by bs bit OPA. Bs bit OPA is an open-drain otpt, to enable inpt port fnctionality. The pin stats is read ot by bs via otpt bit IP. Sandcastle Figre 7 illstrates the timing of the acqisition sandcastle (ASC) and the VA plse with respect to the inpt signal. The sandcastle signal is according to the two-level 5 V sandcastle format. An external vertical gard crrent can overrle the sink crrent to enable blanking prposes.

29 SAA4961 Mltistandard Comb Filter The one-chip Mltistandard Comb Filter In TV signal processing a comb filter is sed to separate the chrominance and the lminance signals from the CVBS signal withot effects sch as cross-lminance and cross-color. The comb filter SAA 4961/V2 shown in figre 3 ses two 2H delay lines together with an adaptive logical comb filter algorithm for processing the PAL standard. In case of NTSC processing two 1H delay lines are sed. Effects like hanging dots or residal cross-color, seen when sing a classical comb filter algorithm, are not prodced. The switched capacitor delay lines prodce three otpt signals 0H, 2H and 4H (NTSC: 0H, 1H, 2H). To prevent alias components reslting from the discrete time signal processing, a low-pass pre-filter is integrated in ront. Together with the transversal band-pass filters, the logical comb filter eliminates the lminance components (in the chrominance freqency band) from the chrominance signal. To eliminate cross-lminance the comb filtered chrominance is now sbtracted from the time compensated CVBS signal and converted by the post filtering to the continos time domain. Signal switches for an external SVHS signal or non-delayed CVBS signals are available. They can be controlled externally via BYP (pin 3) and SSYN (pin 6). Internal clock generation only reqires a sbcarrier signal (fsc or 2 x fsc). Sync separation (SYNC) is inclded for the generation of control signals for the delay lines. Pin names and shord description SYMBOL PIN DESCRIPTION FSC 1 sbcarrier freqency inpt I.C. 2 internal connected BYP 3 BYPASS mode forcing I.C. 4 internal connected REFBP 5 decopling capacitor for bandpass reference SSYN 6 BYPASS definition inpt V cc 7 analog spply voltage V CCO 8 analog otpt spply voltage AGND 9 analog grond (signal reference) CEXT 10 external chrominance inpt OGND 11 analog otpt bffer grond COUT 12 chrominance otpt signal FSCSW 13 fsc reference selection Y ot 14 lminance otpt signal CVBSO 15 ncombed CVBS otpt signal I.C. 16 internal connected YEXT/CVBS 17 CVBS inpt signal LPFION 18 disable alias filter CSY 19 storage capacitor GSYS1 20 standard select 1 DGND 21 digital grond VDD 22 digital spply voltage SYS2 23 standard select 2 REFDL 24 decopling capacitor for delay lines COMBENA 25 COMB mode otpt signal PLLGND 26 analog PLL grond VCCPLL 27 analog PLL spply voltage I.C. 28 internal connected

30 Package type:dip 28 FSC 1 U 28 I.C. I.C VCCPLL BYP 3 26 PLLGND I.C COMBENA REFBP 5 24 REFDL SSYN 6 23 SYS2 VCC VCCO AGND CEXT OGND COUT FSCSW YOUT 7 SAA 4961/V VDD DGND SYS1 CSY LPFION YEXT/CVBS I.C. CVBSO Pinning SAA4961/V2 LPF SWITCHED CAPACITOR DELAY LINES Yext/ CVBS 0H 2H 4H BPH BPH BPH BYP SSYN FSC ADAPTIVE LOGICAL CIRCUIT FOR THE CHROMINANCE SIGNAL CVBSO Clock BPF LPF SYS2 SYS1 V H SYNC -1 ADD Clock LPF Yot Cext LPF Cdt

31 FUNCTIONAL DESCRIPTION The Video Processing The combing path for lminance and chrominance The CVBS signal is fed by a copling capacitor to the video inpt pin 17 (YEXT/CVBS) and is internally clamped. From there it goes to an inpt anti-aliasing lowpass filter. A selector switch, externally controlled by pin 18 (LPFION) allows to switch the inpt filter on and off. From there the video signal is taken to the delay line section of the chip. Here the signal is sampled and seqential stored in a memory of capacitors. The three otpt signals of this circit have a delay of 0H, 2H and 4H for PAL signals (NTSC: 0H, 1H and 2H). These three very accrate in time matched signals are bandpass filtered and then fed to a logical comb filter. Here the comb filter action takes place by adding the 0H and 2H (NTSC: 0H and 1H) signals and by adding at the same way the 2H and 4H (NISC: 1H and 2H) signal, this to free the chrominance signals from nwanted (in band) lminance components. In the same block a decision logic circit makes the selection which chrominance signal shold be taken to the otpt. This is done to prevent hanging dots, or wrong vertical color transients. The otpt signal of the comb filter block is bandpass filtered and fed to the addition stage. Here the 2H (NTSC: 1H) delayed and time eqalized CVBS signal and the comb filtered chrominance signal are added. By this addition the chrominance signal in the lminance channel is cancelled, withot inflencing the high freqency lminance components. By post-filtering the lminance and the chrominance otpt signal paths, the discrete time signals are converted back to the analog time domain and by an otpt bffer fed to YOUT (pin14) for the lminance and COUT (pin12). for the chrominance signal. The bypass signal path for non PAL/NTSC signals and Y/C mode (SVHS) In case the signal is not a PAL or NTSC CVBS signal (for instance SECAM signal) and so not sitable for being combed, the comb filter fnction is bypassed. In that mode the CVBS inpt signal is directly switched to the YOUT bffer (pin 14). The chrominance inpt pin CEXT (pin 10) is then switched to the otpt bffer of COUT (pin 12). These paths are also sed for SVHS signals, or other Y/C signal sorces, where lminance and chrominance signals are already separately available. Switching from combing to bypass is controlled by the bypass signal BYP (pin 3) and bypass definition signal SSYN (pin 6). The teletext path (TXT) It is very important, that the pictre on the pictre tbe is not shifted if the comb filter is switched on or off. There- fore it is recommended to se the Yot path as TV synchronisation sorce. For TXT signals however the Yot path cannot be sed in case of COM B-ON, becase the TXT signals are distorted by the comb action. The CVBS signal, available at pin 15 (CVBSO), can be sed for TXT concepts which are only sing a edced nmber of lines at the end of the vertical blanking interval. If the TXT concept is able to se all lines in the vertical interval only the CVBS signal at the inpt pin 17 can be sed. Clock processing The delay lines of the SAA4961/V2 are designed for a clock freqency of 3x Fsb. The internal clock freqency is locked to the reference freqency Fsc at pin 1. This reference freqency may be Fsb or 2x Fsb and shold be derived from the color decoder. Sync processing A correct fnction or the comb filter is only possible if the control signals for the delay lines are synchronised with the horizontal and vertical freqency of the processed signal. These H and V signals are derived from the sync signal of the incoming CVBS signal (pin 17) via a sync separation circit. This sync separator circit reqires an external capacitor at pin 19.

32 TDA4470B Mltistandard Video-If and Qasi Parallel Sand Processing DESCRIPTION FEATURES 5 V spply voltage, low power consmption Active carrier generation by FPLL principle (freqency-phase-locked-loop) for tre synchronos demodlation Very linear video demodlation, good plse response and excellent intermodlation figres VCO circit is operating on pictre carrier freqency, the VCO freqency is switchable for the L` mode Alignment free AFC withot external reference circit, polarity of the AFC crve is switchable VIF AGC for negative modlated signals (peak sync. detection) and for positive modlation (peak white/black level detector) The TDA4470B is an integrated bipolar circit for mltistandard video/sond IF (VIF/SIF) signal processing in TV/VCR and mltimed a applications. The circit processes all TV video IF signals with negative modlation (e.g., B/G standard), positive modlation (e.g., L standard) and the AM, FM/NICAM sond IF signals. Tner AGC with adjstable take over point Alignment free qasi parallel sond (QPS) mixer for FM/NICAM sond IF signals Intercarrier otpt signals is gain controlled (necessary for digital sond processing) Complete alignment-free AM demodlator with gain controlled AF otpt Separate SIF-AGC with average detection Two independent SIF inpts Parallel operation of the AM demodlator and QPS mixer (for NICAM L stereo sond) Package and relevant pinning is compatible with the single standard version TDA4472, which simplifies the design of an niversal IF modle PINNING Pin Symbol Fnction 1, 2 V i,sif1 SIF1 inpt (symmetrical) 3 Vsw Inpt selector switch 4, 9,16 GND Grond 5 C AGC SIF-AGC (time constant) 6, 7 V i,vif VIF inpt (symmetrical) 8 C AGC VIF-AGC (time constant) 10 R top Take over point, tner AGC 11 I tn Tner AGC otpt crrent 12 V 0,vid Video otpt 13 V SW Standard switch 14 V SW L switch 15 C bi Black level capacitor 17 C ref Internal reference voltage 18 LF Loop filter 19 V SW AFC switch V VCO VCO circit 22 V AFC AFC otpt 23 V S Spply voltage 24 V 0-FM Intercarrier otpt 25 V 0-AM AF otpt - AM sond 26 R comp Offset compensation 27, 28 V i, SIF2 SIF2 inpt (symmetrical) Pin Description V i,sif1 V i,sif1 Vsw GND C AGC V i,vif1 V i,vif1 C AGC GND R top I tn V 0, vid. V SW V SW U TDA 4470B V i,sif2 V i,sif2 R comp V 0, AM V 0, AM V S V AFC V VCO V VCO V SW LF C ref GND C BL

33 Block Diagram for TDA4470-B Offset comp. (optional) Loop filter VCO L switch FPLL 0 O 90 O VCO + phase shift Control AFC AFC switch AFC 6 VIF amp. VIF 7 12 Video C AGC 8 15 AGC (VIF) Video det. Standard 13 Standard Switch C BL Tner TUNER AGC Spply V S Take over point FM det C Ref SIF 2 SIF inpt switch 28 3 SIF amp. Intercarrier (FM / NICAM) 1 SIF 1 2 AGC (SIF) 25 AF (AM) 5 AM det. 4, 9, 16 C AGC

34 CIRCUIT DESCRIPTION Vision IF Amplifier The video IF signal (VIF) is fed throgh a SAW filter to the differential inpt (Pin 6-7) of the VIF amplifier. This amplifier consists of three AC-copled amplifier stages. Each differential amplifier is gain controlled by the atomatic gain control (VIF-AGC). The otpt signal of the VIF amplifier is applied to the FPLL carrier generation and the video demodlator. Tner-and VIF-AGC At Pin 8, the VIF-AGC charges/discharges the AGC capacitor to generate a control voltage for setting the gain of the VIF amplifier and tner in order to keep the video otpt signal at a constant level. Therefore, in the case of all negative modlated signals (e.g., B/G standard) the sync. level of the demodlated video signal is the criterion for a fast charge/discharge of the AGC capacitor. For positive modlation (e.g., L standard) the peak white level of video signal controls the charge crrent. In order to redce reaction time for positive modlation, where a large time constant is needed, an additional black level detector controls the discharge crrent in the event of decreasing VIF inpt signal. The control voltage (AGC voltage at Pin 8) is transferred to an internal control signal, and is fed to the tner AGC to generate the tner AGC crrent at Pin 11 (open collector otpt). The take over point of the tner AGC can be adjsted at Pin 10 by a potentiometer or an external de voltage (from interface circit or microprocessor). FPLL,VCO and AFC The FPLL circit (freqency phase locked loop) consists of a freqency and phase detector to generate the control voltage for the VCO tning. In the locked mode, the VCO is controlled by the phase detector and in nlocked mode, the freqency detector is sperimposed. The VCO operates with an external resonance circit (L and C parallel) and is controlled by internal varicaps. The VCO control voltage is also converted to a crrent and represents the AFC otpt signal at Pin 22. At the AFC switch (Pin 19) three operating conditions of the AFC are possible: AFC crve rising or falling and AFC off. A practicable VCO alignment of the external coil is the adjstment to zero AFC otpt crrent at Pin 22. At center freqency the AFC otpt crrent is eqal to zero. Frthermore. at Pin 14. the VCO center freqency can be switched for setting to the reqired L vale (L standard). The optional potentiometer at Pin 26 allows an offset compensation of the VCO phase for improved sond qality (fine adjstment). Withot a potentiometer (open circit at Pin 26). this offset compensation is not active. The oscillator signal passes a phase shifter and spplies the in-phase signal (0 o ) and the qadratre signal (90 o )of the generated pictre carrier. Video Demodlation and Amplifier The video IF signal, which is applied from the gain controlled IF amplifier, is mltiplied with the inphase component of the VCO signal. The video demodlator is designed for low distortion and large bandwidth. The demodlator otpt signal passes an integrated low pass filter for attenation of the residal vision carrier and is fed to the video amplifier. The video amplifier is realized by an operational amplifier with internal feedback and 8 MHz bandwidth (-3 db). A standard dependent de level shift in this stage delivers the same sync. level for positive and negative modlation. An additional noise clipping is provided. The video signal is fed to VlF-AGC and to the video otpt bffer. This amplifier with a 6 db gain offers easy adaption of the sond trap. For nominal video

35 IF modlation the video otpt signal at Pin 12 is 2 V pp. Sond IF Amplifier and SIF-AGC The SIF amplifier is nearly identical with the 3-stage VIF amplifier. Only the first amplifier stage exists twice and is switchable by a control voltage at Pin 3. Therefore with a minimal external expense it is possible to switch between two different SAW filters. Both SIF inpts featres excellent cross-talk attenation and an inpt impedance which is independent from the switching condition. The SIF-AGC is related to the average level of AM- or FM-carrier and controls the SIF amplifier to provide a constant SIF signal to the AM demodlator and QPS mixer. AM Demodlator The alignment-free AM demodlator is realized by a synchronos detector. The modlated SIF signal from the SIF amplifier otpt is mltiplied in phase with the limited SIF signal (AM is removed). The AF signal of the demodlator otpt is fed to the otpt amplifier and to the SIF-AGC. For all TV standards with negative video modlation (eg., B/G standard). the AF otpt signal (Pin 25) is switched off by the standard switch. Qasi-Parallel-Sond (QPS) Mixer The QPS mixer i~ realized by a mltiplier. The signal (FM or NICAM carrier) is converted to the intercarrier freqency by the regenerated pictre carrier freqency by the regenerated pictre carrier (qadratre signal) which is provided from the VCO. The intercarrier signal is fed via an otpt amplifier to Pin 24. Standard Switch L Switch To have eqal polarity of the video otpt signal the polarity can be switched in the demodlation stage in accordance with the TV standard. Additional a standard dependent de level shift in the video amplifier delivers the same sync. level. In parallel to this, the correct VIF-AGC is selected for positive or negative modlated VIF signals. In the case of negative modlation (e.g., B/G standard) the AM otpt signal is switched off. For positive modlation (L standard) the AM demodlator and QPS mixer is active. This condition allows a parallel operation of the AM sond signal and the NICAM-L stereo sond. With a control voltage at Pin 14 the VCO freqency can be switched for setting to the reqired L vale (L standard). Also a fine adjstment of the L -VCO center freqency is possible via a potentiometer. The L switch is only active for positive modlated video IF-signals (standard switch in L mode). AFC Switch The AFC otpt signal at Pin 22 can be controlled by a switching voltage at Pin 19. It is possible to select an AFC otpt signal with a rising-or falling AFC crve and to switch off the AFC. VCR Mode For the VCR mode in a TV set (external video sorce selected), it is recommendable to switch off the IF circit. With an external switching voltage at Pin 6 or 7, the IF amplifiers are switched off and all signal otpt levels at Pins 12, 24, and 25 are according to the internal de voltage. Internal Voltage Stabilizer The internal bandgap reference ensres constant performance independent of spply voltage and temperatre.

36 TDA9151B Programmable Deflection Controller GENERAL DESCRIPTION The TDA9151B is a programmable deflection controller contained in a 20-pin DIP package and constrcted sing BIMOS technology. This high performance synchronization and DC deflection processor has been especially designed for se in both digital and analog based TV receivers and monitors, and serves horizontal and vertical deflection fnctions for all TV standards. The TDA9151B ses a line-locked clock at 6.75, 13.5 or 27 MHz, depending on the line freqency and application, and reqires only a few external components. The device can be programmed in a selfadaptive mode or in a programmable fixed slope mode. Selection of these modes and a large nmber of other fnctions is flly programmable via the I 2 C-bs. FEATURES General 6.75, 13.5 and 27 MHz clock freqency Few external components Synchronos logic I 2 C-bs controlled Easy interfacing Low power ESD protection Flash detection with restart Two-level sandcastle plse. Vertical deflection 16-bit precision vertical scan Self adaptive or programmable fixed slope mode DC copled deflection to prevent pictre bonce Programmable fixed compression to 75% Programmable vertical expansion in the fixed slope mode S-correction can be preset S-correction setting independent of the field freqency Differential otpt for high DC stability Crrent sorce otpts for high EMC immnity Programmable de-interlace phase. East-West correction DC copled EW correction to prevent pictre bonce 2nd and 4th order geometry correction can be preset Trapezim correction Geometry correction settings are independent of field freqency Self adaptive Blt generator prevents ringing of the horizontal deflection Crrent sorce otpt for high EMC immnity. Horizontal deflection Phase 2 loop with low litter Internal loop filter Dal slicer horizontal flyback inpt Soft start by I 2 C-bs Over voltage protection/detection with selection and stats bit. EHT correction Inpt selection between aqadag or EHT bleeder Internal filter.

37 GENERAL DESCRIPTION Positive spply off-centre shift otpt display sandcastle inpit/otpt horizontal information inpt vertical information inpt line - locked clock inpt line - locked clock select inpt flash detection inpt over voltage protecton inpt serial data inpt / atpt serial clock inpt HORIZONTAL AND VERTICAL DETECTOR DINT VAP PRESCALER PROTACT ON AND START CONTROL LFSS I 2 C INTERFACE H-RESET f CLK V-RESET HORIZONTAL COUNTER VERT CAL PLACE CONTROL GBS STSC MS SLOPE WS WAIT REFERENCE GENERATOR HORIZONTAL PLACE CONTROL CLP OF CS H-PHASE VERT CAL PLACE GENERATOR PRESCALER T D A B PHASE 2 LOOP VERT CAL GEOMETRY AMPL. S-CORR. V-SHIFT EAST - WEST GEOMETRY WIDTH PARA/WIDTH TRAPEZIUM CORNER/PARA SAMPLE - AND - HOLD FILTER FLASH BLDS EHT COMP horizontal flyback inpt horizontal otpt vertical otpt A vertical otpt A east - west geometry otpt EHT information external resistive conversion digital grond analog grond

38 PINNING Pin Description Pin Symbol Fnction 1 HFB horizontal flyback inpt 2 DSC display sandcastle inpt/otpt 3 PROT over voltage protection inpt 4 AGND analog grond 5 LLSC line-locked clock selection inpt 6 EWOUT east-west geometry otpt 7 EHT EHT compensation 8 R CONV external resistive conversion 9 FLASH flash detection inpt 10 VOUT B vertical otpt B 11 VOUT A vertical otpt A 12 V A vertical information inpt 13 H A horizontal information inpt 14 LLC line-locked clock inpt 15 DGND digital grond 16 V CC spply inpt (+8V) 17 SDA serial data inpt/otpt 18 SCL serial clock inpt 19 OFCS off-centre shift otpt 20 HOUT horizontal otpt HFB DSC PROT AGND LLSC EWOUT EHT R CONV FLASH VOUT B U TDA 9151B HOUT OFCS SCL SDA V CC DGND LLC H A V A VOUT A FUNCTIONAL DESCRIPTION Inpt signals (pins 12, 13, 14, 17 and 18) The TDA9151B reqires three signals for minimm operation (apart from the spply). These signals are the line-locked clock (LLC) and the two I 2 C-bs signals (SDA and SCL). Withot the LLC the device will not operate becase the internal synchronos logic ses the LLC as the system clock. I 2 C-bs transmissions are reqired to enable the device to perform its reqired tasks. Once started the IC will se the HA and/or VA inpts for synchronization. If the LLC is not present the otpts will be switched off and all operations discarded (if the LLC is not present the line drive will be inhibited within 2 ms, the EW otpt crrent will drop to zero and the vertical otpt crrent will drop to 20% of the adjsted vale within 100 ms). The SDA and SCL inpts meet the I2Cbs specification, the other three inpts are TTL compatible. The LLC freqency can be divided-by-two internally by connecting LLCS (pin 5) to grond thereby enabling the prescaler. The LLC timing is given in the Chapter Characteristics. Vertical part (pins 6, 8, 10, 11 and 12) SYNCHRONIZATION PULSE The V A inpt (Pin 12) is a TTL-compatible CMOS inpt. Plses at this inpt have to flfil the timing reqirements as illstrated in Fig.6. For correct detection the minimm plse width for both the HIGH and LOW period is 2 internal clock periods. For frther reqirements on minimm plse width see also Section Deinterlace. VERTICAL PLACE GENERATOR An overview of the varios modes of operation of the vertical place generator is illstrated in Fig.l3. With control bit CPR a compress to 75% of the adjsted vales is possible in all modes of operation. This control bit is sed to display 16 : 9 standard pictres on 4 : 3 displays. No new adjstment of other corrections, sch as corner and S-correction, is reqired. With control bit VPR a redction of the crrent dring clipping, wait and stop modes to 20% of the nominal vole can be selected, which will redce the dissipation in the vertical drive circits. Vertical place generator in adaptive mode (MS=logic 0).

39 The vertical start-scan data (sbaddress 02) determines the vertical placement in the total range of 64 x 432 clock periods in 63 steps. The maximm nmber of synchronized lines per scan is 910 with an eqivalent field freqency of 17.2 or 34.4 Hz for f H = or Hz respectively. The minimm nmber of synchronized lines per scan is 200 with an eqivalent field freqency of 78 or 156 Hz for f H = or Hz respectively. If the VA plse is not present, the nmber of lines per scan will increase to If the LLC is not present the vertical blanking will start within 2 µs. Amplitde control is atomatic, with a settling time of 1 to 2 new fields and an accracy of either 16/12 or 48/12 lines depending on the vale of the GBS bit. Differences in the nmber of lines per field, as can occr in TXT or in mlti-head VTR, will not affect the amplitde setting providing the differences are less than the vale selected with GBS. This is called amplitde control gardband. This difference seqence and the difference seqence length are not important. Vertical place generator in constant slope mode (MS = logic I) In this mode the slope can be programmed directly with a two byte vale on sbaddress 0C (MSB) and 0D (LSB). When the actal nmber of lines is greater than the programmed nmber of lines, the circit will enter the stop state in which the differential vertical otpt crrent remains 100% or drops to 20% (programmable with control bit VPR). The programmed vale for the slope is the reqired nmber of lines mltiplied by 72. The programming limits are; minimm 200 x 72 and maximm 910 x 72. A vertical expansion is obtained with a combination of slope data and a programmable wait stats, at sbaddress 0E. The wait stats is selected with control bit MS and can only be activated in the constant slope mode. The wait state is an 8-bit vale, programmable from 0 to 255. The actal wait state is one line longer than the programmed vale. If blanking is applied dring stop and wait stats the differential otpt crrent will be the same with VPR selected vale (20 or 100%). DE-INTERLACE With de-interlace on (DINT = logic 0), the V A plse is sampled with LLC at a position spplied by control bit DIP (de-interlace phase). When DIP = logic 0 sampling takes place 42 clock plses after the leading edge of H A (T = T line x 42/432). When DIP = logic 1 sampling takes place 258 clock plses after the leading edge of H A (T = T line x 258/432). The distance between the two selectable sampling points is (T line x (258-42)/432) which is exactly half a line, ths de-interlace is possible in two directions. The dration of the VA plse mst, therefore, be sfficient to enable the HA plse to caght, in this event an active time of minimm of half a line. With de-interlace off, the V A plse is sampled with the system clock. The leading edge is detected and sed as the vertical reset. Selection of the positive or negative leading edge is achieved by the control bit VAP. Horizontal part (pins 1,2, 13, 19 and 20 SYNCHRONIZATION PULSE The HA inpt (pin 13) is a TTL-compatible CMOS inpt. Plses on this inpt have to flfil the timing reqirements as illstrated in Fig.6. For correct detection the minimm plse width for both the HIGH and LOW periods is 2 internal clock periods. FLYBACK INPUT PULSE The HFB inpt (pin 1) is a CMOS inpt. The delay of the centre of the flyback plse to the leading edge of the HA plse can be set via the I 2 C-bs with the horizontal phase byte (sbaddress 08) The resoltion is 6-bit. OUTPUT PULSE The HOUT plse (pin 20) is an open-drain NMOS otpt. The dty factor for this otpt is typically 52/48 (condcting/non-condcting) dring normal operation. A soft start cases the dty factor to increase linearly from 5 to 52% over a minimm period of 2000 lines in 2000 steps. OFF-CENTRE SHIFT The OFCS otpt (pin 19) is a psh-pll CMOS otpt which is driven by a plse-width modlated DAC. By sing a sitable interface, the otpt signal can be sed for off-centre shift correction in the horizontal otpt stage. This correction is reqired for HDTV tbes with a 16 x 9 aspect ratio and is sefl for high performance flat sqare tbes to obtain the reqired horizontal linearity. For applications where offcentre correction is not reqired, the otpt can be sed as an axiliary DAC. The OFCS signal is phaselocked with the line freqency. The off-centre shift can be set via the I 2 C-bs, sbaddress 09, with a 6- bit resoltion as illstrated in Fig.8. SANDCASTLE The DSC inpt/otpt (pin 2) acts as a sandcastle generating otpt and a gard sensing inpt. As an otpt it provides 2 levels (apart from the base level), one for the horizontal and vertical blanking and the other for the video clamping. As an inpt it acts as a crrent sensor dring the vertical blanking interval for gard detection. CLAMPING PULSE

40 The clamping plse width is 21 internal clock periods. The shift, with respect to HA can be varied from 35 to 49 clock periods in 7 steps via the I2C-bs, clamp shift byte sbaddress 0A, as illstrated in Fig.9. It is possible to sppress the clamping plse dring wait, stop and protection modes with control bit CSU. This will avoid nwanted reset of the TDA4680/81 (only sed in those circits). HORIZONTAL BLANKING The start of the horizontal blanking plse is minimm 38 and maximm 41 clock periods before the centre of the flyback plse, depending on the f clk /f H ratio K in accordance with 41 - (432 - K). Stop of the horizontal blanking plse is determined by the trailing edge of the HFB plse at the horizontal blanking slicing level. VERTICAL BLANKING The vertical blanking plse starts two internal clock plses after the rising edge of the VA plse. Dring this interval a small gard plse, generated dring flyback by the vertical power otpt stage, mst be inserted. Stop vertical blanking is effected at the end of the blanking interval only when the gard plse is present (see Section Vertical gard ). The start scan setting determines the end of vertical blanking with a 6-bit resoltion in steps of one line via the I 2 C-bs sbaddress 02. VERTICAL GUARD In the vertical blanking interval a small nblanking plse is inserted. This plse mst be filled-in by a blanking plse or gard plse from the vertical power otpt stage which was generated dring the flyback period. In this condition the sandcastle otpt acts as gard detection inpt and reqires a minimm 800 µa inpt crrent. This crrent is sensed dring the nblanking period. Vertical blanking is only stopped at the end of the blanking interval when the inserted plse is present. In this way the pictre tbe is protected against damage in the event of missing or malfnctioning vertical deflection VERTICAL GEOMETRY PROCESSING The vertical geometry processing is DC-copled and therefore independent of field freqency. The external resistive conversion (RCONV) at pin 8 sets the reference crrent for both the vertical and EW geometry processing. A sefl range is 100 to 150 µa, the recommended vale is 120 µa. VERTICAL OUTPUTS The vertical otpts VOUT A and VOUTB on pins 10 and 11 together form a differential crrent otpt. The vertical amplitde can be varied over the range 80 to 120% in 63 steps via the I 2 C-bs (sbaddress 00). Vertical S-correction is also applied to these otpts and can be set from 0 to 16% by sbaddress 01 with a 6-bit resoltion. The vertical off-centre shift (OFCS) shifts the vertical deflection crrent zero crossing with respect to the EW parabola bottom. The control range is -1.5 to +1.5% (±1/8 x I8) in 7 steps set by the least significant nibble at sbaddress 03. EW GEOMETRY PROCESSING The EW geometry processing is DC copled and therefore independent of field freqency. RCONV sets the reference crrent for both the vertical and EW geometry processing. The EW otpt is an ESD-protected single-ended crrent otpt. The EW width/width ratio can be set from 100 to 80% in 63 steps via sbaddress 04 and the EW parabola/width ratio from 0 to 20% via sbaddress 05. The EW corner/ew parabola ratio has a control range of -40 to 0% in 63 steps via sbaddress 06. The EW trapezim correction can be set from -1.5 to +1.5% in 7 steps via the most significant nibble at sbaddress 03. BULT GENERATOR The Blt generator makes the EW waveform continos. Protection inpt (pin 3) The protection inpt (PROT) is a CMOS inpt. The inpt voltage mst be EHT scaled and has the following characteristics: Two modes of protection are available with the aid of control bit PRD. With PRD = logic 1 the protection mode is selected, HOUT will be defeated and the PROT bit in the stats word is set if the inpt voltage is above 3.9 V. Ths the deflection stops and EW otpt crrent is zero, while the vertical otpt crrent is redced to 20% of the adjsted vale. A new start of the circit is I 2 C-bs controlled with the ser software. With PRD = logic 0 the detection mode is selected, HOUT will not be defeated and the over voltage information is only written in the PROT stats bit and can be read by the I 2 C-bs. All frther actions, sch as a write of the LFSS bit, are achieved by the I2C-bs. They depend on the configration sed and are defined by ser software. Flash detection/protection inpt (pin 9) The FLASH inpt is a CMOS inpt with an internal pllp crrent of approximately 8 µa. When a negative-going edge crosses the 0.75 V level a restart will be exected with a soft start of approximately lines, sch as in the soft-start mode. When the fnction is not sed pin 9 can be connected to grond, VCC or left open-circit, the internal pll-p crrent sorce will prevent any problems. However a hard wired connection to VCC or grond is

41 recommended when the fnction is not sed. EHT compensation (pin 7) The EHT inpt is a CMOS inpt. The EHT compensation inpt permits scan amplitde modlation shold the EHI spply not be perfect. For correct tracking of the vertical and horizontal deflection the gain of the EW otpt stage, provided by the ratio R CONV-EW /R CONV, mst be 1/16 V scan X V ref. The inpt for EHT compensation can be derived from an EHT bleeder or from the pictre tbes aqadag (sbaddress 0B, bit BLDS). QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS Min. Typ. Max. Unit V CC spply voltage V I CC spply crrent fclk= 6.75 MHz ma P tot total power dissipation top sync-white mw T amb operating ambient temperatre top sync-whit C o Inpts V 14 line-locked clock (LLC) logic level - TTL - - V 13 horizontal sync (H A ) logic level - TTL - - V 12 vertical sync (V A ) logic level - TTL - - V 5 line-locked clock select (LLCC) logic level note 1 - CMOS 5V - - V 18 serial clock (SCL) logic level - CMOS 5V - - V 17 serial data inpt (SDA) logic level - CMOS 5V - - V 1 horizontal flyback (HFB) phase FBL = logic V slicing level FBL = logic V V 1 horizontal flyback (HFB) blanking slicing level mv V 3 over voltage protection (PROT) level V V 9 EHT flash detection level V Otpts V 20 horizontal otpt (HOUT) voltage (open drain) I 20 = 10mA V I 11- I 10(M) vertical differential (VOUT A,B ) vertical amplitde =100% µa otpt crrent (peak vale) I 8 = -120µA V 10,11 vertical otpt voltage V I 6(M) EW (EWOUT) total otpt crrent (peak vale) I 8 = -120µA µa V 6 EW (EWOUT) otpt voltage V SANDCASTLE OUTPUT LEVELS (DSC) V 2 base voltage level V V 2 horizontal and vertical blanking voltage level V V 2 video blanking voltage leve V HORIZONTAL OFF-CENTRE SHIFT (OFCS) V 19 otpt voltage I 19 = 2 ma 0 - V CC V

42 TDA8540 4x4 Video Switch Matrix GENERAL DESCRIPTION The TDA8540 has been designed for switching between composite video signals, therefore the minimm of for inpt lines are provided as reqested for switching between two S-VHS sorces. Each of the for otpts can be set to a high impedance state, to enable parallel connection of several devices. PINNING Pin Symbol Fnction 1 OUT2 video otpt 2 2 DO control otpt 0 3 OUT 3 video otpt 3 4 V CC(D2,3) driver spply voltage; for drivers 2 and 3 5 S2 sb- address inpt 2 6 INO video inpt 0 (CVBS or chrominance signal) 7 S1 sb- address inpt 1 8 IN1 video inpt 1 (CVBS or chrominance signal) 9 AGND analog grond 10 IN2 video inpt 2 (CVBS or lminance signal) 11 S0 sb- address inpt 0 12 IN3 video inpt 3 (CVBS or lminance signal) 13 V CC general spply voltage 14 OUT1 video otpt 1 15 V CC(D0,1) driver spply voltage; for drivers 0 and OUT0 video otpt 0 17 D1 control otpt 1 18 SCL serial clock inpt 19 SDA serial data inpt/otpt 20 DGND digital grond FEATURES I 2 C-bs or non-i 2 C-bs mode (controlled by DC voltages) S-VHS or CVBS processing 3-state switches for all channels Selectable gain for the video channels sb-address facility Slave receiver in the I 2 C mode Axiliary logic otpts for adio switching System expansion possible p to 7 devices (28 sorces) Static short-circit proof otpts ESD protection. OUT 2 DO OUT 3 VCC(D2,3) S2 IN0 S1 IN1 AGND IN U TDA Pin Description DGND SDA SCL D1 OUT 0 VCC(D0,1) OUT 1 V CC IN3 S0 QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS Min. Typ. Max. Unit V CC spply voltage V I CC spply crrent ma I SO isolation OFF state at f = 5 MHz db B 3dB bandwith MHz α CT crosstalk attenation between channels db

43 V CC(D0,1) V CC(D2,3) SWITCH MATRIX 15 4 IN3 12 PEAK- CLAMP GAIN DRIVER 3 3 OUT3 IN2 10 PEAK- CLAMP GAIN DRIVER 2 1 OUT2 IN1 8 PEAK- CLAMP/ BIAS GAIN DRIVER 1 14 OUT3 IN0 V CC DGND AGND PEAK- CLAMP/ BIAS 2 CLO to CL1 SUPPLY power reset DECODER 1 OF DECODER 1 OF 4 DECODER 1 OF 4 DECODER 1 OF I 2 C RECEIVER G0 to G3 4 GAIN TDA DRIVER 0 EN0 to EN OUT1 D1 D0 S0 S1 S2 SCL SDA Block digram. FUNCTIONAL DESCRIPTION The TDA8540 is controlled via a bidirectional I 2 C- bs.3 bits of the I 2 C address can be selected via the address pin, ths providing a facility for parallel connection of 7 devices. Control options via the I 2 C-bs: The inpt signals can be clamped at their negative peak (top sync). The gain factor of the otpts can be selected between 1x or 2x. Each of the for otpts can individally be connected to one of the for inpts. Each otpt can individally be set in a high impedance state. Two binary otpt data lines can be controlled for switching accompanying sond signals. The SDA and SCL pins (pins 19 and 18)can be connected to the I 2 C-bs or to DC switching voltage sorces. Address inpts S0 to S2 (pins 11, 7 and 5) are sed to select sb-addresses or switching to the non- I 2 C mode. Inpts S0 to S2 can be connected to the spply voltage (HIGH) or the grond (LOW). In this way no peripheral components are reqired for selection. I 2 C-Ss sb-addressing S2 S1 S0 I 2 C-bs control After power-p the otpts are initialized in the high impedance state, and D0 and D1 are at a LOW level. Detailed description of the I2C-bs specification, with applications, is given in brochre The I2C-bs and how to se if : This brochre may be ordered sing the code The TDA8540 is a slave receiver. SUB-ADDRESS A2 A1 AO L L L L L H L H L L H H H L L H L H H H L H H H non I 2 C addressable

44 TDA8351 DC- Copled Vertical Deflection Circit GENERAL DESCRIPTION The TDA8351 is a power circit for se in 90 o and 110 o color deflection systems for field freqencies of 50 to120 Hz. The circit provides a DC driven vertical deflection otpt circit, operating as a highly efficient class G system. FUNCTIONAL DESCRIPTION The vertical driver circit is a bridge configration. The deflection coil is connected between the otpt amplifiers, which are driven in phase opposition. An external resistor (RM) connected in series with the deflection coil provides internal feedback information. The differential inpt circit is voltage driven. The inpt circit has been adapted to enable it to be sed with the TDA9150A, TDA9151B, TDA9160A, TDA9162, TDA8366 and TDA8376 which deliver symmetrical crrent signals. An external resistor (RCON) connected between the differential inpt determines the otpt crrent throgh the deflection coil. The relationship between the differential inpt crrent and the otpt crrent is defined by: I diff x R CON = I coil x R M. The otpt crrent is adjstable from 0.5 A (p-p) to 3 A (p-p) by varying R M. The maximm inpt differential voltage is 1.8 V. In the application it is recommended that V dif f = 1.5 V (typ), This is recommended becase of the spread of inpt crrent and the spread in the vale of R CON The flyback voltage is determined by an additional spply voltage V FB. The principle of operating with two spply voltages (class G) makes it possible to fix the spply voltage V p optimm for the scan voltage and the second spply voltage V FB optimm for the flyback voltage. Using this method, very high efficiency is achieved. The spply voltage V FB is almost totally available as flyback voltage across the coil, this being possible de to the absence of a decopling capacitor (not necessary, de to the bridge configration). The otpt circit is flly protected against the following: thermal protection short-circit protection of the otpt pins (pins 4 and 7) short-circit of the otpt pins to V p. A gard circit VO(gard) is provided. The gard circit is activated at the following conditions: dring flyback dring short-circit of the coil and dring short-circit of the otpt pins (pins 4 and 7) to V p or grond dring open loop when the thermal protection is activated. This signal can be sed for blanking the pictre tbe screen. FEATURES Few external components Highly efficient flly DC-copled vertical otpt bridge circit Vertical flyback switch Gard circit Protection against: - short-circit of the otpt pins (7 and 4) - short-circit of the otpt pins to V p Temperatre (thermal) protection High EMC immnity becase of common mode inpts A gard signal in zoom mode. PINNING Pin Symbol Fnction 1 I drive(pos) inpt power-stage (positive); incldes I I(sb) signal bias 2 I drive(neg) inpt power-stage (negative); incldes I I(sb) signal bias 3 V P operating spply voltage 4 V 0(B) otpt voltage B 5 GND grond 6 V FB inpt flyback spply voltage 7 V 0(A) otpt voltage A 8 V 0(gard) gard otpt voltage 9 V I(fb) inpt feedback voltage I drive(pos) I drive(neg) V P V 0(B) GND V FB V 0(A) V 0(gard) V I(fb) U TDA8351 Pin Configration

45 QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS Min. Typ. Max. Unit DC spply V P spply voltage 9-25 V I q qiescent spply crrent ma Vertical circit I O(p-p) otpt crrent (peak-to-peak vale) A I diff(p-p) differential crrent (peak-to-peak vale) µa V diff(p-p) differential inpt voltage (peak-to-peak vale) V Flyback switch I M peak otpt crrent - - ±1.5 A V FB flyback spply voltage V note V Thermal data (in accordance with IEC 747-1) T stg storage temperatre o C T amb operating ambient temperatre o C T vj virtal jnction temperatre o C V P V O(gard) V FB +V P CURRENT SOURCE + - TDA8351 +V P + - +V O(A) V O(A) I drive(pos) 1 I drive(neg) I s +I T -I T +V P V I(fb) +V +I s V O(B) V O(B) 5 GND Block diagram

46 TDA9875A Digital TV Sond Processor (DTVSP) GENERAL DESCRIPTION The TDA9875A is a single-chip Digital TV Sond Processor (DTVSP) for analog and digital mlti-channel sond systems in TV sets and satellite receivers. Spported standards The mltistandard/mlti-stereo capability of the TDA9875A is mainly of interest in Erope, bt also in Hong Kong/Peoples Repblic of China and Soth East Asia. This incldes B/G, D/K, I, M and L standard. In other application areas there exists only sbsets of those standard combinations otherwise only single standards are transmitted. M standard is transmitted in Erope by the American Forces Network (AFN) with Eropean channel spacing (7 MHz VHF, 8 MHz UHF) and monaral sond. The AM sond of L/L' standard is normally demodlated in the 1 st sond IF. The reslting AF signal has to be entered into the mono adio inpt of the TDA9875A. A second possibility is to se the internal AM demodlator stage, however this gives limited performance. Korea has a stereo sond system similar to Erope and is spported by the TDA9875A. Differences inclde deviation, modlation contents and identification. It is based on M standard. An overview of the spported standards and sond systems and their key parameters is given in Table B The analog mlti-channel sond systems (A2, A2+ and A2*) are sometimes also named 2CS (2 carrier systems). FEATURES Demodlator and decoder section Sond IF (SIF) inpt switch e.g. to select between terrestrial TV SIF and SAT SIF sorces SIF AGC with 24 db control range SIF 8-bit Analog-to-Digital Converter (ADC) DQPSK demodlation for different standards, simltaneosly with i-channel FM demodlation NICAM decoding (B/G, I and L standard) Two-carrier mltistandard FM demodlation (B/G, D/K and M standard) Decoding for three analog mlti-channel systems (A2, A2+ and A2*) and satellite sond Optional AM demodlation for system L, simltaneosly with NICAM Programmable identification (B/G, D/K and M standard) and different identification times. DSP section Digital crossbar switch for all digital signal sorces and destinations Control of volme, balance, contor, bass, treble, psedo stereo, spatial, bass boost and soft-mte Plop-free volme control Atomatic Volme Level (AVL) control Adaptive de-emphasis for satellite Programmable beeper Monitor selection for FM/AM DC vales and signals, with peak detection option I 2 S-bs interface for a featre extension (e.g. Dolby srrond) with matrix, level adjst and mte. Analog adio section Analog crossbar switch with inpts for mono and stereo (also applicable as SCART 3 inpt), SCART 1 inpt/otpt, SCART 2 inpt/otpt and line otpt User defined fll-level/-3 db scaling for SCART otpts Otpt selection of mono, stereo, dal A/B, dal A or dal B 20 khz bandwidth for SCART-to-SCART copies Standby mode with fnctionality for SCART copies Dal adio digital-to-analog converter from DSP to analog crossbar switch, bandwidth 15 khz Dal adio ADC from analog inpts to DSP Two dal adio Digital-to-Analog Converters (DACs) for lodspeaker (Main) and headphone (Axiliary) otpts; also applicable for L, R, C and S in the Dolby Pro Logic mode with featre extension.

47 PINNING SYMBOL PIN I/O DESCRIPTION PCLK 1 O NICAM clock otpt at 728 khz NICAM 2 O serial NICAM data otpt at 728 khz ADDR1 3 I first I 2 C-bs slave address modifier SCL 4 I I 2 C-bs clock SDA 5 I/O I 2 C-bs data V SSA1 6 spply spply grond 1; analog front-end circitry V DEC1 7 - positive power spply voltage 1 decopling; analog front-end circitry I REF1 8 - resistor for reference crrent generator; analog front-end circitry P 1 9 I/O first general prpose I/O pin SIF2 10 I sond IF inpt 2 V REF reference voltage; analog front-end circitry SIF1 12 I sond IF inpt 1 ADDR2 13 I second I 2 C-bs slave address modifier V SSD1 14 spply spply grond 1; digital circitry V DDD1 15 spply digital spply voltage 1; digital circitry CRESET 16 - capacitor for power-on reset V SSD4 17 spply spply grond 4; digital circitry XTALI 18 I crystal oscillator inpt XTALO 19 O crystal oscillator otpt P2 20 I/O second general prpose I/O pin SYSCLK 21 O system clock otpt SCK 22 I/O I 2 C-bs clock WS 23 I/O I 2 C-bs word select SDO2 24 O I 2 C-bs data otpt 2 SDO1 25 O I 2 C-bs data otpt 1 SDI2 26 I I 2 C-bs data inpt 2 SDI1 27 I I 2 C-bs data inpt 1 TEST1 28 I first test pin; connected to V SSD1 for normal operation MONOIN 29 I adio mono inpt TEST2 30 I second test pin; connected to V SSD1 for normal operation EXTIR 31 I external adio inpt right channel EXTIL 32 I external adio inpt left channel SCIR1 33 I SCART 1 inpt right channel SCIL1 34 I SCART 1 inpt left channel V SSD3 35 spply spply grond 3; digital circitry SCIR2 36 I SCART 2 inpt right channel SCIL2 37 I SCART 2 inpt left channel V DEC positive power spply voltage 2 decopling; adio analog-to-digital converter circitry V ref(p) 39 - positive reference voltage; adio analog-to-digital converter circitry V ref(n) 40 - reference voltage grond; adio analog-to-digital converter circitry i.c internal connected; note 1 i.c internal connected; note 2 V SSA2 43 spply spply grond 2, adio analog-to-digital converter circitry i.c internal connected; note 2 i.c internal connected; note 1 V ref reference voltage; adio analog-to-digital converter circitry SCOR1 47 O SCART 1 otpt right channel

48 SYMBOL PIN I/O DESCRIPTION SCOL2 48 O SCART 1 otpt left channel V SSD2 49 spply spply grond 2; digital circitry V SSA4 50 spply spply grond 4; adio operational amplifier circitry SCOR 2 51 O SCART 2 otpt right channel SCOL 2 52 O SCART 2 otpt left channel V REF reference voltage; adio digital-to-analog converter and operational amplifier circitry PCAPR 54 - post-filter capacitor pin right channel, adio digital-to-analog converter PCAPL 55 - post-filter capacitor pin left channel, adio digital-to-analog converter V SSA3 56 spply spply grond 3; adio digital-to-analog converter circitry AUXOR 57 O headphone (Axiliary) otpt right channel AUXOL 58 O headphone (Axiliary) otpt left channel V DDA 59 spply positive analog power spply voltage; analog circitry MOR 60 O lodspeaker (Main) otpt right channel MOL 61 O lodspeaker (Main) otpt left channel LOL 62 O line otpt left channel LOR 63 O line otpt right channel V DDD2 64 spply digital spply voltage 2; digital circitry PCLK NICAM ADDR1 SCL SDA V SSA1 V DEC1 I REF1 P 1 SIF2 V REF1 SIF U V DDD2 LOR LOL MOL MOR V DDA AUXOL AUXOR V SSA3 PCAPL PCAPR V REF3 ADDR SCOL 2 V SSD1 SCOR 2 V DDD1 CRESET V SSD4 XTALI XTALO P2 SYSCLK SCK WS SDO2 SDO1 SDI2 SDI1 TEST1 MONOIN TEST2 EXTIR EXTIL TDA9875A V SSA4 V SSD2 SCOL2 SCOR1 V ref2 i.c. i.c. V SSA2 i.c. i.c. V ref(n) V ref(p) V DEC2 SCIL2 SCIR V SSD SCIL1 SCIR1

49 BLOCK DIAGRAM S I F 2 S I F P1 P2 ADDR1 ADDR2 SCL SDA I 2 C INPUT SWITCH AGC, ADC SUPPLY SIF V DEC1 V DEC1 V ref 1 I ref IDENTIFICATION FM (AM) DEMODULATION NICAM DEMODULATION 2 1 NICAM PCLK XTALI XTALO SYSCLK CLOCK PEAK DETECTION A2 DECODER & SAT DECODER LEVEL ADJUST NICAM DECODER LEVEL ADJUST ANALOG CROSSBAR SWITCH SCIR1 SCIL1 SCIR2 SCIL2 EXTIR EXTIL MONOIN SCOR1 SCOL1 SCOR2 SCOL2 LOR LOL SDI1 SDI2 SDO1 SDO2 SCK WS I 2 S DIGITAL SELECT ADC (2) C..C..C..C. V DDD1 V DDD2 V SSD1 V SSD2 V SSD3 V SSD4 CRESET DIGITAL SUPPLY DAC (2) PCAPR PCAPL 15 TDA9875A AUDIO PROCESSING SUPPLY SCART, DAC, ADC V DDA V DEC2 V ref(p) V ref(n) TEST1 TEST TEST DAC (2) DAC (2) V ref2 V ref3 V SSA2 V SSA3 V SSA MOL MOR AUXOL AUXOR

50 ANALOG 2- CARRIER SYSTEMS Table B- Freqency modlation STANDARD SOUND SYSTEM CARRIER FREQUENCY (MHZ) FM DEVIATION (khz) NOM./MAX./OVER SC1 MODULATION SC2 BANDWIDTH/ DE-EMPHASIS (khz/µs) M mono /25/50 mono - 15/75 M A2+ 4.5/ /25/50 1/2(L + R) 1/2(L - R) 15/75 (Korea) B/G A2 5.5/ /50/80 1/2(L + R) R 15/50 I mono /50/80 mono - 15/50 D/K A2 6.5/ /50/80 1/2(L + R) R 15/50 D/K A2* 6.5/ /50/80 1/2(L + R) R 15/50 Table C- identification for A2 systems PARAMETER A2/A2* A2+ (KOREA) Pilot freqency khz = 3.5 x line freqency khz = 3.5 x line freqency Stereo identification Hz = line freqency Hz = line freqency freqency Dal identification Hz = line freqency Hz = line freqency freqency AM modlation depth 50% 50% 2- CARRIER SYSTEMS WITH NICAM Table D- NICAM STANDARD FREQUENCY (MHZ) MODULATION TYPE MODULATION INDEX (%) NOM./MAX DEVIATION (khz) NOM./MAX SC2 (MHz) NICAM DE-EMPHASIS ROLL-OFF (%) NICAM CODING B/G 5.5 FM - 27/ J17 40 note 1 I 6.0 FM - 27/ J note 1 DK 6.5 FM - 27/ J17 40 note 2 L 6.5 AM 54/ J17 40 note 1 SATELLITE SYSTEMS An important specification for satellite TV reception is the Astra specification. The TDA9875A is sited for the reception of Astra and other satellite signals. Table E- FM satellite sond CARRIER TYPE CARRIER FREQUENCY (MHZ) MODULATION INDEX MAXIMUM FM DEVIATION (khz) MODULATION BANDWIDTH/ DE-EMPHASIS (khz/µs) Main 6.50 (1) mono 15/50 (1) Sb 7.02/ m/st/d (2) 15/adaptive (3) Sb 7.38/ m/st/d (2) 15/adaptive (3) Sb 7.74/ m/st/d (2) 15/adaptive (3) Sb 8.10/ m/st/d (2) 15/adaptive (3)

51 FUNCTIONAL DESCRIPTION Description of the demodlator and decoder section 1- SIF INPUT Two inpt pins are provided, SIF1 e.g. for terrestrial TV and SIF2 e.g. for a satellite tner. For higher SIF signal levels the SIF inpt can be attenated with an internal switchable -10 db resistor divider. As no specific filters are integrated, both inpts have the same specification giving flexibility in application. The selected signal is passed throgh an AGC circit and then digitized by an 8-bit ADC operating at MHz. 2- AGC The gain of the AGC amplifier is controlled from the ADC otpt by means of a digital control loop employing hysteresis. The AGC has a fast attack behavior to prevent ADC overloads and a slow decay behavior to prevent AGC oscillations. For AM demodlation the AGC mst be switched off. When switched off, the control loop is reset and fixed gain settings can be chosen from Table 15 (sbaddress 0). The AGC can be controlled via the I 2 C-bs. Details can be fond in the I 2 C-bs register definitions.(see Chapter 10). 3- MIXER The digitized inpt signal is fed to the mixers, which mix one or both inpt sond carriers down to zero IF. A 24-bit control word for each carrier sets the reqired freqency. Access to the mixer control word registers is via the I 2 C- bs. When receiving NICAM programs, a feedback signal is added to the control word of the second carrier mixer to establish a carrierfreqency loop. 4- FM AND AM DEMODULATION An FM or AM inpt signal is fed via a band-limiting filter to a demodlator that can be sed for either FM or AM demodlation. Apart from the standard (fixed) de-emphasis characteristic, an adaptive de-emphasis is available for encoded satellite programs. A stereo decoder recovers the left and right signal channels from the demodlated sond carriers. Both the Eropean and Korean stereo systems are spported. 5- FM IDENTIFICATION The identification of the FM sond mode is performed by AM synchronos demodlation of the pilot signal and narrow-band detection of the identification freqencies. The reslt is available via the I 2 C-bs interface. A selection can be made via the I 2 C-bs for B/G, D/K and M standard and for three different modes that represent different trade-offs between speed and reliability of identification. 6- NICAM DEMODULATION The NICAM signal is transmitted in a DQPSK code at a bit rate of 728 kbit/s. The NICAM demodlator performs DQPSK demodlation and feeds the reslting bitstream and clock signal onto the NICAM decoder and, for evalation prposes, to PCLK (pin 1)and NICAM (pin 2). A timing loop controls the freqency of the crystal oscillator to lock the sampling rate to the symbol timing of the NICAM data. 7- NICAM DECODER The device performs all decoding fnctions in accordance with the "EBU NICAM 728 specification. After locking to the frame alignment word, the data is descrambled by applying the defined psedo-random binary seqence; the device will then synchronize to the periodic frame flag bit C0. The stats of the NICAM decoder can be read ot from the NICAM stats register by the ser (see the I 2 C-bs register description in Section ). The OSB bit indicates that the decoder has locked to the NICAM data. The VDSP bit indicates that the decoder has locked to the NICAM data and that the data is valid sond data. The C4 bit indicates that the sond conveyed by the FM mono channel is identical to the sond conveyed by the NICAM channel. The error byte contains the nmber of sond sample errors, reslting from parity checking, that occrred in the past 128 ms period. The Bit Error Rate (BER) can be calclated sing the following eqation; bit error bit errors BER = = error byte x1.74 x 10-5 total bits 8- NICAM AUTO-MUTE This fnction is enabled by setting bit AMUTE LOW sbaddress 14 (see Section ). Upper and lower error limits may be defined by writing appropriate vales to two registers in the I 2 C-bs section (sbaddresses 16 and 17; see Sections and ). When the nmber of errors in a 128 ms period exceeds the pper error limit the ato-mte fnction will switch the otpt sond from NICAM to whatever sond is on the first sond carrier (FM

52 or AM). When the error cont is smaller than the lower error limit the NICAM sond is restored. The ato-mte fnction can be disabled by setting bit AMUTE HIGH. In this condition clicks become adible when the error cont increases; the ser will hear a signal of degrading qality. A decision to enable/disable the ato-mting is taken by the microcontroller based on an interpretation of the application control bits C1, C2, C3 and C4 and, possibly, any additional strategy implemented by the set maker in the microcontroller software. For NICAM L applications, it is recommended to demodlate AM sond in the first sond IF and connect the adio signal to the mono inpt of the TDA9875A. By setting the AMSEL bit sbaddress 14 (see Section ), the atomte fnction will switch to the adio ADC instead of switching to the first sond carrier. The ADC sorce selector sbaddress 23 (see Section ) shold be set to mono inpt, where the AM sond signal shold be connected. 10- TEST PINS Both test pins are active HIGH, in normal operation of the device they are wired to V SSD1. Test fnctions are for manfactring tests only and are not available to cstomers. Withot external circitry these pads are plled down to LOW level with internal resistors. 11- POWER-ON RESET FLIP-FLOP The power-on reset flip-flop monitors the internal power spply for the digital part of the device. If the spply has temporary been lower than the specified lower limit, the power-on reset bit POR, transmitter register sbaddress 0 (see Section ), will be set to HIGH. The CLRPOR bit, slave register sbaddress 1 (see Section ), resets the power-on reset flipflop to LOW. If this is detected, an initialization of the TDA9875A has to be carried ot to ensre reliable operation. 9- CRYSTAL OSCILLATOR The digital-controlled crystal oscillator (DCXO) is illstrated in Fig.8 (see Chapter 12). The circitry of the DCXO is flly integrated, only the external MHz crystal is needed.

53 TDA2616 2x12W Hi-Fi Adio Power Amplifiers with Mte GENERAL DESCRIPTION The TDA2616 is a dal power amplifiers. It has been especially designed for mains fed applications sch as stereo radio and stereo TV. FEATURES Reqires very few external components No switch-on/switch-off clicks Inpt mte dring switch-on and switch-off Low offset voltage between otpt and grond Excellent gain balance of both amplifiers Hi-Fi accordance with IEC 268 and DIN Short-circit proof and thermal protected Mte possibility. -INV1 1 U MUTE 2 1/2V P /GND 3 PINNING Pin Symbol Fnction 1 -INV1 non-inverting inpt 1 2 MUTE mte inpt 3 1/2V P /GND 1/2 spply voltage or grond 4 OUT1 otpt 1 5 -V P spply voltage (negative) 6 OUT2 otpt 2 7 +V P spply voltage (positive) 8 INV1,2 inverting inpts 1,2 9 -INV2 non-inverting inpt 2 OUT1 -V P OUT2 +V P INV1,2 -INV TDA2616 Pin Configration QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS Min. Typ. Max. Unit ±V P spply voltage range V P O otpt power V P = ±16V; THD = 0.5% W G V internal voltage gain db I G V I channel nbalance db α channel separation db SVRR spply voltage ripple rejection db V no noise otpt voltage µv

54 Block Diagram +V P V ref1 V A 7 TDA2616 INV1 MUTE Ω 20kΩ 4kΩ 5kΩ +V P V B V P CM 20kΩ 4 OUT 1 V ref3 10kΩ +V P 1/2 V P / GND 3 V ref1 +V ref2 voltage comparator THERMAL PROTECTION 10kΩ V A V B V ref2 V P V P INV2 INV1, kΩ 680kΩ V B CM 20kΩ 6 OUT 2 V ref1 V A 5 V P FUNCTIONAL DESCRIPTION The TDA2616 is a hi-fi stereo amplifier designed for mains fed applications, sch as stereo radio and TV. The circit is optimally designed for symmetrical power spplies, bt is also well-sited to asymmetrical power spply systems. An otpt power of 2 x 12 W (THD = 0.5%) can be delivered into an 8 Ω load with asymmetrical power spply of ±16 V. The gain is internally fixed at 30 db, ths offering a low gain spread and a very good gain balance between the two amplifiers (0.2 db). A special featre is the inpt mte circit. This circit disconnects the non-inverting inpts when the spply voltage drops below ±6 V, while the amplifier still retains its DC operating adjstment. The circit featres sppression of nwanted signals at the inpts, dring switch-on and switch-off. The mte circit can also be activated via pin 2. When a crrent of 300 µa is present at pin 2, the circit is in the mte condition. The device is provided with two thermal protection circits. One circit measres the average temperatre of the crystal and the other measres the momentary temperatre of the power transistors. These control circits attack at temperatres in excess of +150 o C, so a crystal operating temperatre of max o C can be sed withot extra distortion. With the derating vale of 2.5 K/W, the heatsink can be calclated as follows: at R L = 8 Ω and V p = ±16 V. the measred maximm dissipation is 14.6 W. With a maximm ambient temperatre of +65 o C, the thermal resistance of the heatsink is: R th = = 3.3 K/W The internal metal block has the same potential as Pin 5.

55 TDA Control IC for SMPS FEATURES Fold-back characteristics provides overload protection for external components Brst operation nder secondary short-circit condition implemented Protection against open or a short of the control loop Switch-off if line voltage is too low (ndervoltage switchoff) Line voltage depending compensation of fold-back point Soft-start for qiet start-p withot noise generated by the transformer Chip-over temperatre protection implemented (thermal shtdown) On-chip ringing sppression circit against parasitic oscillations of the transformer AGC-voltage redction at low load The IC TDA controls the MOS-power transistor and performs all necessary control and protection fnctions in free rnning flyback converters. Becase of the fact that a wide load range is achieved, this IC is applicable for consmer as well as indstrial power spplies. The serial circit and primary winding of the flyback transformer are connected in series to the inpt voltage. Dring the switch-on period of the transistor, energy is stored in the transformer. Dring the switchoff period the energy is fed to the load via the secondary winding. By varying switch-on time of the power transistor, the IC controls each portion of energy transferred to the secondary side sch that the otpt voltage remains nearly independent of load variations. The reqired control information is taken from the inpt voltage dring the switch-on period and from a reglation winding dring the switch-off period. A new cycle will start if the transformer has transferred the stored energy completely into the load. In the different load ranges the switched-mode power spply (SMPS) behaves as follows: No load operation The power spply is operating in the brst mode at typical 20 to 40 khz. The otpt voltage can be a little bit higher or lower than the nominal vale depending of the design of the transformer and the resistors of the control voltage divider. Nominal operation The switching freqency is redced with increasing load and decreasing AC-voltage. The otpt voltage is only dependent on the load. Overload point Maximal otpt power is available at this point of the otpt characteristic. Overload The energy transferred per operation cycle is limited at the top. Therefore the otpt voltages declines by secondary overloading.

56 6 2 5 Reference Voltage typ. 3V Spply Voltage Monitor V 2B Primary Crrent Voltage Converter Otpt Stage and Crrent Control Circit 4 1 V REF V 6min V 6A V 6E V 6max Crrent Sorce V R Control & Overload Amplifier V St Start Plse Generator Stop Comparator Logic Fold-back Point Correction V v Primary Voltage Spervision Zero Crossing Detector Pin Definitions and Fnctions Pin No. Fnction Information Inpt Concerning Secondary Voltage By comparing the reglating voltage - obtained trom the reglating winding of the transformer - with the internal reference voltage, the otpt implse width on pin 5 is adjsted to the load of the secondary side (normal, overload, short-circit, no load). Information Inpt Regarding the Primary Crrent The primary crrent rise in the primary winding is simlated at pin 2 as a voltage rise by means of external RC-element. When a voltage level is reached thats derived from the reglating voltage at pin 1, the otpt implse at pin 5 is terminated. The RC-element serves to set the maximm power at the overload point set. Inpt for Primary Voltage Monitoring In the normal operation V3 is moving between the thresholds V 3H and V 3L (V 3H > V 3 > V 3L ). V 3 < V 3L : SMPS is switched OFF (line voltage too low). V 3 > V 3H : Compensation of the overload point reglation (controlled by pin 2) starts at V 3H : V 3L = 1.7. Grond Otpt Psh-pll otpt provides ±1 A for rapid charge and discharge of the gate capacitance of the power MOS-transistor. Spply Voltage Inpt A stable internal reference voltage V REF is derived from the spply voltage also the switching thresholds V 6A, V 6E, V 6 max and V 6 min for the spply voltage detector. If V 6 > V 6E then V REF is switched on and switched off when V 6 < V 6A - In addition the logic is only enable for V 6 min < V 6 < V 6 max. Inpt for Soft-Start Start-p will begin with short plses by connecting a capacitor from pin 7 to grond. Inpt for the Oscillation Feedback After starting oscillation, every zero transition of the feedback voltage (falling edge) throgh zero (failing edge) triggers an otpt plse at pin 5. The trigger threshold is at + 50 mv typical.

57 TDA6111Q Video Otpt Amplifier FEATURES High bandwidth and high slew rate Black-crrent measrement otpt for Atomatic Black-crrent Stabilization (ABS) Two cathode otpts; one for DC crrents, and one for transient crrents A feedback otpt separated from the cathode otpts Internal protection against positive appearing Cathode-Ray Tbe (CRT) flashover discharges ESD protection Simple application with a variety of color decoders Differential inpt with a designed maximm common mode inpt capacitance of 3 pf, a maximm differential mode inpt capacitance of 0.5 pf and a differential inpt voltage temperatre drift of 50 µv/k Defined switch-off behavior. GENERAL DESCRIPTION The TDA6111Q is a video otpt amplifier with 16 MHz bandwidth. The device is contained in a single in-line 9-pin medim power (DBSSMPF) package, sing high-voltage DMOS technology, intended to drive the cathode of a color CRT. V ip v DDL 1 2 U v in 3 PINNING Pin Symbol Fnction 1 V ip non - inverting voltage inpt 2 v DDL spply voltage LOW 3 v in inverting voltage inpt 4 GND grond, sbstrate 5 I om black crrent measrement otpt 6 v DDH spply voltage HIGH 7 V cn cathode transient voltage otpt 8 V oc cathode DC voltage otpt 9 V fb feedback voltage otpt GND I om v DDH V cn V oc V fb TDA 6111Q Pin Configration QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS Min. Typ. Max. Unit v DDH high level spply voltage V v DDL low levelspply voltage 0-14 W I DDH qiescent high voltage spply crrent V oc = 0.5V DDH ma I DDL qiescent low voltage spply crrent V oc = 0.5V DDH ma V i inpt voltage 0 - V DDL V V oc, V fb otpt voltage V DDL - V DDH V T stg storage temperatre o C T amb operating ambient temperatre o C

58 spply voltage inpt HIGH fedback otpt 6 9 7V MIRROR MIRROR FOLLOWERS V bias 7 cathode transient otpt C par inverting inpt non-inverting inpt DIFFERENTIAL STAGE TDA6111Q 8 5 cathode DC otpt black crrent measrement otpt MIRROR CURRENT SOURCE MIRROR 4 2 grond (sbstrate) spply voltage inpt LOW A-Block diagram LIMITING VALUES In accordance with the Absolte Maximm Rating System (IEC 134). Voltages measred with respect to GND (pin 4); crrents as specified in A; nless otherwise specified. SYMBOL PARAMETER CONDITIONS Min. Max. Unit v DDH high level spply voltage V v DDL low levelspply voltage 0 14 W V i inpt voltage 0 V DDL V V IDM differential mode inpt voltage V V om measrement otpt voltage 0 V DDL V oc cathode otpt voltage V DDL V DDH V V fb feedback otpt voltage V DDL V DDH V I in, I ip inpt crrent 0 1 ma I cosml low-non repetitive peak cathode otpt crrent flashover discharge = 100µC 0 5 A I cosmh high-non repetitive peak cathode otpt crrent flashover discharge = 100nC 0 10 A P tot total power dissipation 0 4 W T stg storage temperatre o C T j jnction temperatre o C V es electrostatic handling hman body model (HBM) - >1500 V machine model (MM) - >400 V

59 Cathode otpt The cathode otpt is protected against peak crrents (cased by positive voltage peaks dring highresistance flash) of 5 A maximm with a charge content of 100 µc. The cathode is also protected against peak crrents (cased by positive voltage peaks dring low-resistance flash) of 10 A maximm with a charge content of 100 nc. Flashover protection The TDA6111Q incorporates protection diodes against CRT flashover discharges that clamp the cathode otpt pin to the V DDH pin. The DC spply voltage at the V DDH Pin has to be within the operating range of 180 to 210 V to ensre that the Absolte Maximm Rating for V DDH of 250 V will not be exceeded dring flashover. To limit the diode crrent, an external 680 R carbon high-voltage resistor in series with the cathode otpt and a 2 kv spark gap are needed (for this resistor-vale, the CRT has to be connected to the main PCB). This addition prodces an increase in the rise and fall times of approximately 5 ns and a decrease in the overshoot of approximately 4%. VDDH to GND mst be decopled: 1. With a capacitor >20 nf with good HF beha vior (e.g. foil). This capacitance mst be placed as close as possible to pins 6 and 4, bt definitely within 5 mm. 2. With a capacitor >10 CIF on the pictre tbe base print (common for three otpt sta ges). VDDL to GND mst be decopled: 1. With a capacitor >20 nf with good HF behavior (e.g. ceramic). This capacitance mst be placed as close as possible to pins 2 and 4, bt definitely within 10 mm. Switch-off behavior The switch-off behavior of the TDA6111Q is defined: when the bias crrent becomes zero, at V DDL (pin 2) lower than approximately 5 V, all the otpt pins (pins 7, 8 and 9) will be high.

60 M27C Megabit (256 kx8) UV EPROM FEATURES Fast access time: 55ns Low Power CMOS Consmption: Active Crrent: 30 ma Standby Crrent 100 µa Programming voltage: 12.75V Electronic signatre for Atomated programming Programming times of arond 24 sec. (Presto II algorithm) 32 1 FDIP32W (F) DESCRIPTIONS The M27C2001 is a high speed 2 Megabit UV erasable and electrically programmable EPROM ideally sited for microprocessor systems reqiring large programs. It is organised as 262, 144 by 8 bits. The Window Ceramic Frit-Seal Dal-in-Line and Leadless Chip Carrier packages have transparent lids which allow the ser to expose the chip to ltraviolet light to erase the bit pattern. A new pattern can then be written to the device by following the programming procedre. For applications where the content is programmed only one time and erasre is not reqired, the M27C2001 is offered in both Plastic Leaded Chip Carrier and Plastic Thin Small Otline packages. SIGNAL NAMES Figre 1. Logic Diagram V CC V pp 18 8 A0-A17 P E G Q0-Q7 A0 - A17 Q0 - Q7 E G P Vpp Vcc Vss address npts data otpts chip enable otpt enable program program spply spply voltage grond V SS