Old Company Name in Catalogs and Other Documents

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1 To our customers, Old Company Name in Catalogs and Other Documents On April st, 2, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: April st, 2 Renesas Electronics Corporation Issued by: Renesas Electronics Corporation ( Send any inquiries to

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3 To all our customers Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April st 23. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices. Renesas Technology Corp. Customer Support Dept. April, 23

4 DESCRIPTION The M3554-XXXFP and M3555-XXXFP are TV screen display control IC which can be used to display information such as number of channels, the date and messages and program schedules on the TV screen. In particular, owing to the built-in SYNC-SEP (synchronous separation) circuit, the synchronous correction circuit, external circuits can be decrease and character turbulence that occurs when superimposing can be reduced. The processor is suitable for AV systems such as VTRs, LDs, and so on. It is a silicon gate CMOS process and M3554-XXXFP and M3555- XXXFP are housed in a 2-pin shrink SOP package. For M3554-FP/M3555-FP that are a standard ROM versions of respectively, the character pattern is also mentioned. FEATURES Screen composition characters lines, 32 characters 7 lines Number of characters displayed (Max.) Character composition dot matrix Characters available characters (M3554) characters (M3555) Character sizes available... 4 (horizontal) 4 (vertical) Display locations available Horizontal direction locations Vertical direction locations Blinking... Character units Cycle : approximately second, or approximately.5 seconds Duty : 25%, 5%, or 75% Data input... By the serial input function (6 bits) Coloring Background coloring (composite video signal) Blanking Total blanking (4 8 dots) Border size blanking Character size blanking Synchronizing signal Composite synchronizing signal generation (PAL, NTSC, M-PAL) 2 output ports ( digital line) Oscillation stop function It is possible to stop the oscillation for synchronizing signal generation Built-in half-tone display function Built-in reversed character display function Built-in synchronous correction circuit Built-in synchronous separation circuit PIN CONFIGURATION (TOP VIEW) CP TESTA CS SCK SIN AC VDD2 CVIDEO LECHA CVIN M3554-XXXFP M3555-XXXFP Outline 2P2Q-A VDD HOR CP2 OSCIN VSS P P TESTB TESTC VSS APPLICATION TV, VCR, Movie REV..2

5 PIN DESCRIPTION Symbol OSC TESTA CS SCK SIN Pin name Clock input Test pin input Chip select input Serial clock input Serial data input Input/ Output Input Input Input Input Function This is the filter output pin. This is the pin for test. Connect this pin to GND during normal operation. This is the chip select pin, and when serial data transmission is being carried out, it goes to L. Hysteresis input. Built-in pull-up resistor. When CS pin is L, SIN serial data is taken in when SCK rises. Hysteresis input. Built-in pull-up resistor. This is the pin for serial input of data and addresses for the display control register and the display data memory. Hysteresis input. Built-in pull-up resistor. AC VDD2 CVIDEO LECHA CVIN VSS TESTC TESTB P P VSS OSCIN CP2 HOR VDD Auto-clear input Power pin Composite video signal output Character level input Composite video signal input Earthing pin Test pin output Test pin input Port P output Port P output Earthing pin fsc input pin for synchronous signal generation Filter output Horizontal synchronizing signal input Power pin Input Output Input Input Output Output Input Output Input When L, this pin resets the internal IC circuit. Hysteresis input. Built-in pull-up resistor. Please connect to +5V with the analog circuit power pin. This is the output pin for composite video signals. It outputs 2VP-P composite video signals. In superimpose mode, character output etc. is superimposed on the external composite video signals from CVIN. This is the input pin which determines the white character color level in the composite video signal. This is the input pin for external composite video signals. In superimpose mode, character output etc. is superimposed on these external composite video signals. Please connect to GND using circuit earthing pin. This is the pin for test. Open this pin during normal operation. This is the pin for test. Connect this pin to GND during normal operation. This pin outputs the port output or BLNK (character background) signal. This pin outputs the port output or CO(character) signal. Please connect to GND using circuit earthing pin (Analog side). This is the input pin for the sub-carrier frequency (fsc) for generating a synchronous signal. A frequency of 3.58MHz is needed for NTSC, and a frequency of 4.434MHz in needed for PAL and 3.576MHz is needed for M-PAL. Filter output pin 2. This is the input pin for external composite video signals. This pin inputs the external video signal clamped sync-chip to.5v, and internally carries out synchronous separation. Please connect to +5V with the digital circuit power pin. 2

6 BLOCK DIAGRAM CS SCK SIN TESTA TESTB VDD AC VSS VSS VDD2 Data control circuit Address control circuit Display control register Display RAM Display character ROM CP HOR 9 Clock oscillation circuit SYNC-SEP circuit H counter Oscillation circuit for synchronizing signal generation Timing generator Display location detection circuit Timing generator Reading address control circuit Display control circuit NTSC PAL M-PAL video output circuit Shift register Port output circuit Blinking circuit 3.58MHz(NTSC) 4.434MHz(PAL) 3.576MHz(M-PAL) OSCIN CP2 CVIDEO CVIN LECHA TESTC P P I/O control circuit

7 MEMORY CONSTITUTION Address 6 to EF6 are assigned to the display RAM, address F6 to F86 are assigned to the display control registers. The internal circuit is reset and all display control registers (address F6 to F86) are set to and display RAM (address 6 to EF6) are RAM erased when the AC pin level is L. When using M3554-XXXFP, set in any of DA7, DAD through DAF of addresses 6 through EF6, and of DAE and DAF of addresses F6 through F86. Setting the blank code FF6 as a character code is an exception. When using M3555-XXXFP, set in any of DAD through DAF of addresses 6 through EF6, and of DAE and DAF of addresses F6 through F86. TESTn (n : a number) is MITSUBISHI test memory, so be sure to observe the setting conditions. Address 6 EF6 F6 F6 F26 F36 F46 F56 F66 F76 F86 Display control register Display RAM DA DA DA F E D DA DA DA DA DA DA DA DA DA DA DA DA DA C B A REV BLINK B G R C6 C5 C4 C3 C2 C C Reverse Blinking Character color Character code REV BLINK B G R C6 C5 C4 C3 C2 C C TEST5 TEST4 TEST3 TEST2 TEST TEST SYSEP SYSEP SEPV SEPV PTD PTD PTC PTC TEST2 TEST2 TEST9 TEST8 TEST7 TEST6 HP7 HP6 HP5 HP4 HP3 HP2 HP HP TEST27 TEST26 TEST25 TEST24 TEST23 TEST22 VP7 VP6 VP5 VP4 VP3 VP2 VP VP TEST33 TEST32 TEST3 TEST3 TEST29 TEST28 VSZ2 VSZ2 VSZ VSZ HSZ2 HSZ2 HSZ HSZ TEST36 TEST35 TEST34 SPACE DSP9 DSP8 DSP7 DSP6 DSP5 DSP4 DSP3 DSP2 DSP DSP TEST42 TEST4 TEST4 TEST39 TEST38 TEST37 EQP PALH MPAL INT/NON N/P BLINK2 BLINK BLINK TEST43 TEST2 TEST TEST LBLACK LIN24/32 BLKHF BB BG BR LEVEL PHASE2 PHASE PHASE TEST46 TEST45 RGBON TEST44 CL7/8 CBLINK CURS7 CURS6 CURS5 CURS4 CURS3 CURS2 CURS CURS LEVEL TEST5 TEST5 TEST49 TEST48 TEST47 RAMERS DSPON STOP STOPIN SCOR EX BLK BLK Fig. Memory constitution (M3554-XXXFP) Address 6 EF6 F6 F6 F26 F36 F46 F56 F66 F76 F86 Display control register Display RAM DA DA DA F E D DA DA DA DA DA DA DA DA DA DA DA DA DA C B A REV BLINK B G R C7 C6 C5 C4 C3 C2 C C Reverse Blinking Character color Character code REV BLINK B G R C7 C6 C5 C4 C3 C2 C C TEST5 TEST4 TEST3 TEST2 TEST TEST SYSEP SYSEP SEPV SEPV PTD PTD PTC PTC TEST2 TEST2 TEST9 TEST8 TEST7 TEST6 HP7 HP6 HP5 HP4 HP3 HP2 HP HP TEST27 TEST26 TEST25 TEST24 TEST23 TEST22 VP7 VP6 VP5 VP4 VP3 VP2 VP VP TEST33 TEST32 TEST3 TEST3 TEST29 TEST28 VSZ2 VSZ2 VSZ VSZ HSZ2 HSZ2 HSZ HSZ TEST36 TEST35 TEST34 SPACE DSP9 DSP8 DSP7 DSP6 DSP5 DSP4 DSP3 DSP2 DSP DSP TEST42 TEST4 TEST4 TEST39 TEST38 TEST37 EQP PALH MPAL INT/NON N/P BLINK2 BLINK BLINK TEST43 TEST2 TEST TEST LBLACK LIN24/32 BLKHF BB BG BR LEVEL PHASE2 PHASE PHASE TEST46 TEST45 RGBON TEST44 CL7/8 CBLINK CURS7 CURS6 CURS5 CURS4 CURS3 CURS2 CURS CURS LEVEL TEST5 TEST5 TEST49 TEST48 TEST47 RAMERS DSPON STOP STOPIN SCOR EX BLK BLK Fig. 2 Memory constitution (M3555-XXXFP) 4

8 SCREEN CONSTITUTION The screen lines and rows are determined from each address of the display RAM. The screen consitution (24 characters lines) is shown in Figure 3 the screen constitution (32 characters 7 lines) is shown in 4. Rows Lines A6 B6 C6 D6 E6 F A6 B6 C6 D6 E6 F A6 2B6 2C6 2D A6 3B6 3C6 3D6 3E6 3F A6 4B6 4C6 4D6 4E6 4F A6 5B6 5C6 5D A6 6B6 6C6 6D6 6E6 6F A6 7B6 7C6 7D6 7E6 7F A6 8B6 8C6 8D A6 9B6 9C6 9D6 9E6 9F6 A6 A6 A26 A36 A46 A56 8 A86 A96 AA6 AB6 AC6 AD6 AE6 AF6 B6 B6 B26 B36 B46 B56 B66 B76 B86 B96 BA6 BB6 BC6 BD6 9 C6 C6 C26 C36 C46 C56 C66 C76 C86 C96 CA6 CB6 CC6 CD6 CE6 CF6 D6 D6 D26 D36 D46 D56 D86 D96 DA6 DB6 DC6 DD6 DE6 DF6 E6 E6 E26 E36 E46 E56 E66 E76 E86 E96 EA6 EB6 EC6 ED6 Note : The hexadecimal numbers in the boxes show the display RAM address. Fig. 3 Screen constitution (24 characters lines) A6 B6 C6 D6 E6 F A6 2B6 2C6 2D6 2E6 2F A6 4B6 4C6 4D6 4E6 4F A6 6B6 6C6 6D6 6E6 6F A6 8B6 8C6 8D6 8E6 8F A6 A6 A26 A36 A46 A56 A66 A76 A86 A96 AA6 AB6 AC6 AD6 AE6 AF6 B6 B6 B26 B36 B46 B56 7 C6 C6 C26 C36 C46 C56 C66 C76 C86 C96 CA6 CB6 CC6 CD6 CE6 CF6 D6 D6 D26 D36 D46 D E E E6 A66 BE6 D66 EE B66 D F F F6 A76 BF6 D76 EF B76 D B86 3 D86 F6 26 E6 96 3F E F E6 996 B96 D96 27 A6 3A6 5A6 7A6 9A6 BA6 DA6 28 B6 3B6 5B6 7B6 9B6 BB6 DB6 29 C6 3C6 5C6 7C6 9C6 BC6 DC6 3 D6 3D6 5D6 7D6 9D6 BD6 DD6 7F6 7E6 9F6 9E6 BF6 BE6 DF6 DE6 Rows Lines Notes. The hexadecimal numbers in the boxes show the display RAM address. Notes 2. When 32 characters 7 lines are displayed, set blank code FF6 to character code of addresses E6 to EF6. Fig. 4 Screen constitution (32 characters 7 lines) 5

9 Display RAM DESCRIPTION Display RAM Address 6 to EF6 DA Contents Name ~C Status Function Remarks C Set ROM-held character code of a character needed (LSB) to display C C2 C3 C4 C5 6 C6 (MSB) A B R G B BLINK Set to during normal operation When RGBON=, set background color by character No blinking (Note 2) Refer to supplemental Refer to BLINK2 to Can not be used unit. Blinking explanation (3). (address F56) C REV Normal character Reversed character Notes. Resetting at the AC pin RAM-erases the display RAM, and the status turns as indicated by the mark around in the status column. 2. Set to only when setting a blank code. When using M3555-XXXFP, DA7 is C7 (MSB). 6

10 Display control register () Address F6 DA ~D Register Status Contents Function Remarks PTC P output (port ) BLNK output Port output control PTC P output (port ) CO output Refer to supplemental explanation (4). 2 PTD It is negative polarity at P output L, BLINK output. It is positive polarity at P output H, BLINK output. Control the port data 3 PTD It is negative polarity at P output L, CO output. It is positive polarity at P output H, CO output. Refer to supplemental explanation (4). 4 SEPV It should be fixed to. Specifies the vertical synchronous separation criterion 5 SEPV It should be fixed to. Refer to supplemental explanation (). 6 7 SYSEP SYSEP SYSEP SYSEP Bias potential.75v Specifies the sync-bias potential 8 TEST It should be fixed to. 9 TEST It should be fixed to. A B TEST2 TEST3 It should be fixed to. It should be fixed to. C TEST4 It should be fixed to. D Note: The mark Notes TEST5 It should be fixed to. around the status value means the reset status by the L level is input to AC pin. 7

11 (2) Address F6 DA ~D Register Status Contents Function Remarks HP (LSB) HP HP2 HP3 HP4 HP5 Let horizontal display start position be HS, HS = T (Σ 2 n HPn+6) VERT 7 n= HS HOR VS Character displaying area Set the horizontal display start position by use of HP7 through HP. HP7 to HP = () to () setting is forbidden. It can be set this up to 24 steps in increments of one T. 6 HP6 T : The oscillation cycle of display clock 7 HP7 (MSB) 8 TEST6 It should be fixed to. 9 TEST7 It should be fixed to. A TEST8 It should be fixed to. B TEST9 It should be fixed to. C TEST2 It should be fixed to. D TEST2 It should be fixed to. 8

12 (3) Address F26 DA ~D Register Status Contents Function Remarks VP (LSB) VP VP2 VP3 VP4 VP5 Let vertical display start position be VS, VS = H Σ 2 n VPnVS VERT 7 n= HS HOR VS Character displaying area Set the vertical display start position by use of VP7 through VP. VP7 to VP = () to () setting is forbidden. It can be set this up to 249 steps in increments of one H. VP7 to VP = () to () setting is forbidden. 6 7 VP6 VP7 (MSB) H : The oscillation cycle of horizontal synchronous signal 8 TEST22 It should be fixed to. 9 TEST23 It should be fixed to. A TEST24 It should be fixed to. B TEST25 It should be fixed to. C TEST26 It should be fixed to. D TEST27 It should be fixed to. 9

13 (4) Address F36 DA ~D Register Status Contents Function Remarks HSZ HSZ HSZ HSZ Horizontal direction size T/dot 2T/dot 3T/dot 4T/dot Character size setting in the horizontal direction for the first line. 2 3 HSZ2 HSZ2 HSZ2 HSZ2 Horizontal direction size T/dot 2T/dot 3T/dot 4T/dot Character size setting in the horizontal direction for the 2nd line to th line. 4 5 VSZ VSZ VSZ VSZ Vertical direction size H/dot 2H/dot 3H/dot 4H/dot Character size setting in the vertical direction for the first line. 6 7 VSZ2 VSZ2 VSZ2 VSZ2 Vertical direction size H/dot 2H/dot 3H/dot 4H/dot Character size setting in the vertical direction for the 2nd line to th line. 8 TEST28 It should be fixed to. 9 TEST29 It should be fixed to. A TEST3 It should be fixed to. B TEST3 It should be fixed to. C TEST32 It should be fixed to. D TEST33 It should be fixed to.

14 (5) Address F46 DA ~D Register Status Contents Function Remarks DSP DSP DSP2 DSP3 DSP4 BLK BLK DSPn= DSPn= Matrix-outline border size Matrix-outline size Border size Character size Matrix-outline size Border size Character size Matrix-outline size Depends on BLK and BLK (address F86) DSPn in the generic name for DSP to DSP9. DSP to DSP9 are each controlled independently. Set the display mode of line. Set the display mode of line 2. Set the display mode of line 3. Set the display mode of line 4. Set the display mode of line 5. 5 DSP5 Set the display mode of line 6. 6 DSP6 Set the display mode of line 7. 7 DSP7 Set the display mode of line 8. 8 DSP8 Set the display mode of line 9. 9 DSP9 Set the display mode of line. A SPACE Normal display Put a space line between line 2 and line 3, and between line 8 and line 9. Put a space line between line 2 and line 3 in displaying 32 characters. B TEST34 It should be fixed to. C TEST35 It should be fixed to. D TEST36 It should be fixed to.

15 (6) Address F56 DA Contents Register ~D Status Function BLINK BLINK Duty BLINK Blinking off 25% 5% BLINK 75% Division of vertical synchronizing signal into /64. Cycle approximately second. 2 BLINK2 Division of vertical synchronizing signal into /32. Cycle approximately.5 second. _ NTSC, M-PAL mode 3 N/P PAL mode _ Interlace 4 INT/NON Non interlace _ N/P MPAL Synchronous mode NTSC 5 MPAL M-PAL PAL Not available PALH INT/NON Number of scanning lines 625H lines 6 PALH 626H lines 627H lines 628H lines Not include the equivalent pulse. 7 EQP Include the equivalent pulse. It should be fixed to. 8 TEST37 It should be fixed to. 9 TEST38 It should be fixed to. A TEST39 It should be fixed to. B TEST4 It should be fixed to. C TEST4 It should be fixed to. D TEST42 Note. To blink a character, set to DAB (the blinking bit) of the display RAM. Remarks Blinking duty ratio can be altered. (Note) Blinking cycle can be altered. Refer to register MPAL Scanning lines control (only in internal synchronization) Synchronizing signal is selected _ with this register and N/P register. It should be fixed to at NTSC Effective only at non-interlace 2

16 (7) Address F66 DA ~D Register Status Contents Function Remarks PHASE PHASE2 PHASE PHASE Raster Black Red Raster color setting Refer to supplemental explanation (2) about video signal level PHASE Green Yellow Blue 2 PHASE2 Magenta Cyan White 3 LEVEL Internal bias off Internal bias on Generates bias potential for composite video signals 4 5 BR BG BB BG BR Character background color Black Red Green Yellow Character background color setting. Refer to supplemental explanation (2) about video signal level Blue 6 BB Magenta Cyan White The halftone displaying OFF in superimpose This register is available in the 7 BLKHF The halftone displaying ON in superimpose superimpose displaying only. (Note) _ 24 characters lines display 8 LIN24/32 32 characters 7 lines display Blanking level I 2.3V Set a blackness level 9 LBLACK Blanking level II 2.V It should be fixed to. A TEST It should be fixed to. B TEST It should be fixed to. C TEST2 D TEST43 It should to be fixed to. Note. It is neccessary to input the external composite video signal to the CVIN pin, and externally connect a to 2Ω register in series. 3

17 (8) Address F76 DA ~D Register Status Contents Function Remarks CUR CUR CUR2 CUR3 CUR4 CUR5 Let cursor displaying address be CURS, 7 CURS = Σ 2 n CURn n= Set the cursor displaying address by use of CUR7 through CUR. CUR7 to CUR () setting is forbidden under 24 characters display. CUR7 to CUR () setting is forbidden under 32 characters display. Set CUR7 to CUR = () under cursor is not be displayed. The cursor displaying address (CURS) is correspond to display construction. 6 CUR6 7 CUR7 8 CBLINK No blinking Blinking The cursor blinking setting 9 _ CL7/8 Cursor displaying at the 7th dot by vertical direction. Cursor displaying at the 8th dot by vertical direction. Refer to character construction. A TEST44 It should be fixed to. B RGBON Normal Character background coloring Refer to supplemental explanation (3). C TEST45 It should be fixed to. D TEST46 It should be fixed to. 4

18 (9) Address F86 DA ~D Register Status Contents Function Remarks BLK BLK BLK DSPn= Matrix-outline border size Border size DSPn= Matrix-outline size Character size Display mode (BLNK output) variable BLK Matrix-outline size Character size Border size Matrix-outline size A B C D EX SCOR STOPIN STOP DSPON RAMERS TEST47 TEST48 TEST49 TEST5 TEST5 LEVEL External synchronization Internal synchronization Superimpose monotone display Superimpose coloring display (only NTSC) fsc input mode Oscillation VCO for display Stop oscillation VCO for display Display OFF Display ON RAM not erased RAM erased It should be fixed to. It should be fixed to. It should be fixed to. It should be fixed to. It should be fixed to. Internal bias OFF Internal bias ON Synchronizing signal switching (Note) setting is forbidden at internal synchronous or PAL, M-PAL mode displaying. OSCIN oscillation control Control oscillation VCO for display This register does not exist (Note 3). Generates bias potential for synchronous separation. Notes. In dealing with the internal synchronization, cut off external video signals outside the IC. The leakage of external input video signals can be avoided. Notes 2. In displaying color superimposition, enter into the OSCIN pin the fsc signal that phase-synchronizes with the color burst of the composite video signals (input to the CVIN pin). Notes 3. Erases all the display RAM. The character code turns to blank-ff6, the encode data bit and the blinking bit turn to respectively, and reversed character bit turns to. 5

19 Supplemental explanation about display control register () How to effect synchronous separation from composite video signals Synchronous separation is effected as follows depending on the width of L-level of the vertical synchronous period.. Less than 8.4µs Not to be determined to be a vertical synchronous signal. 2. Equal to or higher than 8.4µs but less than 5.6µs When two clocks continue, if take place, it is L period is determined to be a vertical synchronization signal. 3. Equal to or higher than 5.6µs It is L period is determined to be a vertical synchronous signal with no condition. The determination is made at the timing indicated by V in Fig.4 either in case 2 or in case 3. Sequence of synchronizing pulse Composite video signal Equalizing pulse 8.4µs 5.6µs 8.4µs V Vertical synchronous signal Fig. 5 The method of synchronous separation from composite video signal. 6

20 (2) Video signal level Color Sync-chip Pedestal Color burst Black Red Green Yellow Blue Magenta Cyan White 27 6 ± 2 /6 /6 ± 2 /6 7 /6 ± 2 /6 /6 ± 2 /6 23 /6 ± 2 /6 VDD : 5.V, Ta : 25 C Phase angle (rad) Brightness level (V) Amplitude ratio (to color burst) NTSC method PAL, M-PAL method Min..3.9 Typ Max Min. Typ. Max. ± 4 / /6 ± 2 /6 ± 7 /6 ± 2 / ± ± 5 /6 ± 2 / ± /6 ± 2 /6 5 /6 ± 2 /6 ± /6 ± 2 /6 ± 9 /6 ± 2 / R-Y CB RS CB / 4 B-Y - / 4 CB2 RS2 CB Color burst under NTSC CB,CB2 Color burst under PAL or M-PAL RS,RS2 Color subcarrier under PAL or M-PAL Fig. 6 Bector phases (3) Setting RGBON (address F76) RGBON =... Sets background colors depending on BB, BG, and BR (address F66), screen by screen. RGBON =... Sets background colors depending on R, G, B (address 6 to EF6), character by character. The color setting is shown below. Color Setting B G R Color Black Red Green Yellow Blue Magenta Cyan White 7

21 (4) Port output and BLNK, CO output BLNK (CO) PTD (PTD) PTC (PTC) Output Polarity switching PTD (PTD) Select PTD,, PTC, (Address F6) Fig. 7 Example of port control (5) Setting conditions for oscillating or stopping the display clock STOP DSPON CS pin at display clock operating L at display clock stop H STOP, CDSPON (Address F86) (6) Setting condition at LEVEL, LEVEL LEVEL Operation state (Character display) Now-working condition Internal synchronous External synchronous (no characters are displayed) LEVEL (address F66), LEVEL (address F86) 8

22 DISPLAY FORMS have the following four display forms as the blanking function, when CO and BLNK are output. () Character size : Blanking same as the character size. (2) Border size : Blanking the background as a size from character. (3) Matrix-outline size: Blanking the background as a size from all character font size. (4) Matrix-outline : Blanking the background as a size from all border size character font size. Border display. This display format allows each line to be controlled independently, so that two kinds of display formats can be combined on the same screen. 2 dots 2 dots 4 dots 4 dots Scanning line 8 dots CO BLNK CVIDEO a a a a () Character size (2) Border size (3) Matrix-outline size (4) Matrix-outline border size Note: In this case, the output polarity that CO and BLNK is positive. a: Background carrier color signal Fig. 8 Display forms at each display mode 9

23 DATA INPUT EXAMPLE Data of display RAM and display control registers can be set by then serial input function. Owing to automatic address increment, not necessary to enter addresses for the second and subsequent data. In automatically, the next of address F86 is assigned to address 6. Fig. 9 shows an example of data setting by the serial input function (M3554-XXXFP), Fig. shows an example of data setting by the serial input function (M3555-XXXFP). NO. Data contewts Address/Data Spplemental explanation Address(F86) Address setting DA DA DA F E D DA DA DA DA DA DA DA DA DA DA DA DA DA C B A Data(F86) Display OFF 3 Data(6) REV BLINK B G R C6 C5 C4 C3 C2 C C 4 24 Data(6) Data(EE6) Display RAM address 6 to EF6 setting REV BLINK REV BLINK B G R B G R C6 C5 C4 C3 C2 C C C6 C5 C4 C3 C2 C C 242 Data(EF6) REV BLINK B G R C6 C5 C4 C3 C2 C C 243 Data(F6) Register PTD PTD PTC PTC 244 Data(F6) address F6 to F76 setting HP 7 HP 6 HP 5 HP 4 HP 3 HP 2 HP HP 245 Data(F26) VP 7 VP 6 VP 5 VP 4 VP 3 VP 2 VP VP 246 Data(F36) VSZ VSZ VSZ VSZ HSZ HSZ HSZ HSZ Data(F46) DSP DSP DSP DSP DSP DSP DSP DSP DSP DSP SPACE Data(F56) EQP PALH MPAL INT /NON N/P BLINK BLINK BLINK Data(F66) TEST TESTTEST LIN LEVEL PHASE PHASE PHASE 2 LBLACK 24/32 BLKHF BB BG BR 2 25 Data(F76) RGBON CL CURS CURS CURS CURS CURS CURS CURS CURS 7/8 CBLINK LEVEL RAM 25 Data(F86) Display ON STOP STOP DSPON SCOR BLK BLK EX ERS IN Fig. 9 Example of data setting by the serial input function (M3554-XXXFP) 2

24 NO. Data couteuts Address/Data Supplemental explauation Address(F86) Address setting DA DA DA F E D DA DA DA DA DA DA DA DA DA DA DA DA DA C B A Data(F86) Display OFF 3 Data(6) REV BLINK B G R C7 C6 C5 C4 C3 C2 C C 4 24 Data(6) Data(EE6) Display RAM address 6 to EF6 setting REV BLINK REV BLINK B G R B G R C7 C7 C6 C5 C4 C3 C2 C C C6 C5 C4 C3 C2 C C Data(EF6) Data(F6) Data(F6) Data(F26) Data(F36) Data(F46) Data(F56) Data(F66) Data(F76) Data(F86) Register address F6 to F76 setting Display ON REV BLINK B G R C7 C6 C5 C4 C3 C2 C C PTD PTD PTC PTC HP 7 HP 6 HP 5 HP 4 HP 3 HP 2 HP HP VP 7 VP 6 VP 5 VP 4 VP 3 VP 2 VP VP VSZ VSZ VSZ VSZ HSZ HSZ HSZ HSZ SPACE DSP DSP DSP DSP DSP DSP DSP DSP DSP DSP EQP PALH MPAL INT BLINK BLINK BLINK /NON N/P 2 TEST TEST TEST LIN LEVEL PHASE PHASE PHASE 2 LBLACK 24/32 BLKHF BB BG BR 2 RGBON CL CURS CURS CURS CURS CURS CURS CURS CURS 7/8 CBLINK LEVEL RAM STOP STOP DSPON SCOR BLK BLK EX ERS IN Fig. Example of data setting by the serial input function (M3555-XXXFP) 2

25 SERIAL DATA INPUT TIMING () The address consists of 6 bits. (2) The data consists of 6 bits. (3) The 6 bits in the SCK after the CS signal has fallen are the address, and for succeeding input data, the address is incremented every 6 bits. CS SCK SIN LSB MSB LSB MSB LSB MSB Address (6 bit) Data N (6 bit) Data N+ (6 bit) N =, 2, 3 Fig. Serial input timing 22

26 CHARACTER FONT Images are composed on a 2 8 dot matrix, and characters can be linked vertically and horizontally with other characters to allow the display the continuous symbols. Character code FF6 is so fixed as to be blank and to have no background, thus cannot assign a character font to this code. () Border display (set by register BLK, (address F86)) 2 dots When the character extends to the top dot of the matrix, no border is left at the top. 8 dots When the character extends to the bottom (8th) dot of the matrix, no border is left at the bottom. Note: Hatching represents border. (2) Cursor display (Border display) Character Note: When the cursor positioning at the bottom (8th) dot, no border is left at the bottom. Register CL7/8 (address F76) = Positioning the cursor at the 7th dot. Register CL7/8 = Positioning the cursor at the 8th dot. Fig. 2 Character font and border 23

27 Note 4: Construct integral circuit by built-in 3kΩ of AC pin and an external condenser. Attention to supply voltage rise time about this CR constant. Note 5: External loop filter 2 constant is provisional valve. Note 6: Connect fsc frequency..3vp-p 4.Vp-p VOSCIN In displaying color superimposition, enter into the OSCIN pin the fsc signal that phase-synchronizes with the color burst of the composite video signals (input to the CVIN pin). NTSC = 3.58MHz PAL= 4.434MHz M-PAL= 3.576MHz PERIPHERAL CIRCUIT Note 7: In dealing with the internal synchronization, cut off external video signals outside the IC. The leakage of external input video signals can be avoided. External composite video signal input From microcomputer +7.V +5.V Note 3 Note P 47 µ Note Composite video signal input + 47µ k.5v +7.V 2.2k Note 7 22µ k.22µ Note 4 µ + +5.V +5.V µ µ µ µ µ 2 CP VDD 2 9 TESTA HOR CS SCK SIN AC VDD2 CVIDEO CP2 OSCIN VSS P P TESTB µ Delay circuit k.µ fsc 47P Note 6 Note LECHA TESTC CVIN VSS Note : Clamp sync chip to.5v. Note 2: Set basic electric potential in consid eration of dynamic range of the transistor. Note 3: External loop filter constant is provisional valve. Fig. 3 example of peripheral circuit 24

28 Precautions () Points to note in setting the display RAMs a) Be careful to the edges may sway depending on the combination of character s background color and raster color. Edge sway Fig. 4 Example of display b) If what display exceeds the display area in dealing with external synchronization, (if use double - size characters), set the character code of the addresses lying outside that display area blank code FF6. Inside of display Outside of display area 6 B6C6 76 Inside of display F6 2F6 Outside of display area C6 D86 D76 EF6 Set blank code FF6 to character code of Numbers are adresses part. Fig. 5 Example of display 25

29 (2) Before setting registers at the starting of system, be sure to reset the M3552-XXXSP/FP by applying L level to the AC pin. (3) Power supply noise When power supply noise is generated, the internal oscillator circuit does not stabilize, whereby causing horizontal jitters across the picture display. Therefore, connect a bypass capacitor between the power supply and GND. 3) Wait 2 ms (the period necessary for the internal oscillation circuit to stabilize) before entering data. 4) Set necessary data in other registers, and make the display RAM ready. (4) Synchronous correction action When switching channel or in the special playback mode (quick playback, rewinding, and so on) of VTR, effect of synchronous correction becomes strong, and distortion of a character is apt to occur because the continuity of video signal is suddenly switched. When the continuity of video signal is out of order, erasure of displayed characters is recommended in a extreme short time to raise the quality of displayed characters. (5) Notes on fsc signal input This IC amplifies the subcarrier frequency (fsc) signal (NTSC, M- PAL system: 3.58MHz, PAL system: 4.43MHz) input to the OSCIN pin (7-pin) and generates the composite video signal internally. The amplified fsc signal can be destabilized in the following cases. a) When the fsc signal is outside of recommended operating conditions. b) When the waveform of the fsc signal is distorted. c) When DC level in the fsc waveform fluctuates. When the amplified signal is unstable, the composite video signal generated inside the IC is also unstable in terms of synchronization with the subcarrier and phase. Consequently, this results in color flicker and lost synchronization when the composite video signal is generated. Make note of the fact that this may prevent a stable blue background from being formed. (6) Forbidding to stop entering the fsc signal This IC doesn t properly work if the fsc signal is not entered into the OSCIN pin (pin 7), so don t stop the fsc signal so as to work the IC. To stop the IC, turn the display off (set in the register DSPON (address F86).) (7) Forbidding to set data during the period in which the internal oscillation circuit stabilizes a) To start entering the fsc signal when its input is stopped. b) To start oscillating the oscillation circuit for display when its oscillation is stopped. (to assign to the register STOP (address F86) when it is assigned, or the like.) c) To turn on the internal bias when it is turned off. (to assign to the register LEVEL (address F86) when it is assigned.) There can be instances in which data are not properly set in the registers until the internal oscillation circuit stabilizes, so follow the steps in sequence as given below. ) Set in the register DSPON (address F86). (the display is turned off) 2) Effect the settings a), b), and c) given above. 26

30 TIMING REQUIREMENTS (Ta = 2 C to 7 C, VDD = 5±.25V, unless otherwise noted) Symbol Parameter tw(sck) SCK width 4 tsu(cs) CS setup time 2 th(cs) tsu(sin) th(sin) tword CS hold time SIN setup time SIN hold time word writing time Note. When oscillation stop at register STOR (address F86), V (field term) or more of tsu(cs) and th(cs) are needed. Min. Limits Typ. Max. Unit ns ns µs ns ns µs CS tw(cs) 2µs (min.) tsu(cs) tw(sck) tw(sck) th(cs) SCK tsu(sin) th(sin) SIN CS tword SCK Fig. 6 Serial input timing requirements 27

31 ABSOLUTE MAXIMUM RATINGS (VDD = 5V, Ta = 2 to 7 C, unless otherwise noted) Symbol Parameter Conditions VDD VI VO Pd Topr Tstg Supply voltage Input voltage Output voltage Power dissipation Operating temperature Storage temperature With respect to VSS Ta=25 C Ratings.3~6. VSS.3 VI VDD+.3 VSS VO VDD 3 2~7 4~25 Unit V V V mw C C RECOMMENDED OPERATING CONDITIONS (VDD = 5V, Ta = 2 to 7 C, unless otherwise noted) VDD VIH VIL Symbol VCVIN VOSCIN foscin fosc Display oscillation frequency fosc2 Notes. Noise component is within 3mV. Notes 2. fh: Horizontal synchronous frequency (MHz). Parameter Supply voltage H level input voltage AC, CS, SIN, SCK, TESTA, TESTB L level input voltage AC, CS, SIN, SCK, TESTA, TESTB CVIN, HOR Input voltage OSCIN (Note) Synchronous signal oscillation frequency (Duty 4~6%) 24 characters lines 32 characters 7 lines Min VDD.3VP-P Limits Typ. 5. VDD 2.VP-P fh 64 fh Max VDD.2 VDD 4.VP-P Unit V V V V V MHz MHz MHz ELECTRICAL CHARACTERISTICS (VDD = 5V, Ta = 25 C, unless otherwise noted) Symbol Parameter Test conditions Min. Limits Typ. Max. Unit VDD Supply voltage Ta= 2~7 C V IDD Supply current VDD=5.V 3 5 ma VOH H level output voltage P, P VDD=4.75V, IOH=.4mA 3.75 V VOL L level output voltage P, P VDD=4.75V, IOL=.4mA.4 V RI Pull-up resistance AC, CS, SCK, SIN, TESTB VDD=5.V 3 kω VIDEO SIGNAL INPUT CONDITIONS (VDD = 5V, Ta = 2 to 7 C, unless otherwise noted) Symbol Parameter Test conditions Min. Limits Typ. Max. Unit VIN-SC Composite video signal input clamp voltage Sync-chip voltage.5 V 28

32 Note for Supplying Power () Timing of power supplying to AC pin The internal circuit of M3554-XXXFP/ M3555-XXXFP is reset when the level of the auto clear input pin AC is L. This pin is hysteresis input with the pull-up resistor. The timing about power supplying of AC pin is shown in Figure 6. tw is the interval after the supply voltage becomes.8 VDD or more and before the supply voltage to the AC pin (VAC) becomes.2 VDD or more. After supplying the power (VDD and VSS) to M3554-XXXFP/ M3555-XXXFP, the tw time must be reserved for ms or more. Before starting input from the microcomputer, the waiting time (ts) must be reserved for 5ms after the supply voltage to the AC pin becomes.8 VDD or more. (2) Timing of power supplying to VDD pin and VDD2 pin The power need to supply to VDD and VDD2 at a time, though it is separated perfectly between the VDD as the digital line and the VDD2 as the analog line. Voltage [V] VDD.8 VDD Supply voltage VAC (AC pin input voltage).2 VDD tw ts Time t [s] Fig. 7 Timing of power supplying to AC pin PRECAUTION FOR USE Notes on noise and latch-up Connect a capacitor (approx.. F) between pins VDD and VSS at the shortest distance using relatively thick wire to prevent noise and latch up. ROM ORDERING METHOD Please submit the information described below when ordering Mask ROM. () ROM Order Confirmation Form... (2) Data to be written into mask ROM... EPROM (three sets containing the identical data) (3) Mark Specification Form... (4) Program for character font generating + froppy disk in which character data is input 29

33 STANDARD ROM TYPE : M3554-FP M3554-FP is a standard ROM type of M3554-XXXFP character patterns are fixed to the contents of Figure 8 to 9. 3

34 A6 B6 C6 D6 E6 F A6 B6 C6 D6 E6 F A6 2B6 2C6 2D6 2E6 2F A6 3B6 3C6 3D6 3E6 3F6 Fig. 8 M3554-FP character pattern () 3

35 A6 4B6 4C6 4D6 4E6 4F A6 5B6 5C6 5D6 5E6 5F A6 6B6 6C6 6D6 6E6 6F A6 7B6 7C6 7D6 7E6 7F6 Fig. 9 M3554-FP character pattern (2) 32

36 STANDARD ROM TYPE : M3555-FP M3555-FP is a standard ROM type of M3555-XXXFP Character patterns are fixed to the contents of Figure 2 to

37 A6 B6 C6 D6 E6 F A6 B6 C6 D6 E6 F A6 2B6 2C6 2D6 2E6 2F A6 3B6 3C6 3D6 3E6 3F6 Fig. 2 M3555-FP character pattern () 34

38 A6 4B6 4C6 4D6 4E6 4F A6 5B6 5C6 5D6 5E6 5F A6 6B6 6C6 6D6 6E6 6F A6 7B6 7C6 7D6 7E6 7F6 Fig. 2 M3555-FP character pattern (2) 35

39 A6 8B6 8C6 8D6 8E6 8F A6 9B6 9C6 9D6 9E6 9F6 A6 A6 A26 A36 A46 A56 A66 A76 A86 A96 AA6 AB6 AC6 AD6 AE6 AF6 B6 B6 B26 B36 B46 B56 B66 B76 B86 B96 BA6 BB6 BC6 BD6 BE6 BF6 Fig. 22 M3555-FP character pattern (3) 36

40 C6 C6 C26 C36 C46 C56 C66 C76 C86 C96 CA6 CB6 CC6 CD6 CE6 CF6 D6 D6 D26 D36 D46 D56 D66 D76 D86 D96 DA6 DB6 DC6 DD6 DE6 DF6 E6 E6 E26 E36 E46 E56 E66 E76 E86 E96 EA6 EB6 EC6 ED6 EE6 EF6 F6 F6 F26 F36 F46 F56 F66 F76 F86 F96 FA6 FB6 FC6 FD6 FE6 FF6 blank Fig. 23 M3555-FP character pattern (4) 37

41 PACKAGE OUTLINE 38

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