PI3EQX Gbps, 1-Lane, PCIe 2.0 ReDriver with I 2 C Programming Interface. Features. Description. Figure 1. Pin Diagram (Top Side View)

Transcription

1 5.Gbps, -Lane, PCIe. ReDriver with I C Programming Interface Features ÎÎPCIe. compatible ÎÎTwo 5.Gbps differential signal pairs ÎÎAdjustable Receiver Equalization ÎÎΩ Differential CML I/O s ÎÎPin Configured Output Emphasis and Output Swing Control ÎÎInput signal level detect and squelch for each channel ÎÎAutomatic Receiver Detect ÎÎLow Power : ~33mW (3.3V)/~5mW (.5V) ÎÎIndustrial Temp Support -4 C~ +85 C ÎÎStand-by Mode Power Down State ÎÎTwo power options: 3.3V or.5v ÎÎPackaging: -Pin TQFN (4x4mm) Figure. Pin Diagram (Top Side View) 3.3V /.5V Operation 3 33 /.5 OS_A \ SCL Figure. Block Diagram Signal Detection DNC /.5 EQ_B DE_B / A DE_A / SDA EQ_A DNC / GND OS_B / A 3.3 /.5 AI+ AI- EN# BO- BO+ AO+ AO- IC_EN BI- BI+ Description Pericom Semiconductor s PI3EQX58 is a low power, high performance 5. Gbps signal ReDriver designed specifically for the PCIe. protocol. The device provides programmable equalization, De-Emphasis, and output swing controls to optimize performance over a variety of physical mediums by reducing Inter-Symbol Interference. PI3EQX58 supports two Ω Differential CML data I/O s between the Protocol ASIC to a switch fabric, over cable, or to extend the signals across other distant data pathways on the user s platform. The integrated equalization circuitry provides flexibility with signal integrity of the signal before the ReDriver. A low-level input signal detection and output squelch function is provided for each channel. When the channels are enabled, EN# =, and operating, that channels input signal level (on xi+/-) determines whether the output is active. If the input signal level of the channel falls below the active threshold level (Vth-) then the outputs are driven to the common mode voltage. In addition to signal conditioning, when EN# =, the device enters a low power standby mode. The PI3EQX58 also includes a fully programmable I C interface. When I C control mode is enabled, IC_EN =, equalization, output swing, and de-emphasis settings can be adjusted by programming the related registers. Figure 3 PCIe. ReDriver PI3EQX67 PI3EQX77 CML Blade Server RXP Equalizer Limiting Amp CML TXP PCIe. Cable Blade Server RXN TXN EQ_x - Repeated times - Power Management

2 Pin Description Pin # Pin Name Type Description Input 3 EN# Input AI+ AI- BI+ BI- BO- BO+ AO- AO+ DNC /.5 EQ_B, EQ_A Output DNC / Power Input 8 DE_B / A Input CML input channels with selectable input termination between 5Ω to internal V bias or internal 6kΩ pull-down to GND. Chip Enable. When the pin is driven "Low", chip is in normal operation. When the pin is driven High, chip is in power down mode. With internal kω pull-down resistor. Selectable output termination between 5Ω to internal V bias kω to internal V bias, or Hi-Z. Do Not Connect /.5V Voltage Supply Set the equalization of two channels. These are Tri-level input pins. When set to "HIGH" the pin becomes Logic ""; when set to "open", the pin becomes "open", when set to "low", the pin becomes logic "". Please refer to Mode Adjustment on page 3. Set the de-emphasis of the output CML buffer for Channel B. This is a Tri-level input pins When set to "high", the pin becomes logic ""; when set to "open", the pin becomes "open"; when set to "low", the pin becomes logic "". Please refer to Mode Adjustment on page 3. 9 OS_B / A Input 3.3 /.5 Power 3 IC_EN Input 8 DE_A / SDA Input / Output This pin is also used for I C programming interface. When set to "high" or floating I C address bit A is set to "". When set to "low" I C address bit A is set to "". Set the output swing of Channel B. This is a Tri-level input pins When set to "HIGH", the pin becomes Logic ""; when set to "open", the pin becomes "open", when set to "low", the pin becomes logic "". This pin is also used for I C programming interface. When set to "high" or floating I C address bit A is set to "". When set to "low" I C address bit A is set to "". 3.3V Voltage Supply /.5V Voltage Supply I C Control Enable. When the pin is driven High, chip is in I C Control Mode. When the pin is driven Low, chip is in pin strap control mode. With internal kω pull-down resistor. Set the de-emphasis of the output CML buffer for Channel A. These is a Tri-level input pin. When set to "high", the pin becomes logic ""; when set to "open", the pin becomes "open"; when set to "low", the pin becomes logic "". Please refer to Mode Adjustment on page 3. This pin is also used as Data Line for I C programming interface 3.3V tolerant. Set the output swing of Channel A. This is a Tri-level input pins When set to "HIGH", the pin becomes Logic ""; when set to "open", the pin becomes "open", when set to "low", the pin becomes logic "". 9 OS_A / SCL Input This pin is also used as Clock Line for I C programming interface3.3 tolerant. Center Pad GND GND Supply Ground.

3 Configuration Table EN# Function Input R Output R Channels disable if EN# is high, Chip Power Down 6kΩ to GND Hi-Z Chip and channels enabled 5Ω 5Ω IC_EN Function I C Mode is enabled when I C_EN pin is pulled up to "" I C Mode is disabled and configured in Pin-strap control when I C_EN pin is pulled down to "" Mode Adjustment Equalization Setting through Pin Strap: EQ_A/B are the selection pins for the equalization selection for each direction. Equalizer setting 3.3 db NC 8. db (Default).7 db 3

4 Equalization Setting through I C Programming Interface: Equalizer setting A/B_CH Byte Register db 3.3 db 4.5 db 5.6 db 6.8 db 7.4 db 8. db (Default) 8.7 db 9.3 db db.8 db.7 db.5 db 3.3 db 4. db 5 db Note: *Bits A/B_CH[3:] are for other settings, see I C register definition Output Swing Setting through Pin Strap: OS_A/B are the selection pins for the output swing selection for each direction. Output swing setting OS_A/B Output 5Gbps 9mVppd NC (Default) mvppd (Default) V DD mvppd Output Swing Setting through I C Programming Interface: Output swing setting A/B_CH[3:]* Output 5Gbps 9mVppd mvppd (Default) mvppd mvppd Note: *Bits A/B_CH[7:4,:] are for other settings, see I C register definition 4

5 De-emphasis Setting through Pin Strap: DE_A/B are the selection pins for the de-emphasis selection for each direction. De-emphasis setting DE_A/B 5Gbps db NC -3.5dB (Default) V DD -6dB De-emphasis Setting through I C Programming Interface: De-emphasis setting A/B_CH[:]* 5Gbps db -db -3.5dB (Default) -6dB Note: *Bits A/B_CH[7:] are for other settings, see I C register definition 5

6 Transferring Data Every byte put on the SDA line must be 8-bits long. Each byte has to be followed by an acknowledge bit. Data is transferred with the most significant bit (MSB) first (see the I C Data Transfer diagram). The PI3EQX58 will never hold the clock line SCL LOW to force the master into a wait state. Note: Block-write and Block-read transfers have a fixed offset of x, because of the very small number of configuration bytes. An offset byte presented by a host to the PI3EQX58 is not used. Addressing Up to four PI3EQX58 devices can be connected to a single I C bus. The PI3EQX58 supports 7-bit addressing, with the LSB indicating either a read or write operation. The address for a specific device is determined by the A and A input pins. Address Assignment A6 A5 A4 A3 A A A R/W Programmable =R, =W Acknowledge Data transfer with acknowledge is required from the master. When the master releases the SDA line (HIGH) during the acknowledge clock pulse, the PI3EQX58 will pull down the SDA line during the acknowledge clock pulse so that it remains stable LOW during the HIGH period of this clock pulse as indicated in the I C Data Transfer diagram. The PI3EQX58 will generate an acknowledge after each byte has been received. Data Transfer A data transfer cycle begins with the master issuing a start bit. After recognizing a start bit, the PI3EQX58 will watch the next byte of information for a match with its address setting. When a match is found it will respond with a read or write of data on the following clocks. Each byte must be followed by an acknowledge bit, except for the last byte of a read cycle which ends with a stop bit. For a write cycle, the first data byte following the address byte is a dummy or fill byte that is not used by the PI3EQX58. This byte is provided to provided compatibility with systems implementing -bit addressing. Data is transferred with the most significant bit (MSB) first. I C Data Transfer Start & Stop Conditions A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition. A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition, as shown in the figure below. SDA SDA SCL S START condition P STOP condition SCL Figure 4. I C START and STOP conditions. 6

7 I C Data Transfer. Read sequence ACK DATA OUT ACK ACK DATA OUT N NO ACK I C Master start DEV SEL R / W stop. Write sequence ACK ACK ACK ACK ACK I C Master start DEV SEL R / W DUMMY BYTE DATA IN DATA IN N stop 3. Combined sequence ACK DUMMY BYTE ACK ACK DATA OUT ACK ACK DATA OUT N NO ACK I C Master start DEV SEL R / W start DEV SEL R / W stop Notes:. only block read and block write from the lowest byte are supported for this application.. for some IC application, an offset address byte will be presented at the second byte in write command, which is called dummy byte here and will be simply ignored in this application for correct interoperation. 7

8 Register Description BYTE - Channel A Setting Register (A_CH[7:]) Bit Type Power-on State Control Signal Description 7 R/W latch from pin A_EQ[3] Controls Equalization setting of CH A 6 R/W latch from pin A_EQ[] Default setting is 8.dB; latched from pin A_EQ 5 R/W latch from pin A_EQ[] 4 R/W latch from pin A_EQ[] 3 R/W A_OS[] Controls output swing of CH A. R/W A_OS[] Default setting is mvppd; A_OS[:]="" R/W A_DE[] Controls output de-emphasis of CH A R/W A_DE[] Default setting is -3.5dB; A_DE[:]="" BYTE - Channel B Setting Register (B_CH[7:]) Bit Type Power-on State Control Signal Description 7 R/W latch from pin B_EQ[3] Controls Equalization setting of CH B 6 R/W latch from pin B_EQ[] Default setting is 8.dB; latched from pin B_EQ 5 R/W latch from pin B_EQ[] 4 R/W latch from pin B_EQ[] 3 R/W B_OS[] Controls output swing of CH B R/W B_OS[] Default setting is mvppd; B_OS[:]="" R/W B_DE[] Controls output de-emphasis of CH B R/W B_DE[] Default setting is -3.5dB; B_DE[:]="" BYTE - Global Function Setting Register (GBL_FUNC[7:]) Bit Type Power-on State Control Signal Description 7 R/W TDET_EN Termination Detect Enable 6 R/W APD_EN Auto Slumber Mode Enable 5 R/W ADE_EN Auto-De-emphasis Enable 4 R/W EM_HALF Half bit de-emphasis Enable 3 R/W UNPLUG_EN Unplug detector Enable R/W UNPLUG_VTH Unplug Detector Threshold R/W Latch from pin A_PD Channel A Power Down; latched from pin EN# R/W Latch from pin B_PD Channel B Power Down, latched from pin EN# 8

9 BYTE 3 - Channel A Status Register (A_STAT[7:]) Bit Type Power-on State Control Signal Description 7 R N/A TDET_A HIGH indicates receiver detected at channel A 6 R N/A APD_A HIGH indicates power saving mode at channel A 5 R N/A SDET_A HIGH indicates signal detected at channel A 4 R N/A ADE_A 3 R Reserved R Reserved R Reserved R Reserved BYTE 4 - Channel B Status Register (B_STAT[7:]) Bit Type Power-on State Control Signal Description HIGH indicates de-emphasis data only at channel A 7 R N/A TDET_B HIGH indicates receiver detected at channel B 6 R N/A APD_B HIGH indicates power saving mode at channel B 5 R N/A SDET_B HIGH indicates signal detected at channel B 4 R N/A ADE_B HIGH indicates de-emphasis data only at channel B 3 R Reserved R Reserved R Reserved R Reserved BYTE 5 - RESREVED, Offset = x5, Default Power On State = "" BYTE RESREVED 9

10 Maximum Ratings (Above which useful life may be impaired. For user guidelines, not tested.) Storage Temperature C to +5 C Supply Voltage to Ground Potential....5V to +4.6V DC SIG Voltage....5V to V DD +.5V Current Output... 5mA to +5mA Power Dissipation Continuous... W Operating Temperature to +85 C ESD, Human Body Model... 6kv to +6kV ESD, Machine Model... V to +V ESD, Charged Device Model... 5V to +5V Note: Stresses greater than those listed under MAXI- MUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. AC/DC Electrical Characteristics 3.3V/.5V Power Supply Characteristics Symbol Parameter Conditions Min. Typ. Max. Units V DD33 Power Supply Voltage 3.3V V P STANDBY33 Supply Power Standby EN# =.8.8 P DEVICE_UNPLUG Supply Power Device Unplug EN# =, TDET = mw P ACTIVE33 Supply Power Active EN# =, V RX-DIFF-P V TH-SD, Output Swing = 9mVppd V DD.5 Power Supply Voltage.5V V P STANDBY.5 Supply Power Standby EN# =.8.85 P DEVICE_UNPLUG Supply Power Device Unplug EN# =, TDET = mw P ACTIVE.5 Supply Power Active EN# =, V RX-DIFF-P V TH-SD, Output Swing = 9mVppd 5 98 I DD-STANDBY Supply Current Standby EN# =.5 ma I DD-DEVICE_UNPLUG Supply Current Device Unplug EN# =, TDET =..5 I DD-ACTIVE Supply Current Active Output Swing = 9mV ppd ma

11 AC/DC Electrical Characteristics (Continued..) Symbol Parameter Conditions Min. Typ. Max. Units t PD Latency From input to output ns CML Receiver Input (W Differential) Z RX-DC DC Input Impedance Z RX-DIFF-DC DC Differential Input Impedance 8 Ω V RX-DIFFP-P Differential Input Peak-to-peak Voltage 75 V RX-CM-ACP AC Peak Common Mode Input Voltage 5 mv V TH-SD Signal detect Threshold EN# = mvppd J RS Residual Jitter (,) Total Jitter.3 Ulp-p Notes. K8.7 pattern is applied differentially at point A as shown in Figure 5.. Total jitter does not include the signal source jitter. Total jitter (TJ) = (4. RJ + DJ) where RJ is random RMS jitter and DJ is maximum deterministic jitter. Signal source is a K8.5 ± pattern ( ) for the deterministic jitter test and K8.7 () or equivalent for random jitter test. Residual jitter is that which remains after equalizing media-induced losses of the environment of Figure or its equivalent. The deterministic jitter at point B must be from media-induced loss, and not from clock source modulation. Jitter is measured at V at point C of Figure 5. AC/DC Electrical Characteristics (Continued..) Symbol Parameter Conditions Min. Typ. Max. Units CML Transmitter Output (Ω differential) Z OUT Output Resistance Single-Ended Z TX-DIFF-DC DC Differential TX Impedance 7 V TX-DIFFP-P Differential Peak-to-peak Output Voltage V TX-DIFFP-P = * V TX-D+ - V TX-D- Ω 9 mv V TX-C Common-Mode Voltage V TX-D+ + V TX-D- /.5. V V cm_ac TX AC common mode voltage mvpp V TX-Pre-Ratio-max Max TX De-emphasis Level -6 db C AC-coupling AC coupling capacitor 75 nf LVCMOS Control Pins (Pins: 3, 3) V IH V IL Input High Voltage (Bi-Level) Input Low Voltage (Bi-Level) Tri-level Control Pins (Pins: 7, 7, 8, 8, 9, 9).65 V DD.35 V DD

12 PI3EQX58 AC/DC Electrical Characteristics (Continued..) Symbol Parameter Conditions Min. Typ. Max. Units V IH Input High Voltage (Tri-Level).8V DD V V MID Input mid level.4v DD.6V DD V IL Input Low Voltage (Tri-Level).V DD I IH Input High Current, V IH = V DD 5 I IL Input Low Current, V IL = V -5 µa Note:. Recommended output coupling capacitor is 75nF to nf (on each output). V DD = V DD 33 or V DD.5 FR4 Signal Source A B C D.U.T. SmA SmA Connector Connector In Out 36IN Figure 5. Test Condition Referenced in the Electrical Characteristic Table C uf C.uF C3.uF EQ_A R R8 DE_A/SDA R R9 OS_A/SCL R R3 R EQ_B R DE_B/A R3 R4 OS_B/A R6 R7 R3 for EQX58 Vdd(.5V or 3.3V) R9 R38 7kohmR V kohm +3.3V HOST U OS_A/SCL DE_A/SDA EQ_A R R= ON, when EQX58 Vdd=.5V R= NC, when EQX58 Vdd=3.3V DEVICE OS_A/SCL DE_A/SDA R4 R43 ohm or NC ohm or NC 4.7k 4.7k Q5 S G SK38@SOT-3 Q6 S D G C.u D R4 k R4 k HOST_SCL HOST_SDA NC for normal mode 3 R4 C6.uF 4 C7.uF 5 R3= ON, when EQX58 Vdd=.5V R3= NC, when EQX58 Vdd=3.3V 5 C4.uF AI+ AO+ DNC HGND EQ_B 3P3/P5 DE_B / A OS_A / SCL OS_B / A DE_A / SDA 3P3/P5 A_EQ DNC R3 EQ_B DE_B/A OS_B/A RX+ RX- TX+ TX- AI- EN# BO- BO+ C5.uF AO- 4 R5 IC_EN 3 GND BI- BI+ PI3EQX58ZDE@TQFN TX+ TX- RX+ RX- CONTROL PIN FUNCTION DESCRIPTION PIN Name IC_EN OS_A/SCL DE_A/SDA DE_B/A level shift circuit PIN FUNCTION DESCRIPTION IC Control enable. When the pin is driven "High", chip is in IC control mode. When the pin is driven "Low", chip is in pin strap control mode. With internal K ohm pull-down resistor. Set the output swing of Channel A. This is a Tri-level input pin. This pin is also used as Clock Line for IC programming interface. SK38@SOT-3 Set the de-emphasis of output CML buffer for Channel A. This is a Tri-level input pins.this pin is also used as Data Line for IC programming interface. Set the de-emphasis of output CML buffer for Channel B. This is a Tri-level input pins.this pin is also used for IC programming interface when it is set to "high", IC address bit A is set to "". When it is set to "low"or floating, IC address bit A is set to "" To IC Host Controller Pin strapping R5 = on R4 open, Tri-level control by R & R3 R43=open, Tri-level control by R8 & R9 Tri-level control by R3 & R4 IC operator R5 = open R4 = on R43 = on For IC Registor Address A Selection NOTE: After PCB layout, de-emphasis, output swing and Equalizer should be fine tune OS_B/A Set the output swing of Channel B. This is a Tri-level input pins. This pin is also used for IC programming interface when it is set to "high", IC address bit A is set to "". When it is set to "low"or floating, IC address bit A is set to "" Tri-level control by R6 & R7 For IC Registor Address A Selection Output de-emphasis setting Equalizer setting Description Description PI3EQX58ZDE db R3 & R8 NC, R4 & R9 on 3.3 db R & R NC, R & R on open -3.5 db R3 & R8 NC, R4 & R9 NC open 8. db R & R NC, R & R NC -6 db R3 & R8 on, R4 & R9 NC.7 db R & R on, R & R NC Output Swing setting EN# RxDet Input R Output R Description X 6K to GND Hi-Z 9mVppd R6 & R NC, R7 & R3 on 6K to GND 5 ohm / K open mvppd R6 & R NC, R7 & R3 NC 5 ohm 5 ohm mvppd R6 & R on, R7 & R3 NC Title PI3EQX58 refernce design draw by PSC Anne Size Document Number Rev B <Doc> V Friday, February 3, Date: Sheet of

13 Packaging Mechanical: -contact TQFN (ZD) DATE: 9//8 DESCRIPTION: -Lead, Thin Fine Pitch Quad Flat No-Lead (TQFN) PACKAGE CODE: ZD DOCUMENT CONTROL #: PD-84 REVISION: -- Ordering Information Ordering Number Package Code Package Description PI3EQX58ZDE ZD Pb-Free and Green -pin TQFN (4x4mm) Notes: Thermal characteristics can be found on the company web site at E = Pb-free and Green X suffix = Tape/Reel Pericom Semiconductor Corporation All trademarks are property of their respective owners. 3