Simple Link Protocol (SLP)

Size: px
Start display at page:

Download "Simple Link Protocol (SLP)"

Transcription

1 Simple ink Protocol (SP) zero-overhead packet delineation for 10Gb thernet N-PHY lbuquerque meeting March 6-10, 2000 Kamran zadet, ei-lei Song, om ruman, Mark Yu Paul Bottorff, Norival Figueira, avid Martin... Fred Weniger. Vitesse om Palkert... MCC Jim Yokouchi.Sumitomo on arson riquint ucent echnologies Nortel Networks 1

2 Goals For packet-delineation & line coding scheme (PCS) Zero overhead No packet length required No rate conversion required (10.000Gb/s and GBaud) Serial- and WM-PM agnostic N friendly - simple and low cost Suitable for other non-ethernet packet-based protocols For chip-to-chip interconnect (XU) M mitigation No code conversion required Can work with 8b/10b H or SUP 2

3 3 Key Concepts for SP Standard thernet frames have sufficient information to find packet/byte boundaries Control characters are embedded in nter-packet Gap (PG) ncoding: zero-overhead scrambling ata payload is scrambled bit serialization of thernet packets Control characters: M-reducing scrambling or C-balanced control chars ata Control ata Control O P SYNCHONZON PN O P S O P

4 SP Frame elineation PHY state machine tracks context : {HUN,, CONO} HUN state: unsynchronized, looking for repeated characters Start of Packet ook for SOP byte When found, enter mode ook for frame termination pattern Frame termination pattern: (-FG) ook for {OP, 11 x } nter CONO state ll bytes are control characters until SOP is found etection of error packet (-FG) : rop current packet and nter CONO state 4

5 etection of control sequences here are 2 critical control sequences, each at least 12-byte long nd of normal packet: -FG nd of error packet: -FG Occurrence of these flags inside payload is once every 2,000 billion years (match over 12Bytes is very unlikely) f the end-of-packet sequence, the -FG, is found inside payload (not a lucky day!) ransmitter generates -FG Packet is re-transmitted with a different scrambler state llowing up to 3-bit mismatches for detection of the control sequences to increase the likelihood of matching patterns 5

6 What about false match? Pattern matching with 3 bit error tolerance means = difference between two words is less than 3 bits ikelihood of matching patterns with 3 bit error tolerance is greater than with no error tolerance, but still extremely small Probability of false match: ~ once every 15 million years (see supporting calculations in full presentation) 6

7 Calculating Probability of False Match Chance that a 96-bit segment matches desired pattern B to within 2 bits Pr X = i Bi 3 = * i= = Number of 96-bit patterns per year (@10Gbit/s) = bit/s x 1/8 bits x (3600x24x365) s / year ; 4x10 16 / year hus, frequency of false match is once every 15 million years 7

8 Scrambling Scheme Payload Control Payload Control x x 7 + x Similar to scrambling scheme used in SON (proposed by Bottorff, Martin & Figueira) x is self-synchronous x 7 + x is periodically synchronized ual scrambler nner scrambler prevents malicious attack Outer scrambler defines spectral characteristics Scrambling improves M characteristics 8

9 Pattern Spectral Measurements at lane ate db improvement for scrambling relative to 8b/10b Green: PBS @ 2.5gbit/sec ed: ed: 3.125gbit/sec 9

10 Pattern Spectral Measurements at ine ate Green: PBS @ Gb/s Gb/s ed: ed: Gb/s Gb/s 10

11 Control characters S: SOP : OP : rror : dle B: Busy dle 4 bit Hamming distance => 1 bit error correction, or 3bit error detection Can have up to 16 control codes with 4b Hamming distance plenty of spares 11

12 Code for Control Characters he following extended Hamming (8,4) code can be used for representing up to 16 control characters: ( , ), ( , ), ( , ), ( , ), ( , ), ( , ), ( , ), ( , ), ( , ), ( , ), ( , ), ( , ), ( , ), ( , ), ( , ), ( , ). Property: -- minimum Hamming distance of 4 he first 14 code words are C-balanced, hence can be used directly for systems without scrambler 12

13 oss of Synchronization oss of synchronization occurs when: PHY control state machine in mode and no PG after timeout period imeout period can be chosen as maximum frame length ( bytes) for thernet For non-thernet applications, other timeout period can be used (e.g., 8 Kbytes) Synchronization is achieved immediately at the next PG (provided that optical link is up) No handshaking required between ransmitter & eceiver Synchronization time < maximum packet length 13

14 pplication of SP to PCS/PM nterface 16-bit Parallel (625MHz) nterface of choice for serial PM 16 bit interface is formed by grouping two bytes at XGM Phase ambiguity in serial PM results in constant bit offset between mux & demux easily resolved by searching for -FG using sliding window to find byte-sync Scrambled 4-bit Serial (2.5GBaud / lane) SP could also be used for transmission over 4-channel WWM esults in 25% lower Baud-rate for only 2.5% penalty due to C wander ach of the 4 bytes of the encoder is directly sent serially on four lanes eskewing can be done using GN control code periodically embedded in PG 14

15 Summary of Simple ink Protocol Zero overhead ( GBaud) No rate conversion, gear box, or elastic buffers SOP is not restricted to ane 0: no impact on PG irect mapping of thernet (N friendly) ata rate does not decrease to 9.29Gb/s (as for 64b/66b) Preserves byte boundaries (WN friendly) Suitable for both serial and WM ow latency (could be used in serial nfiniband) Scrambling allows C balance and is good for M Best performance, at lowest baud-rate Can work with or without H (as serial /O) 15

16 emonstration System 16-bit 622 MHz interface into Opto module < 20k gates (~3% of FPG logic resources) VH code will be made available to SP supporters 16

17 Bell aboratories Back-up slides 17

18 18 Case of ransmit rror / bort Support of cut-through packet switching rror can occur inside the payload: when error occurs terminate packet, then: insert at least 4 error symbols (desirable in some applications) X SQUNC XGM S O P O P S O P O P PCS OUPU SQUNC

19 Pattern Spectral Measurements ata Pattern 1megabit in length using PBS 8B10B Pattern 8B10B ncode ata Pattern Scrambled Pattern Scrambled ata Pattern based on proposed X^58+X^19+1 Sequence 19

20 Pattern Spectral Measurements est setup used in spectral measurements Pattern Generator coax Spectrum nalyzer Clock Source 20

21 PCS latency ess than XGM clock latency at encoder (direct mapping of XGM) 3 XGM clock cycles at the decoder to detect OP (12Bytes) can be reduced by using less than 12Bytes to detect OP ex: when using 8Bytes pattern matching, latency can be reduced to 2 cycles Probability of false match with 8bytes and 1b error tolerance is 3.52 x10-18 False match over 8bytes with 1b error tolerance occurs ~ once a year n the conservative case (12Bytes) latency is 16 Byte times total PCS latency is = 12.8ns 21

22 Scrambler synchronization uring loss of sync or initialization enter HUN mode ook for sequence of repeated characters Output of descrambled s should give a long chain of 000. nitially open the loop of the side-stream descrambler, and after observing N zeros, enable sync bit (then close the loop of the descrambling shift register) 100BS-X uses a similar scheme... x6 x 7 + sync... x6 x Sync detect sync 22

10GE WAN PHY: Physical Medium Attachment (PMA)

10GE WAN PHY: Physical Medium Attachment (PMA) 10GE WAN PHY: Physical Medium Attachment (PMA) IEEE 802.3 Meeting, Albuquerque March 6-10, 2000 Norival Figueira, Paul Bottorff, David Martin, Tim Armstrong, Bijan Raahemi.. Enrique Hernandez-Valencia..

More information

10GBASE-R Test Patterns

10GBASE-R Test Patterns John Ewen jfewen@us.ibm.com Test Pattern Want to evaluate pathological events that occur on average once per day At 1Gb/s once per day is equivalent to a probability of 1.1 1 15 ~ 1/2 5 Equivalent to 7.9σ

More information

Toward Convergence of FEC Interleaving Schemes for 400GE

Toward Convergence of FEC Interleaving Schemes for 400GE Toward Convergence of FEC Interleaving Schemes for 400GE Zhongfeng Wang and Phil Sun Broadcom Corp. and Marvell IEEE P802.3bs, Task force, Sep., 2015 1 INTRODUCTION This presentation discusses tradeofffs

More information

DisplayPort 1.4 Link Layer Compliance

DisplayPort 1.4 Link Layer Compliance DisplayPort 1.4 Link Layer Compliance Neal Kendall Product Marketing Manager Teledyne LeCroy quantumdata Product Family neal.kendall@teledyne.com April 2018 Agenda DisplayPort 1.4 Source Link Layer Compliance

More information

Error performance objective for 25 GbE

Error performance objective for 25 GbE Error performance objective for 25 GbE Pete Anslow, Ciena IEEE 25 Gb/s Ethernet Study Group, Ottawa, Canada, September 2014 1 History The error performance objective adopted for the P802.3ba, P802.3bj

More information

EFM Copper Technical Overview EFM May, 2003 Hugh Barrass (Cisco Systems), Vice Chair. IEEE 802.3ah EFM Task Force IEEE802.

EFM Copper Technical Overview EFM May, 2003 Hugh Barrass (Cisco Systems), Vice Chair. IEEE 802.3ah EFM Task Force IEEE802. EFM Copper Technical Overview EFM May, 2003 Hugh Barrass (Cisco Systems), Vice Chair. IEEE 802.3ah EFM Task Force barrass_1_0503.pdf hbarrass@cisco.com 4 Technical Overview The Components of the Standard

More information

AMD-53-C TWIN MODULATOR / MULTIPLEXER AMD-53-C DVB-C MODULATOR / MULTIPLEXER INSTRUCTION MANUAL

AMD-53-C TWIN MODULATOR / MULTIPLEXER AMD-53-C DVB-C MODULATOR / MULTIPLEXER INSTRUCTION MANUAL AMD-53-C DVB-C MODULATOR / MULTIPLEXER INSTRUCTION MANUAL HEADEND SYSTEM H.264 TRANSCODING_DVB-S2/CABLE/_TROPHY HEADEND is the most convient and versatile for digital multichannel satellite&cable solution.

More information

802.3bj FEC Overview and Status. 400GbE PCS Baseline Proposal DRAFT. IEEE P802.3bs 400 Gb/s Ethernet Task Force

802.3bj FEC Overview and Status. 400GbE PCS Baseline Proposal DRAFT. IEEE P802.3bs 400 Gb/s Ethernet Task Force 802.3bj FEC Overview and Status 400GbE PCS Baseline Proposal DRAFT IEEE P802.3bs 400 Gb/s Ethernet Task Force January 2015 Atlanta Mark Gustlin Xilinx Arthur Marris - Cadence Gary Nicholl - Cisco Dave

More information

Laboratory 4. Figure 1: Serdes Transceiver

Laboratory 4. Figure 1: Serdes Transceiver Laboratory 4 The purpose of this laboratory exercise is to design a digital Serdes In the first part of the lab, you will design all the required subblocks for the digital Serdes and simulate them In part

More information

TV4U QUAD DVB-S2 to DVB-C TRANSMODULATOR

TV4U QUAD DVB-S2 to DVB-C TRANSMODULATOR INSTRUCTION MANUAL Features of the new DVB-C transmodulators line Through the use of the FPGA technology the transmodulators provides the highest performance at the lowest price. Four carriers are formed

More information

Technical Article MS-2714

Technical Article MS-2714 . MS-2714 Understanding s in the JESD204B Specification A High Speed ADC Perspective by Jonathan Harris, applications engineer, Analog Devices, Inc. INTRODUCTION As high speed ADCs move into the GSPS range,

More information

Error performance objective for 400GbE

Error performance objective for 400GbE Error performance objective for 400GbE Pete Anslow, Ciena IEEE 400 Gb/s Ethernet Study Group, York, September 2013 1 Introduction The error performance objective adopted for the P802.3ba, P802.3bj and

More information

10 Mb/s Single Twisted Pair Ethernet Proposed PCS Layer for Long Reach PHY Dirk Ziegelmeier Steffen Graber Pepperl+Fuchs

10 Mb/s Single Twisted Pair Ethernet Proposed PCS Layer for Long Reach PHY Dirk Ziegelmeier Steffen Graber Pepperl+Fuchs 10 Mb/s Single Twisted Pair Ethernet Proposed PCS Layer for Long Reach PHY Dirk Ziegelmeier Steffen Graber Pepperl+Fuchs IEEE P802.3cg 10 Mb/s Single Twisted Pair Ethernet Task Force 8/29/2017 1 Content

More information

SpaceFibre. Steve Parkes, Chris McClements, Martin Suess* Space Technology Centre University of Dundee *ESA, ESTEC

SpaceFibre. Steve Parkes, Chris McClements, Martin Suess* Space Technology Centre University of Dundee *ESA, ESTEC SpaceFibre Steve Parkes, Chris McClements, Martin Suess* Space Technology Centre University of Dundee *ESA, ESTEC 1 Lessons Learnt from SpaceWire Cable Mass 87 g/m approximately Bi-directional Data strobe

More information

Data Rate to Line Rate Conversion. Glen Kramer (Broadcom Ltd)

Data Rate to Line Rate Conversion. Glen Kramer (Broadcom Ltd) Data Rate to Line Rate Conversion Glen Kramer (Broadcom Ltd) Motivation 100G EPON MAC data rate is 25 Gb/s 25GMII transmits 32 bits @ 390.625 MHz (on both rising and falling edges) 64b/66b encoder adds

More information

Synchronization Issues During Encoder / Decoder Tests

Synchronization Issues During Encoder / Decoder Tests OmniTek PQA Application Note: Synchronization Issues During Encoder / Decoder Tests Revision 1.0 www.omnitek.tv OmniTek Advanced Measurement Technology 1 INTRODUCTION The OmniTek PQA system is very well

More information

A Look at Some Scrambling Techniques U sed in Various Data Transport Protocols

A Look at Some Scrambling Techniques U sed in Various Data Transport Protocols Nov 1993 DOC: IEEE PB02.11-93/216 IEEE 802.11 Wireless Access Methods and Physical Layer Specifications TITLE: DATE: AUTHOR: A Look at Some Scrambling Techniques U sed in Various Data Transport Protocols

More information

P802.3av interim, Shanghai, PRC

P802.3av interim, Shanghai, PRC P802.3av interim, Shanghai, PRC 08 09.06.2009 Overview of 10G-EPON compiled by Marek Hajduczenia marek.hajduczenia@zte.com.cn Rev 1.2 P802.3av interim, Shanghai, PRC 08 09.06.2009 IEEE P802.3av 10G-EPON

More information

CHAPTER 6 ASYNCHRONOUS QUASI DELAY INSENSITIVE TEMPLATES (QDI) BASED VITERBI DECODER

CHAPTER 6 ASYNCHRONOUS QUASI DELAY INSENSITIVE TEMPLATES (QDI) BASED VITERBI DECODER 80 CHAPTER 6 ASYNCHRONOUS QUASI DELAY INSENSITIVE TEMPLATES (QDI) BASED VITERBI DECODER 6.1 INTRODUCTION Asynchronous designs are increasingly used to counter the disadvantages of synchronous designs.

More information

DATUM SYSTEMS Appendix A

DATUM SYSTEMS Appendix A DATUM SYSTEMS Appendix A Datum Systems PSM-4900 Satellite Modem Technical Specification PSM-4900, 4900H and 4900L VSAT / SCPC - Modem Specification Revision History Rev 1.0 6-10-2000 Preliminary Release.

More information

Course 10 The PDH multiplexing hierarchy.

Course 10 The PDH multiplexing hierarchy. Course 10 The PDH multiplexing hierarchy. Zsolt Polgar Communications Department Faculty of Electronics and Telecommunications, Technical University of Cluj-Napoca Multiplexing of plesiochronous signals;

More information

(51) Int Cl.: H04L 1/00 ( )

(51) Int Cl.: H04L 1/00 ( ) (19) TEPZZ Z4 497A_T (11) EP 3 043 497 A1 (12) EUROPEAN PATENT APPLICATION published in accordance with Art. 153(4) EPC (43) Date of publication: 13.07.2016 Bulletin 2016/28 (21) Application number: 14842584.6

More information

ELEC 691X/498X Broadcast Signal Transmission Winter 2018

ELEC 691X/498X Broadcast Signal Transmission Winter 2018 ELEC 691X/498X Broadcast Signal Transmission Winter 2018 Instructor: DR. Reza Soleymani, Office: EV 5.125, Telephone: 848 2424 ext.: 4103. Office Hours: Wednesday, Thursday, 14:00 15:00 Slide 1 In this

More information

Digital Transmission System Signaling Protocol EVLA Memorandum No. 33 Version 3

Digital Transmission System Signaling Protocol EVLA Memorandum No. 33 Version 3 Digital Transmission System Signaling Protocol EVLA Memorandum No. 33 Version 3 A modified version of Digital Transmission System Signaling Protocol, Written by Robert W. Freund, September 25, 2000. Prepared

More information

A LOW COST TRANSPORT STREAM (TS) GENERATOR USED IN DIGITAL VIDEO BROADCASTING EQUIPMENT MEASUREMENTS

A LOW COST TRANSPORT STREAM (TS) GENERATOR USED IN DIGITAL VIDEO BROADCASTING EQUIPMENT MEASUREMENTS A LOW COST TRANSPORT STREAM (TS) GENERATOR USED IN DIGITAL VIDEO BROADCASTING EQUIPMENT MEASUREMENTS Radu Arsinte Technical University Cluj-Napoca, Faculty of Electronics and Telecommunication, Communication

More information

SMPTE STANDARD Gb/s Signal/Data Serial Interface. Proposed SMPTE Standard for Television SMPTE 424M Date: < > TP Rev 0

SMPTE STANDARD Gb/s Signal/Data Serial Interface. Proposed SMPTE Standard for Television SMPTE 424M Date: < > TP Rev 0 Proposed SMPTE Standard for Television Date: TP Rev 0 SMPTE 424M-2005 SMPTE Technology Committee N 26 on File Management and Networking Technology SMPTE STANDARD- --- 3 Gb/s Signal/Data Serial

More information

Guidance For Scrambling Data Signals For EMC Compliance

Guidance For Scrambling Data Signals For EMC Compliance Guidance For Scrambling Data Signals For EMC Compliance David Norte, PhD. Abstract s can be used to help mitigate the radiated emissions from inherently periodic data signals. A previous paper [1] described

More information

802.3bj Scrambling Options

802.3bj Scrambling Options 802.3bj Scrambling Options IEEE P802.3bj July 2012 San Diego Roy Cideciyan IBM Mark Gustlin Xilinx Jeff Slavick Avago Contributors and supporters Pete Anslow Ciena Andre Szczepanek Inphi Stephen Bates

More information

BABAR IFR TDC Board (ITB): requirements and system description

BABAR IFR TDC Board (ITB): requirements and system description BABAR IFR TDC Board (ITB): requirements and system description Version 1.1 November 1997 G. Crosetti, S. Minutoli, E. Robutti I.N.F.N. Genova 1. Timing measurement with the IFR Accurate track reconstruction

More information

Canova Tech. IEEE 802.3cg Collision Detection Reliability in 10BASE-T1S March 6 th, 2019 PIERGIORGIO BERUTO ANTONIO ORZELLI

Canova Tech. IEEE 802.3cg Collision Detection Reliability in 10BASE-T1S March 6 th, 2019 PIERGIORGIO BERUTO ANTONIO ORZELLI Canova Tech The Art of Silicon Sculpting PIERGIORGIO BERUTO ANTONIO ORZELLI IEEE 802.3cg Collision Detection Reliability in 10BASE-T1S March 6 th, 2019 Public Document Slide 1 Public Document Slide 2 Outline

More information

Basics of BISS scrambling. Newtec. Innovative solutions for satellite communications

Basics of BISS scrambling. Newtec. Innovative solutions for satellite communications Basics of BISS scrambling Contents Definition of scrambling BISS modes BISS mode 1 BISS mode E Calculation of encrypted session word Buried ID Injected ID Connection diagram Rate adaptation Back panel

More information

Overview: Logic BIST

Overview: Logic BIST VLSI Design Verification and Testing Built-In Self-Test (BIST) - 2 Mohammad Tehranipoor Electrical and Computer Engineering University of Connecticut 23 April 2007 1 Overview: Logic BIST Motivation Built-in

More information

for Television ---- Bit-Serial Digital Interface for High-Definition Television Systems Type FC

for Television ---- Bit-Serial Digital Interface for High-Definition Television Systems Type FC SMPTE STNDRD NSI/SMPTE 292M-1996 for Television ---- it-serial Digital Interface for High-Definition Television Systems 1 Scope This standard defines a bit-serial digital coaxial and fiber-optic interface

More information

TV4U DVB-S2 to DVB-S2 TRANSMODULATOR

TV4U DVB-S2 to DVB-S2 TRANSMODULATOR TV4U to TRANSMODULATOR TV4U to TRANSMODULATOR INSTRUTION MANUAL TV4U to TRANSMODULATOR The main application of to transmodulator Experience of MVDS terrestrial broadcasting shows that carrier must be restored

More information

CS311: Data Communication. Transmission of Digital Signal - I

CS311: Data Communication. Transmission of Digital Signal - I CS311: Data Communication Transmission of Digital Signal - I by Dr. Manas Khatua Assistant Professor Dept. of CSE IIT Jodhpur E-mail: manaskhatua@iitj.ac.in Web: http://home.iitj.ac.in/~manaskhatua http://manaskhatua.github.io/

More information

How SolarFlare Communications Broke. SolarFlare Communications

How SolarFlare Communications Broke. SolarFlare Communications ow SolarFlare Communications roke the 10Gbps on UP arrier SolarFlare Communications eadquarters: rvine, CA Product Focus: 10Gbps UP Ethernet chip set Fabless business model with foundry CMOS process Key

More information

SDTV 1 DigitalSignal/Data - Serial Digital Interface

SDTV 1 DigitalSignal/Data - Serial Digital Interface SMPTE 2005 All rights reserved SMPTE Standard for Television Date: 2005-12 08 SMPTE 259M Revision of 259M - 1997 SMPTE Technology Committee N26 on File Management & Networking Technology TP Rev 1 SDTV

More information

Performance Driven Reliable Link Design for Network on Chips

Performance Driven Reliable Link Design for Network on Chips Performance Driven Reliable Link Design for Network on Chips Rutuparna Tamhankar Srinivasan Murali Prof. Giovanni De Micheli Stanford University Outline Introduction Objective Logic design and implementation

More information

LPI SIGNALING ACROSS CLAUSE 108 RS-FEC

LPI SIGNALING ACROSS CLAUSE 108 RS-FEC March 2015 P802.3by 25 Gb/s Ethernet Task Force 1 LPI SIGNALING ACROSS CLAUSE 108 RS-FEC Adee Ran March 2015 P802.3by 25 Gb/s Ethernet Task Force 2 Background LPI original functions TX informs the RX that

More information

Performance Results: High Gain FEC over DMT

Performance Results: High Gain FEC over DMT Performance Results: High Gain FEC over DMT Nov 18, 2014 Sacha Corbeil, Shijun Yang Introduction The 4x100G DMT 400GE link proposals for the 500m, 2km and 10km PMD s rely on Forward Error Correction (FEC)

More information

FEC Options. IEEE P802.3bj January 2011 Newport Beach

FEC Options. IEEE P802.3bj January 2011 Newport Beach FEC Options IEEE P802.3bj January 2011 Newport Beach Stephen Bates PMC-Sierra, Roy Cideciyan IBM, Mark Gustlin Xilinx, Martin Langhammer - Altera, Jeff Slavick Avago, Zhongfeng Wang Broadcom Supporters

More information

A Terabyte Linear Tape Recorder

A Terabyte Linear Tape Recorder A Terabyte Linear Tape Recorder John C. Webber Interferometrics Inc. 8150 Leesburg Pike Vienna, VA 22182 +1-703-790-8500 webber@interf.com A plan has been formulated and selected for a NASA Phase II SBIR

More information

Backplane NRZ FEC Baseline Proposal

Backplane NRZ FEC Baseline Proposal Backplane NRZ FEC Baseline Proposal IEEE P802.3bj March 2012 Hawaii Stephen Bates PMC-Sierra, Matt Brown APM, Roy Cideciyan IBM, Mark Gustlin Xilinx, Adam Healey - LSI, Martin Langhammer - Altera, Jeff

More information

3rd Slide Set Computer Networks

3rd Slide Set Computer Networks Prof. Dr. Christian Baun 3rd Slide Set Computer Networks Frankfurt University of Applied Sciences WS1718 1/41 3rd Slide Set Computer Networks Prof. Dr. Christian Baun Frankfurt University of Applied Sciences

More information

Pro Video Formats for IEEE 1722a

Pro Video Formats for IEEE 1722a Pro Video Formats for IEEE 1722a Status & Next Steps Rob Silfvast Avid Technology, Inc. 12-August-2012 Today s Pro Video Infrastructure (for Live Streams, not file-based workflows) SDI (Serial Digital

More information

CAP240 First semester 1430/1431. Sheet 4

CAP240 First semester 1430/1431. Sheet 4 King Saud University College of Computer and Information Sciences Department of Information Technology CAP240 First semester 1430/1431 Sheet 4 Multiple choice Questions 1-Unipolar, bipolar, and polar encoding

More information

White Paper Lower Costs in Broadcasting Applications With Integration Using FPGAs

White Paper Lower Costs in Broadcasting Applications With Integration Using FPGAs Introduction White Paper Lower Costs in Broadcasting Applications With Integration Using FPGAs In broadcasting production and delivery systems, digital video data is transported using one of two serial

More information

ECEN454 Digital Integrated Circuit Design. Sequential Circuits. Sequencing. Output depends on current inputs

ECEN454 Digital Integrated Circuit Design. Sequential Circuits. Sequencing. Output depends on current inputs ECEN454 igital Integrated Circuit esign Sequential Circuits ECEN 454 Combinational logic Sequencing Output depends on current inputs Sequential logic Output depends on current and previous inputs Requires

More information

Transmission scheme for GEPOF

Transmission scheme for GEPOF Transmission scheme for GE Rubén Pérez-Aranda (rubenpda@kdpof.com) Agenda Motivation and objectives Transmission scheme: overview Transmission scheme: pilot sequences Transmission scheme: physical header

More information

VITERBI DECODER FOR NASA S SPACE SHUTTLE S TELEMETRY DATA

VITERBI DECODER FOR NASA S SPACE SHUTTLE S TELEMETRY DATA VITERBI DECODER FOR NASA S SPACE SHUTTLE S TELEMETRY DATA ROBERT MAYER and LOU F. KALIL JAMES McDANIELS Electronics Engineer, AST Principal Engineers Code 531.3, Digital Systems Section Signal Recover

More information

IN A SERIAL-LINK data transmission system, a data clock

IN A SERIAL-LINK data transmission system, a data clock IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 53, NO. 9, SEPTEMBER 2006 827 DC-Balance Low-Jitter Transmission Code for 4-PAM Signaling Hsiao-Yun Chen, Chih-Hsien Lin, and Shyh-Jye

More information

ATSC vs NTSC Spectrum. ATSC 8VSB Data Framing

ATSC vs NTSC Spectrum. ATSC 8VSB Data Framing ATSC vs NTSC Spectrum ATSC 8VSB Data Framing 22 ATSC 8VSB Data Segment ATSC 8VSB Data Field 23 ATSC 8VSB (AM) Modulated Baseband ATSC 8VSB Pre-Filtered Spectrum 24 ATSC 8VSB Nyquist Filtered Spectrum ATSC

More information

Arbitrary Waveform Generator

Arbitrary Waveform Generator 1 Arbitrary Waveform Generator Client: Agilent Technologies Client Representatives: Art Lizotte, John Michael O Brien Team: Matt Buland, Luke Dunekacke, Drew Koelling 2 Client Description: Agilent Technologies

More information

40G SWDM4 MSA Technical Specifications Optical Specifications

40G SWDM4 MSA Technical Specifications Optical Specifications 40G SWDM4 MSA Technical Specifications Specifications Participants Editor David Lewis, LUMENTUM The following companies were members of the SWDM MSA at the release of this specification: Company Commscope

More information

The Discussion of this exercise covers the following points:

The Discussion of this exercise covers the following points: Exercise 3-1 Digital Baseband Processing EXERCISE OBJECTIVE When you have completed this exercise, you will be familiar with various types of baseband processing used in digital satellite communications.

More information

FEC Architectural Considerations

FEC Architectural Considerations FEC Architectural Considerations P802.3bj Interim IEEE 802.3 Atlanta November 2011 Mark Gustlin Cisco, John D Ambrosia Dell, Sudeep Bhoja - Broadcom Contributors and Supporters Frank Chang Vitesse Roy

More information

arxiv: v1 [physics.ins-det] 30 Mar 2015

arxiv: v1 [physics.ins-det] 30 Mar 2015 FPGA based High Speed Data Acquisition System for High Energy Physics Application Swagata Mandal, Suman Sau, Amlan Chakrabarti, Subhasis Chattopadhyay VLSID-20, Design Contest track, Honorable Mention

More information

Commsonic. (Tail-biting) Viterbi Decoder CMS0008. Contact information. Advanced Tail-Biting Architecture yields high coding gain and low delay.

Commsonic. (Tail-biting) Viterbi Decoder CMS0008. Contact information. Advanced Tail-Biting Architecture yields high coding gain and low delay. (Tail-biting) Viterbi Decoder CMS0008 Advanced Tail-Biting Architecture yields high coding gain and low delay. Synthesis configurable code generator coefficients and constraint length, soft-decision width

More information

Distributed by: www.jameco.com 1-800-831-4242 The content and copyrights of the attached material are the property of its owner. 200 MBaud HOTLink Transceiver Features Second generation HOTLink technology

More information

Design Matched Filter for Digital Transmission Ethernet

Design Matched Filter for Digital Transmission Ethernet Design Matched Filter for Digital Transmission Ethernet Eman Salem Electrical Engineering Department Benha Faculty of Engineering Benha University - Egypt Eman.salem@bhit.bu.edu.eg Hossam Labeb Electrical

More information

Datasheet SHF A Multi-Channel Error Analyzer

Datasheet SHF A Multi-Channel Error Analyzer SHF Communication Technologies AG Wilhelm-von-Siemens-Str. 23D 12277 Berlin Germany Phone +49 30 772051-0 Fax +49 30 7531078 E-Mail: sales@shf.de Web: http://www.shf.de Datasheet SHF 11104 A Multi-Channel

More information

Contents Circuits... 1

Contents Circuits... 1 Contents Circuits... 1 Categories of Circuits... 1 Description of the operations of circuits... 2 Classification of Combinational Logic... 2 1. Adder... 3 2. Decoder:... 3 Memory Address Decoder... 5 Encoder...

More information

DXP-xMAP General List-Mode Specification

DXP-xMAP General List-Mode Specification DXP-xMAP General List-Mode Specification The xmap processor can support a wide range of timing or mapping operations, including mapping with full MCA spectra, multiple SCA regions, and finally a variety

More information

COPYRIGHT 2011 AXON DIGITAL DESIGN BV ALL RIGHTS RESERVED

COPYRIGHT 2011 AXON DIGITAL DESIGN BV ALL RIGHTS RESERVED GFS-HFS-SFS100/110 3Gb/s, HD, SD frame synchronizer with optional audio shuffler A Synapse product COPYRIGHT 2011 AXON DIGITAL DESIGN BV ALL RIGHTS RESERVED NO PART OF THIS DOCUMENT MAY BE REPRODUCED IN

More information

Metastability Analysis of Synchronizer

Metastability Analysis of Synchronizer Forn International Journal of Scientific Research in Computer Science and Engineering Research Paper Vol-1, Issue-3 ISSN: 2320 7639 Metastability Analysis of Synchronizer Ankush S. Patharkar *1 and V.

More information

TAXI -compatible HOTLink Transceiver

TAXI -compatible HOTLink Transceiver TAXI -compatible HOTLink Transceiver TAXI -compatible HOTLink Transceiver Features Second-generation HOTLink technology AMD AM7968/7969 TAXIchip -compatible 8-bit 4B/5B or 10-bit 5B/6B NRZI encoded data

More information

Draft Baseline Proposal for CDAUI-8 Chipto-Module (C2M) Electrical Interface (NRZ)

Draft Baseline Proposal for CDAUI-8 Chipto-Module (C2M) Electrical Interface (NRZ) Draft Baseline Proposal for CDAUI-8 Chipto-Module (C2M) Electrical Interface (NRZ) Authors: Tom Palkert: MoSys Jeff Trombley, Haoli Qian: Credo Date: Dec. 4 2014 Presented: IEEE 802.3bs electrical interface

More information

Using the MAX3656 Laser Driver to Transmit Serial Digital Video with Pathological Patterns

Using the MAX3656 Laser Driver to Transmit Serial Digital Video with Pathological Patterns Design Note: HFDN-33.0 Rev 0, 8/04 Using the MAX3656 Laser Driver to Transmit Serial Digital Video with Pathological Patterns MAXIM High-Frequency/Fiber Communications Group AVAILABLE 6hfdn33.doc Using

More information

Programmable Pattern Generator For 10GBASE-R/W. Jonathan Thatcher. World Wide Packets

Programmable Pattern Generator For 10GBASE-R/W. Jonathan Thatcher. World Wide Packets Programmable Pattern Generator For 10GBASE-R/W Jonathan Thatcher World Wide Packets Motivation n Motivation: provide a simple to implement, programmable pattern generator. n Rationale: it is not clear

More information

Therefore, HDCVI is an optimal solution for megapixel high definition application, featuring non-latent long-distance transmission at lower cost.

Therefore, HDCVI is an optimal solution for megapixel high definition application, featuring non-latent long-distance transmission at lower cost. Overview is a video transmission technology in high definition via coaxial cable, allowing reliable long-distance HD transmission at lower cost, while complex deployment is applicable. modulates video

More information

TAXI -compatible HOTLink Transceiver

TAXI -compatible HOTLink Transceiver TAXI -compatible HOTLink Transceiver Features Second-generation HOTLink technology AMD AM7968/7969 TAXIchip -compatible 8-bit 4B/5B or 10-bit 5B/6B NRZI encoded data transport 10-bit or 12-bit NRZI pre-encoded

More information

Essentials of HDMI 2.1 Protocols

Essentials of HDMI 2.1 Protocols Essentials of HDMI 2.1 Protocols for 48Gbps Transmission Neal Kendall Product Marketing Manager Teledyne LeCroy quantumdata Product Family neal.kendall@teledyne.com December 19, 2017 Agenda Brief review

More information

Training & EEE Baseline Proposal

Training & EEE Baseline Proposal Training & EEE Baseline Proposal IEEE 802.3bp - Plenary Meeting - November 2014 William Lo, Zhenyu Liu, Marvell 1 Baseline Proposal Adopt training and EEE framework in this presentation as baseline Based

More information

10G-BASE-T. Jaime E. Kardontchik Stefan Wurster Carlos Laber. Idaho - June

10G-BASE-T. Jaime E. Kardontchik Stefan Wurster Carlos Laber. Idaho - June 10G-BASE-T Jaime E. Kardontchik Stefan Wurster Carlos Laber Idaho - June 1999 email: kardontchik.jaime@microlinear.com Introduction This proposal takes the best parts of several proposals that preceded

More information

Improvements to Boundary Clock Based Time Synchronization through Cascaded Switches. Sihai Wang Samsung Electronics

Improvements to Boundary Clock Based Time Synchronization through Cascaded Switches. Sihai Wang Samsung Electronics Improvements to Boundary Clock Based Time hronization through Cascaded Switches Sihai Wang Samsung Electronics sihai.wang@samsung.com Outline Introduction to IEEE-1588 (PTP) hronization-capable Clock Improved

More information

REPORT/GATE FORMAT. Ed Boyd, Xingtera Supporters: Duane Remein, Huawei

REPORT/GATE FORMAT. Ed Boyd, Xingtera Supporters: Duane Remein, Huawei REPORT/GATE FORMAT Ed Boyd, Xingtera Supporters: Duane Remein, Huawei 1 Overview EPON defines a physical layer for 1Gbps and 10Gbps. EPoC requires more granularity and flexibility to adapt to limited spectrum

More information

IN DIGITAL transmission systems, there are always scramblers

IN DIGITAL transmission systems, there are always scramblers 558 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 53, NO. 7, JULY 2006 Parallel Scrambler for High-Speed Applications Chih-Hsien Lin, Chih-Ning Chen, You-Jiun Wang, Ju-Yuan Hsiao,

More information

Design and FPGA Implementation of 100Gbit/s Scrambler Architectures for OTN Protocol Chethan Kumar M 1, Praveen Kumar Y G 2, Dr. M. Z. Kurian 3.

Design and FPGA Implementation of 100Gbit/s Scrambler Architectures for OTN Protocol Chethan Kumar M 1, Praveen Kumar Y G 2, Dr. M. Z. Kurian 3. International Journal of Computer Engineering and Applications, Volume VI, Issue II, May 14 www.ijcea.com ISSN 2321 3469 Design and FPGA Implementation of 100Gbit/s Scrambler Architectures for OTN Protocol

More information

FEC IN 32GFC AND 128GFC. Scott Kipp, Anil Mehta June v0

FEC IN 32GFC AND 128GFC. Scott Kipp, Anil Mehta June v0 FEC IN 32GFC AND 128GFC Scott Kipp, Anil Mehta skipp@brocade.com June 2013 13-216v0 1 FEC For Lower Cost and Longer Reach Forward Error Correction (FEC) began to be used in Backplane Ethernet and has proliferated

More information

Investigation on Technical Feasibility of Stronger RS FEC for 400GbE

Investigation on Technical Feasibility of Stronger RS FEC for 400GbE Investigation on Technical Feasibility of Stronger RS FEC for 400GbE Mark Gustlin-Xilinx, Xinyuan Wang, Tongtong Wang-Huawei, Martin Langhammer-Altera, Gary Nicholl-Cisco, Dave Ofelt-Juniper, Bill Wilkie-Xilinx,

More information

REGIONAL NETWORKS FOR BROADBAND CABLE TELEVISION OPERATIONS

REGIONAL NETWORKS FOR BROADBAND CABLE TELEVISION OPERATIONS REGIONAL NETWORKS FOR BROADBAND CABLE TELEVISION OPERATIONS by Donald Raskin and Curtiss Smith ABSTRACT There is a clear trend toward regional aggregation of local cable television operations. Simultaneously,

More information

Commsonic. Satellite FEC Decoder CMS0077. Contact information

Commsonic. Satellite FEC Decoder CMS0077. Contact information Satellite FEC Decoder CMS0077 Fully compliant with ETSI EN-302307-1 / -2. The IP core accepts demodulated digital IQ inputs and is designed to interface directly with the CMS0059 DVB-S2 / DVB-S2X Demodulator

More information

OPTOCORE Technology Overview. Topology and Connection Set-up. Yamaha Emulation Mode (YEM) Ring Topology

OPTOCORE Technology Overview. Topology and Connection Set-up. Yamaha Emulation Mode (YEM) Ring Topology Technology Overview is a synchronous, redundant, optical ring network capable to transport audio, video, control data and word clock over extremely long distances. The large variety of modules can all

More information

Analog to digital A/V (12 bit) bridge with SDI & embedded audio bypass/processing input COPYRIGHT 2010 AXON DIGITAL DESIGN BV ALL RIGHTS RESERVED

Analog to digital A/V (12 bit) bridge with SDI & embedded audio bypass/processing input COPYRIGHT 2010 AXON DIGITAL DESIGN BV ALL RIGHTS RESERVED Analog to digital A/V (12 bit) bridge with SDI & embedded audio bypass/processing input A Synapse product COPYRIGHT 2010 AXON DIGITAL DESIGN BV ALL RIGHTS RESERVED NO PART OF THIS DOCUMENT MAY BE REPRODUCED

More information

Functional Diagram: Figure 1 PCIe4-SIO8BX-SYNC Block Diagram. Chan 1-4. Multi-protocol Transceiver. 32kb. Receiver FIFO. 32kb.

Functional Diagram: Figure 1 PCIe4-SIO8BX-SYNC Block Diagram. Chan 1-4. Multi-protocol Transceiver. 32kb. Receiver FIFO. 32kb. PCIe4-SIO8BX-SYNC High Speed Eight Channel Synchronous Serial to Parallel Controller Featuring RS485/RS232 Serial I/O (Software Configurable) and 32k Byte FIFO Buffers (512k Byte total) The PCIe4-SI08BX-SYNC

More information

Rec. ITU-R BT RECOMMENDATION ITU-R BT * WIDE-SCREEN SIGNALLING FOR BROADCASTING

Rec. ITU-R BT RECOMMENDATION ITU-R BT * WIDE-SCREEN SIGNALLING FOR BROADCASTING Rec. ITU-R BT.111-2 1 RECOMMENDATION ITU-R BT.111-2 * WIDE-SCREEN SIGNALLING FOR BROADCASTING (Signalling for wide-screen and other enhanced television parameters) (Question ITU-R 42/11) Rec. ITU-R BT.111-2

More information

AT660PCI. Digital Video Interfacing Products. DVB-S2/S (QPSK) Satellite Receiver & Recorder & TS Player DVB-ASI & DVB-SPI outputs

AT660PCI. Digital Video Interfacing Products. DVB-S2/S (QPSK) Satellite Receiver & Recorder & TS Player DVB-ASI & DVB-SPI outputs Digital Video Interfacing Products AT660PCI DVB-S2/S (QPSK) Satellite Receiver & Recorder & TS Player DVB-ASI & DVB-SPI outputs Standard Features - PCI 2.2, 32 bit, 33/66MHz 3.3V. - Bus Master DMA, Scatter

More information

Further Studies of FEC Codes for 100G-KR

Further Studies of FEC Codes for 100G-KR Further Studies of FEC Codes for 100G-KR Nov. 2011, IEEE 802.3bj Meeting, Atlanta Zhongfeng Wang, Hongtao Jiang, and Chung-Jue Chen Broadcom Corp., USA Introduction Incoming data is coded with 64B/66B

More information

8b10b Macro. v2.0. This data sheet defines the functionality of Version 1.0 of the 8b10b macro.

8b10b Macro. v2.0. This data sheet defines the functionality of Version 1.0 of the 8b10b macro. v2.0 8b10b Macro Product Summary Gigabit Ethernet 8b10b Function 125 MHz Operation Transmit and Receive Function isparity and Illegal Code Error Checking Connects directly to industry-standard Gigabit

More information

PAM8 Baseline Proposal

PAM8 Baseline Proposal PAM8 Baseline Proposal Authors: Chris Bergey Luxtera Vipul Bhatt Cisco Sudeep Bhoja Inphi Arash Farhood Cortina Ali Ghiasi Broadcom Gary Nicholl Cisco Andre Szczepanek -- InPhi Norm Swenson Clariphy Vivek

More information

MIPI D-PHY Bandwidth Matrix Table User Guide. UG110 Version 1.0, June 2015

MIPI D-PHY Bandwidth Matrix Table User Guide. UG110 Version 1.0, June 2015 UG110 Version 1.0, June 2015 Introduction MIPI D-PHY Bandwidth Matrix Table User Guide As we move from the world of standard-definition to the high-definition and ultra-high-definition, the common parallel

More information

Update on FEC Proposal for 10GbE Backplane Ethernet. Andrey Belegolovy Andrey Ovchinnikov Ilango. Ganga Fulvio Spagna Luke Chang

Update on FEC Proposal for 10GbE Backplane Ethernet. Andrey Belegolovy Andrey Ovchinnikov Ilango. Ganga Fulvio Spagna Luke Chang Update on FEC Proposal for 10GbE Backplane Ethernet Andrey Belegolovy Andrey Ovchinnikov Ilango Ganga Fulvio Spagna Luke Chang 802.3ap FEC Proposal IEEE802.3ap Plenary Meeting Vancouver, Nov14-17 2005

More information

Chapter 9 MSI Logic Circuits

Chapter 9 MSI Logic Circuits Chapter 9 MSI Logic Circuits Chapter 9 Objectives Selected areas covered in this chapter: Analyzing/using decoders & encoders in circuits. Advantages and disadvantages of LEDs and LCDs. Observation/analysis

More information

Altera JESD204B IP Core and ADI AD9144 Hardware Checkout Report

Altera JESD204B IP Core and ADI AD9144 Hardware Checkout Report 2015.12.18 Altera JESD204B IP Core and ADI AD9144 Hardware Checkout Report AN-749 Subscribe The Altera JESD204B IP core is a high-speed point-to-point serial interface intellectual property (IP). The JESD204B

More information

Asynchronous IC Interconnect Network Design and Implementation Using a Standard ASIC Flow

Asynchronous IC Interconnect Network Design and Implementation Using a Standard ASIC Flow Asynchronous IC Interconnect Network Design and Implementation Using a Standard ASIC Flow Bradley R. Quinton*, Mark R. Greenstreet, Steven J.E. Wilton*, *Dept. of Electrical and Computer Engineering, Dept.

More information

LINEAR DIGITAL RECORDER WITH 100 MBYTE/SEC HIPPI INTERFACE

LINEAR DIGITAL RECORDER WITH 100 MBYTE/SEC HIPPI INTERFACE LINEAR DIGITAL RECORDER WITH 100 MBYTE/SEC HIPPI INTERFACE John C. Webber Interferometrics Inc. 14120 Parke Long Court Chantilly, VA 22021 (703) 222-5800 webber@interf.com SUMMARY A plan has been formulated

More information

EE273 Lecture 14 Synchronizer Design November 11, Today s Assignment

EE273 Lecture 14 Synchronizer Design November 11, Today s Assignment 273 Lecture 14 Synchronizer esign November 11, 1998 William J. ally Computer Systems Laboratory Stanford University billd@csl.stanford.edu 1 Today s Assignment Term Project design a signaling system entire

More information

Lecture 10: Sequential Circuits

Lecture 10: Sequential Circuits Introduction to CMOS VLSI esign Lecture 10: Sequential Circuits avid Harris Harvey Mudd College Spring 2004 1 Outline Floorplanning Sequencing Sequencing Element esign Max and Min-elay Clock Skew Time

More information

COPYRIGHT 2016 AXON DIGITAL DESIGN BV ALL RIGHTS RESERVED

COPYRIGHT 2016 AXON DIGITAL DESIGN BV ALL RIGHTS RESERVED HD, SD SDI VBI/VANC encoder A Synapse product COPYRIGHT 2016 AXON DIGITAL DESIGN BV ALL RIGHTS RESERVED NO PART OF THIS DOCUMENT MAY BE REPRODUCED IN ANY FORM WITHOUT THE PERMISSION OF AXON DIGITAL DESIGN

More information

Lossless Compression Algorithms for Direct- Write Lithography Systems

Lossless Compression Algorithms for Direct- Write Lithography Systems Lossless Compression Algorithms for Direct- Write Lithography Systems Hsin-I Liu Video and Image Processing Lab Department of Electrical Engineering and Computer Science University of California at Berkeley

More information