MODU LE DAY. Class-A, B, AB and C amplifiers - basic concepts, power, efficiency Basic concepts of Feedback and Oscillation. Day 1

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1 DAY MODU LE TOPIC QUESTIONS Day 1 Day 2 Day 3 Day 4 I Class-A, B, AB and C amplifiers - basic concepts, power, efficiency Basic concepts of Feedback and Oscillation Phase Shift Wein Bridge oscillators. 1. Explain the operation with diagram of class A resistive load power amplifier. 2. Explain the operation with diagram of class B push pull amplifier. 3. Class B push pull amplifier use as? 4. Write down the advatages of class B push pull amplifier. 5. Draw and explain RC phase shift using Operational amplifier. 6. Draw and explain Wein Bridge oscillators. Question 7 : Explain the Astable Multivibrators and write down one application. Question 8 : Draw and explain with one application of 555 Timer. Day 5 Day 6 Day 7 II Astable & Monostable Multivibrators Schimtt Trigger circuits 555 Timer 1. Explain the Astable Multivibrators and write down one application. 2. Draw and explain with one application of 555 Timer. Day 8 III BCD, ASCII, EBDIC, Gray codes and their conversions 1 Convert the number ( )10 to binary. 2 Convert the gray code word to binary 3 Subtract 748 from 983 using 9 s complement 4 Convert the number (0.45)10 to octal number. 5 Convert the number (348.35)10 to hexadecimal number. 6 Convert the decimal 9826 to both BCD and ASCII codes. 7 Convert binary (10110)2 to gray code. 8 Briefly explain BCD code. What are its advantages and disadvantages. 9 What is the importance of gray code? 10 Decode the ASCII code

2 Day 9 Signed binary number representation with 1 s and 2 s complement methods 1 Find the 1 s and 2 s complement of ( )2 (Using formula). 2 Using 1 s complement, subtract ( )2 ( )2. 3 Distinguish between 1 s complement and 2 s complement. 4 Subtract (7A)16 from (CO)16. 5 Find the twos complement of the number Represent (+15)10 and (-15)10 in 1 s complement form 7 Use 8-bit 2 s complement arithmetic to subtract Add +38 and -22 using 2 s complement method 9 Determine the base of the numbers where 54/4= Determine the base of the numbers where 24+17=40. Day 10 Binary arithmetic, Venn diagram, Boolean algebra (recapitulation) 1 Add the binary numbers and Represent the decimal number in BCD addition Multiply (1011)2 by (101)2 4 Divide ( )2 by (1001)2 5 Add the binary numbers: Perform binary subtraction using 2 s complement representation of negative numbers. 5-7=? 7 Add (23)8 + (67)8 8 Subtract (37)8 from (53) divide by Subtract

3 Day 11 Representation in SOP and POS forms, Minimization of logic expressions by algebraic method 1 Apply DeMorgan s theorem to the following expressions(a) (A+B+C) (b) ABC+DEF 2 Simplify F = (A+B)(A+C)(B+C) 3 Reduce the expression A[B+C(AB+AC)] 4 Express the Boolean function F=A+B C in a sum of minterms. 5 Express the Boolean function F=xy+x z in a standard product of maxterm form. 6 Simplify the following three variable expression using algebric simplification Y = m(1,3,5,7) 7 If AB+AB=C, show that AC+AC=B 8 Simplify the expression Y= m (3,4,5,7,9,13,14,15) using K-map method. 9 Simplify the expression Y = (0,1,4,5,6,8,9,12,13,14) using K-map. 10 Obtain (a) minimal SOP and (b) minimal POS for the following expression F(A,B,C,D) = m (0,1,2,5,8,9,10) Day 12&13 IV Adder and Subtractor circuits (half & full adder & subtractor), Encoder, Decoder 1. Design a simple circuit based on combinational logic to double the output frequency 2.Design a COMBINATIONAL circuit that can divide the clock frequency by Convert a 2-input NAND gate into an inverter. 4. Design a 8:3 encoder using 4:2 encoders. 5. Design a 3:8 decoder using 2:4 decoders. Day 14 Comparator, Multiplexer, De-Multiplexer and Parity Generator 1. Implement the following Boolean function using 8:1 MUX:

4 F(A,B,C,D)= m 0+m 1+m 2+m 3+m 4+m 9+m What are the differences between a MUX and a DEMUX. 3. Design a 16:1 MUX using 4:1 and 2:1 MUX. 4. What is the difference between a DEMUX and Decoder. 5. Design a 3bit parity generator and checker circuit. 1. Basic Difference between a combinational and sequential circuit. Day 15 V Basic Flip-flop & Latch 2. Basic Difference between a latch and a flipflop. 3. Draw a block diagram (not a gate-level diagram) of a D latch and a D flip-flop. Show and label all inputs and outputs. 4. Write the truth tables for both a D latch and a D flipflop. 5. Discuss the applications, advantages and disadvantages of Positive and negative, level and edge triggered flipflops.

1. Determine the final output states over time for the following circuit, built from D-type gated latches: At what specific times in the pulse diagram does the final output assume the input s state?

The logic level at the D input is transferred to Q on NGT of CLK. b. The Q output is ALWAYS identical to the CLK input if the D input is HIGH. c.

5 1. Determine the final output states over time for the following circuit, built from D-type gated latches: At what specific times in the pulse diagram does the final output assume the input s state? How does this behavior differ from the normal response of a D-type latch? 2. Which statement BEST describes the operation of a negative-edge-triggered D flip-flop? Day 16 Flip-flops - SR, JK, D, T a. The logic level at the D input is transferred to Q on NGT of CLK. b. The Q output is ALWAYS identical to the CLK input if the D input is HIGH. c. The Q output is ALWAYS identical to the D input when CLK = PGT. d. The Q output is ALWAYS identical to the D input. 3. How is a J-K flip-flop made to toggle? a. J = 0, K = 0 b. J = 1, K = 0 c. J = 0, K = 1 d. J = 1, K = 1 4. The phenomenon of interpreting unwanted signals on J and K while Cp (clock pulse) is HIGH is called. a. parity error checking b. ones catching c. digital discrimination d. digital filtering 5. A PN FF has 4 operations; clear to 0, no change, complement and set to 1, when the inputs P and N are 00,01,10 and 11 respectively. Tabulate the characteristics table,derive the equation and tabulate the excitation table. 6. Realize a D FF using SR FF.

6 Day 17 JK Master-slave Flip Flops 1. What is race around condition? The asynchronous input can be used to set the flipflop to the a) 1 state b) 0 state c) either 1 or 0 state d) None of the Mentioned 2. Input clock of RS flip-flop is given to a) Input b) Pulser c) Output d) Master slave flip-flop 3. D flip-flop is a circuit having a) 2 NAND gates b) 3 NAND gates c) 4 NAND gates d) 5 NAND gates 4. In JK flip flop same input, i.e. at a particular time or during a clock pulse, the output will oscillate back and forth between 0 and 1. At the end of the clock pulse the value of output Q is uncertain. The situation is referred to as? a) Conversion condition b) Race around condition c) Lock out state d) None of the Mentioned 5. Master slave flip flop is also referred to as? a) Level triggered flip flop b) Pulse triggered flip flop c) Edge triggered flip flop d) None of the Mentioned 6. In a positive edge triggered JK flip flop, a low J and low K produces? a) High state b) Low state c) Toggle state d) None of the Mentioned 7. If one wants to design a binary counter, preferred type of flip-flop is a) D type b) S-R type c) Latch d) J-K type 8. S-R type flip-flop can be converted into D type flipflop if S is connected to R through a) OR Gate b) Inverter c) AND Gate d) Full Adder 9. Which of the following flip-flops is free from race around problem? a) T flip-flop b) SR flip-flop c) Master-Slave Flip-flop d) None of the Mentioned 10. Which of the following is the Universal Flip-flop? a) S-R flip-flop b) J-K flip-flop c) Master slave flip-flop d) D Flip-flop 11. How race around condition can be eliminated?

7 1. Describe the characteristics of shift registers. 2. What is the difference between serial and parallel transfer? Explain how to convert the serial data to parallel and vice versa. What type of register is needed. 3. The content of a 4-bit register is initially The register is shifted six times to the right with the serial input being What is the content of the register after each shift. Day 18 Registers - SISO, SIPO,PIPO,PISO, 4. Draw the logic diagram of a 4-bit register with four D-FF and four 4x1 mux with mode selection inputs s1 and s0. The register operates according to the following function table: S S Reg Op No change 0 1 Complemen t the 4 outputs 1 0 Clear registers 1 1 Load parallel data 5. Explain the operation of Universal Shift registers.

8 Day 19 VI Counters, Ring counter, Johnson counter 1. To turn any counter into a "count-down" counter (i.e. a two-bit "count-down" counter will count 11, 10, 01, 00, 11,...), you can XOR each of the output bits with 1, thus inverting them. XORing with 0, of course, doesn't change the output. Draw a two-bit counter with inputs "up" and "down" (in addition to the common clock). A third flip-flop stores whether or not the counter should currently be counting up or down; the "up" input makes the clock start counting up and the "down" input makes the clock start counting down. (The "up" or "down" input will be held at 1 for at least a clock cycle, and it doesn't matter what happens while it's being held at 1.) 2. Design a three-bit "counter" which counts 0, 3, 6, 1, 4, 7, 2, 5, 0, 3, Design a 4-bit Ring counter and Johnson s Counter.

9 Day 20 Basic concept of Synchronous and Asynchronous counters 1. Discuss the difference between synchronous and asynchronous counters. 2. Show that a BCD ripple counter can be constructed using a 4-bit binary ripple counter with asynchronous clear and a NAND gate that detects the occurrence of count Design a 3-bit binary synchronous down-counter using J-K flip-flops. First, draw the state bubble diagram, showing the 3-bit flip-flop outputs as the state. Draw the circuit diagram, using flip-flops as blocks (don t draw the individual gates in each flip-flop). Show and label all inputs and outputs. Assume the J-K flipflops are rising-edge-triggered. 2. Design MOD 4 synchronous counter using JK FF. Day 21 Design of Mod N Counter 3. Design a synchronous counter for counting the sequence 4,6,7,3,1,4, avoid lockout using JK FF. 4. Design a synchronous binary MOD 6 counter. 5. Design a counter with the irregular binary count sequence of 1,2,5 and 7 6. How many flipflops will be complemented in a 10-bit binary ripple counter to reach the next count after the following count: a b

10 Day 22 D/A conversion techniques Basic concepts (D/A :R-2-R only) 1. Draw and explain the R-2-R D/A converter. Day 23 A/D conversion techniques A/D: successive approximation 1. Draw and explain the A/D: successive approximation. VII Day 24 Logic Families - TTL, ECL 1. Write down the advantage of TTL over other logic families. 2. Draw and explain emitter coupled logic. Day 25 VIII MOS and CMOS - basic concepts. 1. Write down the advatages of CMOS.

1. Convert the decimal number to binary, octal, and hexadecimal.

1. Convert the decimal number 435.64 to binary, octal, and hexadecimal. 2. Part A. Convert the circuit below into NAND gates. Insert or remove inverters as necessary. Part B. What is the propagation delay