Little Logic Guide. Gates Configurables Signal Switches Translators

Transcription

1 Little Logic Guide Gates Configurables Signal Switches Translators ti.com 08

2 Little Logic Guide Table of Contents Introduction As the world leader in logic, Texas Instruments (TI) offers a full spectrum of logic functions and technologies including BiCMOS, Bipolar, and the latest advanced CMOS families. TI offers the most advanced logic technology while still maintaining support for traditional logic products. Our logic portfolio includes: Over 000 functions Technologies from 0.8 V to 8 V Best in class End-of-Life policies Overview... Little Logic Products by Performance Logic Migration to.8-v Future Performance Comparisons... Gate Functions... Signal Switches... Configurables... LVT Translators... Packaging 7 Advanced Packaging...7 Little Logic Packaging...8 Little Logic Package Cross Reference...8 Selection Tables 9 Single-Gate Functions...9 Dual-Gate Functions... Triple-Gate Functions... Signal-Switch Functions.... Configurable Functions... Voltage Translation Functions... - Cross-Reference 7 Competitor Cross-Reference Part Number Definition.... Competitor Part Prefixes... Resources and Support TI Worldwide Technical Support.... Little Logic Guide 08 Texas Instruments

3 Little Logic Guide Overview WIN not only today s race, but tomorrow s with TI Little Logic Better engine, customer centric With TI s broad technical experience and application support in logic, analog and mixed signal designs, we provide our customers with gate functions, buffers/registers, level translators and switches in state-of-the art packaging. To better meet your growing needs, TI works closely with you to get your engine started. Faster time-to-market, easy-to-use Reaching faster time-to-market requires easier design routing and minimized development risk. Little Logic devices in TI s space saving packages are easy to implement, stay closer to the circuitry and help simplify board designs. Without time-consuming invention of new silicon, designers can reach better performance with ASIC designs by using Little Logic functions. More performance, one-stop selection TI s large portfolio includes single-, dualand triple-gates of the most popular functions in space saving packages to allow you the space you need. By replacing multiple devices through single configurable functions, Little Logic helps to reduce inventory. No pit-stop, ever TI Logic s stable no end-of-life policy secures that all products in our portfolio will always be available. This means more than 0,000 devices are orderable to support the widest range of applications and end-equipment at any time you need them. Little Logic s stable delivery culture is nothing new; it has lasted for more than 0 years. We help you to keep going and solve delivery issues. WIN with best-in-class support For more information on TI s Little Logic, call your local TI Field Sales office, your authorized TI distributor, or visit us at TI Logic Forces: Worldwide # vendor in the logic market Broadest portfolio of function and package combinations No end-of-life policy, the product you need is always available Biggest capacity in the market, no delivery pit-stop Best-in-class support for easier and faster design Before After Buffer Single gate µp Single gate µp Single gate Texas Instruments Little Logic Guide 08

4 Little Logic Products by Performance Logic Migration to.8-v Future Keep the pace, even longer! TI s numerous logic technologies with low power help designers extend battery life easily. With a varied operating voltage of. V down to 0.8 V, this graph shows how our devices work to keep your system running faster and longer. Supply voltage (V CC ) 0 + AHC 7.0 ns AHCT 7. ns. ns V +. V AHC 0. ns LVT 0 ns AUP. ns. ns +. ns AUP. ns.0 ns. V 7. ns AUP 8. ns. ns +.8 V. ns AUP 0. ns Technology advancement +. V. ns AUP. ns + +. V.7 ns AUP 8.0 ns 0.8 V Performance Comparisons Family Operating Voltage Range (V) Optimized Voltage (V) Propagation Delay - tpd (typ) (ns) Output Drive (ma) Input Tolerance (V) AUP 0.8 to.... Yes 0.8 to Yes. to...0. Yes AHC.0 to No AHCT. to No CBT. to Yes CBTD. to Yes CBTLV. to Yes CBT. to Yes LVT.8 to.. 7. No I OFF Protection The progagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). The value listed is a maximum. The FET switch has no output drive. The drive current at the output terminal is determined by the drive current of the device connected at the input terminal of the FET switch. Gate Functions Little Logic gates have all the features of their bigger cousins but in single, double, and triple gate functions. They cover the full range of voltages from 0.8 V to. V. They come in tiny packages making them excellent for handheld and any other equipment where space is a concern. Standard gates include: - and -input gates Schmitt trigger input gates -state output buffer Open drain output Power off Hi-Z Buffer decoder and multiplexer Latch and flip-flop Dual power rail translator Gate translations Advantages: I off supports hot insertion I off allows voltages on the inputs or outputs when V cc is at 0 V Shcmitt trigger input allows any slope on the rise and fall times Translators LVTxxx devices support both up and down translation. AUPTxx devices support up translation Over voltage tolerant on input allows down translation Open drain output enables up or down translation LVT (up or down translation) Operating range.8 V to. V Drive 7 ma at. V Speed 0 MHz at. V typical (fastest speed) Operating range 0.8 V to.7 V Drive ma at. V, 9 ma at. V Speed 0 MHz at. V typical AHC (low power) Operating range.0 V to. V Drive ma at. V, 8 ma at V Speed 0 MHz at V typical (high drive) Operating range. V to. V Drive ma at. V, ma at.0 V Speed 0 MHz at V typical AUP (lowest power less than 0.9 µa at. V) Operating range 0.8 V to. V Drive.9 ma at. V, ma at. V Speed 90 MHz at. V typical Little Logic Guide 08 Texas Instruments

5 Little Logic Products by Performance Signal Switches CBT (Bus switch) Operating range: -V to.-v V CC 0.-ns typical t pd SN7CBTG SN7CBTDG SN7CBTG8 SN7CBTDG8 CBTLV (low-voltage bus switch) Operating range:.-v to.-v V CC 0.-ns typical t pd SN7CBTLVG CBT (low-voltage translation bus switch) Operating range:.-v to.-v V CC 0.-ns typical t pd SN7CBTG (low-voltage CMOS) Operating range:.-v to.-v V CC.0-ns typical t pd SN7G SN7G7 SN7G SN7G (advanced ultra-low-voltage CMOS) Operating range: 0.8-V to.7-v V CC.0-ns typical t pd SN7G SN7G SN7G. V G TTL-to-LVTTL level shifter The G can be used for simple translation from -V TTL levels to LVTTL. The control pin is tolerant to. V and, with a maximum r ON of Ω at V CC =. V, the voltage drop across the switch is only 0. V with ma of through current. -V TTL Signal GND B A C V CC G LVTTL Visit for the application report, Selecting the Right TI Signal Switch. Texas Instruments Little Logic Guide 08

6 Little Logic Products by Performance Configurables The next-generation configurable devices in the Little Logic portfolio are the G97/98/99 functions in both the and AUP technologies. By providing nine single-gate logic solutions in the G97/98 and 0 functions in the G99, the devices allow reductions in device inventory and simplify part management. AUP (advanced ultra-low-power CMOS) Operating range: 0.8-V to.-v V CC.-ns typical t pd SN7AUPG7 SN7AUPG97 SN7AUPG99 SN7AUPG8 SN7AUPG98 C0 C08 C Inverter AND Inverter C7 C C7 Buffer OR Selector G97 C97 (low-voltage CMOS) Operating range:.8-v to.-v V CC.0-ns typical t pd SN7G7 SN7G97 SN7G99 SN7G8 SN7G98 C00 C0 C C7 C0 NAND NOR Inverter C8 Inverter Buffer Selector with Inverter G98 C98 LVT Translators LVT is the industry s first logic family of devices to fully integrate gate and up or down translation functionality operating from a single power supply. The LVT family is available in nine different logic gates which are NAND & AND, NOR, OR, and XOR as well as several different buffer functions giving the customer a wide portfolio of logic gate functions to choose from. Key Features Wide voltage range (.8-.0 V V cc ) Up-translation mode Down-translation mode 0º to ºC T a operation LVT Benefits More than 0% board reduction by integration of the logic gate function and the up and down level shifter Widest voltage range of.8 V to.0 V Single power supply enables ease of routing Single logic product family for three design modes Extended temperature range Applications Industrial - Metering Automotive Infotainment Computing Tablets, PC Personal Electronics Smartphones, Wearables. V CMOS Input (.8 V,. V,. V) V CC CMOS Output (. V) T00 T0 T0 LVTTL/CMOS (. V) T08 T T T8 T T LVT Family Functions Little Logic Guide 08 Texas Instruments

7 Packaging Advanced Packaging Electronic development continues to grow into new and innovative markets. Since innovation often means shrinking size, packaging finds itself in the forefront of enabling new features. The ability to further customize packaging for medical, automotive and industrial applications is playing a bigger role meeting new desires and enabling solutions that were not possible in the past. Meeting today s dynamic market needs for advanced package solutions like size, thermal, electrical, and cost is more exciting than ever. needs. The broad TI NanoStarTM and μqfn package portfolio continues to offer more performance at a smaller size to solve design issues. TI has developed and qualified fine pitch options in both package nodes. µqfn (0.mm pitch DSF package) Smallest line pitch, µqfn package in full production today Over 0% smaller than the original, 0. mm pitch µqfn package Our latest NanoStarTM additions include small, 0. mm pitch offerings such as 0. mm x 0.9 mm x 0. mm, -pin packages that are easy-to-use in smaller and thinner end applications. µqfn (0.0 mm pitch DPW package) % Smaller than DRY (0. mm pitch) package % Smaller than DSF (0. mm pitch) package 0. mm pitch enables ease of manufacturing Sampling multiple functions across /AUP Direct cross to NXP GX package The µqfn portfolio now includes the world s smallest 0.8 mm x 0.8 mm (0. mm pitch) package, called the DPW package. TI continues to invest in innovative solutions to be a leader in package development and offers two distinct package type solutions to address today s, as well as tomorrow s, market % Smaller % Smaller QFN µqfn µqfn (DPW) Little Logic Package Trend QFN x. x 0. (H) Lead Pitch 0. µqfn x x 0. (H) Lead Pitch 0.. x. x 0. (H) Lead Pitch 0. WCSP 0.9 x. x 0. (H) Lead Pitch 0. WCSP (YZV) 0.9 x 0.9 x 0. (H) Lead Pitch 0. WCSP 0.77 x.7 x 0. (H) Lead Pitch 0. WCSP 0.77 x.7 x 0. (H) Lead Pitch 0. WCSP 0.77 x.77 x 0. (H) Lead Pitch 0. SOT- (DBV).9 x.8 x. (H) Lead Pitch 0.9 DRL SC-70 (DCK) x. x. (H) Lead Pitch 0. µqfn (DPW) 0.8 x 0.8 x 0. (H) Lead Pitch 0. Development Texas Instruments Little Logic Guide 08 7

8 Packaging Little Logic Packaging YFP YZP DCK DBV DCT DCU DRY DSF DQE RSE YZV DRL 8-Ball -Ball -Ball 8-Ball -/-Ball -/-Pin -/-Pin 8-Pin 8-Pin -Pin -Pin 8-Pin 8-Pin -Ball -/-Pin DPW -Pin Package Sizes YFP YZP DCK DBV DCT DCU DRY DSF DQE RSE YZV DRL DPW Package YFP YFP YFP YZP YZP DCK DBV DCT DCU DRY DSF DQE RSE YZV DRL DPW Pin 8-ball -ball -ball 8-ball -/-ball -/-pin -/-pin 8-pin 8-pin -pin -pin 8-pin 8-pin -ball -/-pin -pin Height (inches) (mm) Area (sq. inches) (sq. mm) Little Logic Packaging Cross-Reference Cross-Reference Device TI Fairchild ON Toshiba NXP Pericom STMicro NanoStar Package WCSP YZP L SOT- (-pin) DBV M DT F GV TX ST SC-70 (-pin) DCK P DF FU GW CX CT SOT- (-pin) DBV DT GV SC-70 (-pin) DCK P DF DW SSOP (8-pin) DCT FU VSSOP (8-pin) DCU K8 US FK DC SOT (-pin) DRL XVT ESV NanoStar (-ball) YZV Micro QFN (8-pin) DQE Micro QFN (8-pin) RSE L8 MU GM Micro QFN (-pin) DRY L AM GM Micro QFN (-pin) DSF FH CM GF Micro QFN (-pin) DPW GX TI package suffix decoder Pitch (inches) (mm) Length (inches) (mm) Width (inches) (mm) YZP is NanoStar package YZV is NanoStar package DBV is - and -pin leadframe DCK is - and -pin leadframe, slightly smaller than DBV DCT is 8-pin leadframe DCU is 8-pin leadframe, slightly smaller than DCT DRL is -pin plastic small-outline 8 Little Logic Guide 08 Texas Instruments

9 Selection Tables Single-Gate Functions Single-Gates Function Description SOT- (DBV) (DCK) US8 (DCU) XSON (DQE) SOT (DRL) XSON UQFN (RSE) (YZV) µqfn (DPW) G00 Single -Input NAND Gate X X X X X X X G0 Single -Input NOR Gate X X X X X X X G0 Single Inverter X X X X X X X X Gu0 Single Unbuffered Inverter X X X X X X X Gx0 Crystal Oscillator Driver X X X G0 Single Inverter Buffer/Driver w/open Drain Output X X X X X X X G07 Single Buffer/Driver w/open Drain Output X X X X X X X X G08 Single -Input AND Gate X X X X X X X G0 Single -Input NAND Gate X X X X X G Single -Input AND Gate X X X X X G Single Schmitt Trigger Inverter X X X X X X X G7 Single Schmitt Trigger Buffer X X X X X X X X G8 of Non-Inverting MUX X X X X X G9 of Decoder/Demultiplexer X X X X X G7 Single -Input NOR Gate X X X X X G9 of Decoder/Demultiplexer X X X G Single -Input OR Gate X X X X X X X G Single Buffer Gate X X X X X X X X X G8 Single -Input NAND Gate w/open Drain Output X X X X X G7 Single Positive-Edge-Triggered D-Type Flip-Flop X X X X G79 Single D-Type Flip-Flop X X X X G80 Single D-Type Flip-Flop X X X G8 Single -Input Exclusive-OR Gate X X X X G Single Retrig Monostable w/schmitt Trigger Inputs X X X G Single Bus Buffer Gate w/-state Output X X X X X X X G Single Bus Buffer Gate w/-state Output X X X X X X G Single -input NAND gate with Schmitt Trigger input X X X G9 -Line to -Line Decoder X X X G7 Single D-Type Flip-Flop w/asynch Clr X X X X G0 Single Buffer/Driver w/-state Output X X X X X G Single -Input OR Gate X X X X X G7 Single D-Type Latch w/-state Output X X X G7 Single D-Type Flip-Flop w/-state Output X X X G8 Single -Input Exclusive-OR Gate X X X X X G08 Single -Input Positive AND-OR Gate X X X G08 Single -Input Positive OR-AND Gate X X X AHCG00 Single -Input NAND Gate X X X AHCG0 Single -Input NOR Gate X X X AHCG0 Single Inverter X X X AHCGU0 Single Unbuffered Inverter X X X AHCG08 Single -Input AND Gate X X X AHCG09 Single -Input AND Gate w/ Open Drain Output X X AHCG Single Schmitt Trigger Inverter X X X AHCG Single -Input OR Gate X X X AHCG8 Single -Input Exclusive-OR Gate X X X AHCG Single Bus Buffer Gate w/-state Output X X X AHCG Single Bus Buffer Gate w/-state Output X X X G00 Single -Input NAND Gate X X X X G0 Single -Input NOR Gate X X X X G0 Single Inverter X X X X X Gu0 Single Unbuffered Inverter X X X G0 Single Inverter Buffer/Driver w/open Drain Output X X X G07 Single Buffer/Driver w/open Drain Output X X X G08 Single -Input AND Gate X X X X G Single Schmitt Trigger Inverter X X X G7 Single Schmitt Trigger Buffer X X X X G9 of Decoder/Demultiplexer X X X X G Single -Input OR Gate X X X X G7 Single Positive-Edge-Triggered D-Type Flip-Flop X X X X Texas Instruments Little Logic Guide 08 9

10 Selection Tables Single-Gate Functions Single-Gates (continued) Function Description SOT- (DBV) (DCK) G79 Single D-Type Flip-Flop X X X G80 Single D-Type Flip-Flop X X X G8 Single -Input Exclusive-OR Gate X X X G Single Bus Buffer Gate w/-state Output X X X G Single Bus Buffer Gate w/-state Output X X X G0 Single Buffer/Driver w/-state Output X X X US8 (DCU) XSON (DQE) SOT (DRL) XSON UQFN (RSE) (YZV) µqfn (DPW) AUPG00 Single -Input NAND Gate X X X X X X X X AUPG0 Single -Input NOR Gate X X X X X X X AUPG0 Single Inverter X X X X X X X AUPG0 Single Inverter Buffer/Driver w/open Drain Output X X X X X X AUPG07 Single Buffer/Driver w/open Drain Output X X X X X X X X AUPG08 Single -Input AND Gate X X X X X X X X AUPG Single Schmitt Trigger Inverter X X X X X X X AUPG7 Single Schmitt Trigger Buffer X X X X X X X AUPG Single -Input OR Gate X X X X X X X X AUPG Single Buffer Gate X X X X X X X X AUPG7 -Input Non-Inverting MUX X X X X X X X AUPG7 Single Positive-Edge-Triggered D-Type Flip-Flop X X X X X X AUPG79 Single D-Type Flip-Flop X X X X X X X AUPG80 Single D-Type Flip-Flop X X X X X X AUPG Single Bus Buffer Gate w/-state Output X X X X X X X AUPG Single Bus Buffer Gate w/-state Output X X X X X X X AUPG0 Single Buffer/Driver w/-state Output X X X X X X AHCTG00 Single -Input Positive-NAND Gate X X AHCTG0 Single -Input Positive-NOR Gate X X AHCTG0 Single Inverter Gate X X AHCTG08 Single -Input Positive-AND Gate X X X AHCTG Single Schmitt-Trigger Inverter Gate X X AHCTG Single -Input Positive-OR Gate X X X AHCTG8 Single -Input Exclusive-OR Gate X X AHCTG Single Bus Buffer Gate With -State Output X X X AHCTG Single Bus Buffer Gate With -State Output X X Function Description SOT- (DBV) (DCK) AUPT00 -Input NAND Gate X AUPT0 -Input NOR Gate X AUPT0 Inverter X AUPT08 -Input AND Gate X AUPT Schmitt Trigger Inverter X AUPT7 Schmitt Trigger Buffer X AUPT -Input OR Gate Single-Bit X AUPT Buffer/Driver X X X AUPT0 Schmitt Trigger Buffer/Driver X AUPT7 Single-Supply Voltage-Level Translator with 9 X X X X X X Configurable Gate Logic Functions AUPT8 Single-Supply Voltage-Level Translator with 9 X X X X X X Configurable Gate Logic Functions AUPT8 -Input Exclusive-OR Gate X US8 (DCU) SOT (DRL) XSON 0 Little Logic Guide 08 Texas Instruments

11 Little Logic Guide Single-Gate Functions Function Description SOT- (DBV) (DCK) US8 (DCU) SOT (DRL) XSON AUPT87 -Input Exclusive NOR Gate X AUPT97 Single-Supply Voltage-Level Translator with 9 X X X X X X Configurable Gate Logic Functions AUPT98 Single-Supply Voltage-Level Translator with 9 X X X X X X Configurable Gate Logic Functions AUPT7 to Data Selector/Multiplexer X AUPT8 -Input Multiplexer X Function Description SOT- (DBV) (DCK) US8 (DCU) SOT (DRL) (DPK) XSON LVT00 NAND Gate and/or Up/Down-Translator X X LVT0 Inverter Buffer/Driver and/or Up/Down-Translator X X LVT08 -Input AND Gate and/or Up/Down-Translator X X LVT0 -Input NOR Gate and/or Up/Down-Translator X X LVT -Input OR Gate and/or Up/Down-Translator X X LVT Single Buffer Gate X X LVT Buffer/Driver w/-state Output w/high Disabled and/or Up/Down-Translator X X LVT Buffer/Driver w/-state Outputs w/low Disabled and/or Up/Down-Translator X X LVT8 -Input Exclusive-OR (XOR) Gate and/or Up/Down- Translator X X Single-Gate Diagram Texas Instruments Little Logic Guide 08

12 Selection Tables Dual-Gate Functions Dual-Gates Function Description SOT- (DBV)- (DCK) G00 Dual -Input NAND Gate X X X G0 Dual -Input NOR Gate X X X G0 Dual Inverter X X X X GU0 Dual Unbuffered Inverter X X X G0 Dual Inverter w/open Drain Output X X X X X G07 Dual Non-Inverter w/open Drain Output X X X X X G08 Dual -Input AND Gate X X X G Dual Schmitt Inverter X X X G7 Dual Schmitt Trigger Input Buffers X X X X X G Dual -Input OR Gate X X X G Dual Non-Inverter X X X X G8 Dual -Input NAND Gate w/open Drain Output X X X G : Analog Multiplexer/Demultiplexer X X X G79 Dual Positive-Edge-Triggered D-Type Flip-Flop X X X G80 Dual Positive-Edge-Triggered D-Type Flip-Flop X X X G8 Dual -Input Exclusive-OR Gate X X X G Dual Bus Buffer Gate w/-state Outputs X X X G Dual Bus Buffer Gate w/-state Outputs X X X G Dual -Input NAND Gate with Schmitt-Trigger Inputs X X X G7 Single Line to Line Data Selector/Multiplexer X X X G0 Dual Bus Buffer Gate w/-state Outputs X X X G Dual Buffer/Driver w/-state Outputs X X X US8 (DCU) SOT (DRL) XSON XSON (DQE) UQFN (RSE) G00 Dual -Input NAND Gate X X X G0 Dual -Input NOR Gate X X X G0 Dual Inverter X X X GU0 Dual Unbuffered Inverter X X X X G0 Dual Inverter w/open Drain Output X X X G07 Dual Non-Inverter w/open Drain Output X X X G08 Dual -Input AND Gate X X X G Dual -Input OR Gate X X X G Dual Non-Inverter X X X X G : Analog Multiplexer/Demultiplexer X X X G79 Dual Positive-Edge-Triggered D-Type Flip-Flop X X X G80 Dual Positive-Edge-Triggered D-Type Flip-Flop X X X G8 Dual -Input Exclusive-OR Gate X X X G Dual Bus Buffer Gate w/-state Outputs X X X G Dual Bus Buffer Gate w/-state Outputs X X X X G0 Dual Bus Buffer Gate w/-state Outputs X X X G Dual Buffer/Driver w/-state Outputs X X X Little Logic Guide 08 Texas Instruments

13 Selection Tables Dual-Gate Functions Dual-Gates (continued) Function Description SOT- (DBV)- (DCK) AUPG00 Dual -Input NAND Gate X X X X AUPG0 Dual -Input NOR Gate X X X X AUPG0 Dual Inverter X X X X AUPG0 Dual Inverter w/open Drain Output X X X X AUPG07 Dual Non-Inverter w/open Drain Output X X X X AUPG08 Dual -Input AND Gate X X X X X AUPG Dual Schmitt Inverter X X X X AUPG7 Dual Schmitt Trigger Input Buffers X X X X AUPG Dual -Input OR Gate X X X X AUPG Dual Non-Inverter X X X X AUPG79 Dual Positive-Edge-Triggered D-Type Flip-Flop X X X X AUPG80 Dual Positive-Edge-Triggered D-Type Flip-Flop X X X X AUPG Dual Bus Buffer Gate w/-state Outputs X X X X X AUPG Dual Bus Buffer Gate w/-state Outputs X X X X X AUPG0 Dual Bus Buffer Gate w/-state Outputs X X X X AUPG Dual Buffer/Driver w/-state Outputs X X X X US8 (DCU) SOT (DRL) XSON XSON (DQE) UQFN (RSE) Dual-Gate Diagram G0/GU0 G0 G07 G00 G0 G08 G G7 8 7 G G 8 7 G8 8 7 G 8 7 S Q C D R Q G7 8 7 Q C D C D G79 Q 8 7 Q C D C D G80 Q 8 7 G G A B A/B Y Y G G G7 8 7 G0 8 7 G Texas Instruments Little Logic Guide 08

14 Selection Tables Triple-Gate Functions Triple-Gates Function Description US8 (DCU) XSON (DQE) UQFN (RSE) G0 Triple Inverter Gate X X X GU0 Triple Inverter Gate (Unbuffered) X X X G0 Triple Inverter Buffer/Driver w/open Drain Output X X X G07 Triple Buffer/Driver w/open Drain Output X X X G Triple Schmitt Trigger Inverter X X X G7 Triple Schmitt Trigger Buffer X X X G Triple Buffer Gate X X X AUPG0 Triple Inverter Gate X X X X AUPG0 Triple Inverter Buffer/Driver w/open Drain Output X X X X AUPG07 Triple Buffer/Driver w/open Drain Output X X X X AUPG Triple Schmitt Trigger Inverter X X X X AUPG7 Triple Schmitt Trigger Buffer X X X X AUPG Triple Buffer Gate X X X X Triple-Gate Diagram Signal-Switch Functions Signal-Switch Function Description SOT- (DBV)- (DCK)- CBTG Single FET Bus Switch X X CBTG8 Single FET Bus Switch X X CBTG Single FET Bus Switch X X CBTDG Single FET Bus Switch X X CBTDG8 Single FET Bus Switch X X CBTLVG Single FET Bus Switch X X SOT- (DBV)- (DCK)- US8 (DCU) SOT (DRL) SON SON G Single Analog Switch X X X X X X G7 Single-Pole, Double-Throw (SPDT) Analog Switch X X X X X X G Single-Pole, Double-Throw (SPDT) Analog Switch X X X G Dual Analog Switch X X X G Dual Analog Switch X X X G Single-Pole, Double-Throw (SPDT) Analog Switch X X X G Dual Analog Switch X X X Signal-Switch Diagram CBT CBT CBT CBTD CBTD CBTLV G G G8 G7 Little Logic Guide 08 G G Texas Instruments

15 Selection Tables Configurable Functions Configurables Function Description SOT- (DBV)- US8 (DCU) SOT (DRL) G7 Configurable Multiple-Function Gate X X X X X X G8 Configurable Multiple-Function Gate X X X X X X G97 Configurable Multiple-Function Gate X X X X X X G98 Configurable Multiple-Function Gate X X X X X X G99 Ultra-Configurable Multiple-Function Gate X X X (DCK) SON AUPG7 Configurable Multiple-Function Gate X X X X X X X AUPG8 Configurable Multiple-Function Gate X X X X X X X AUPG97 Configurable Multiple-Function Gate X X X X X X X AUPG98 Configurable Multiple-Function Gate X X X X X X X AUPG99 Ultra-Configurable Multiple-Function Gate X X X Configurable Diagrams AUP AUP AUP AUP 8 7 AUP G7 G8 G97 G98 G99 Voltage Translation Functions Single-Supply Function Description SOT- (DBV) AUPT00 -Input NAND Gate X AUPT0 -Input NOR Gate X AUPT0 Inverter X AUPT08 -Input AND Gate X AUPT Schmitt Trigger Inverter X AUPT7 Schmitt Trigger Buffer X AUPT -Input OR Gate Single-Bit X AUPT Buffer/Driver X X X AUPT0 Schmitt Trigger Buffer/Driver X AUPT7 Single-Supply Voltage-Level Translator with 9 Configurable Gate Logic Functions AUPT8 Single-Supply Voltage-Level Translator with 9 Configurable Gate Logic Functions AUPT8 -Input Exclusive-OR Gate X AUPT87 -Input Exclusive NOR Gate X AUPT97 Single-Supply Voltage-Level Translator with 9 Configurable Gate Logic Functions AUPT98 Single-Supply Voltage-Level Translator with 9 Configurable Gate Logic Functions AUPT7 to Data Selector/Multiplexer X AUPT8 -Input Multiplexer X (DCK) US8 (DCU) SOT (DRL) XSON X X X X X X X X X X X X X X X X X X X X X X X X Texas Instruments Little Logic Guide 08

16 Selection Tables Voltage Translation Functions Single-Supply (continued) Function Description SOT- (DBV) LVT00 NAND Gate and/or Up/Down-Translator X X LVT0 Inverter Buffer/Driver and/or Up/Down-Translator X X LVT08 -Input AND Gate and/or Up/Down-Translator X X LVT0 -Input NOR Gate and/or Up/Down-Translator X X LVT -Input OR Gate and/or Up/Down-Translator X X LVT Single Buffer Gate X X LVT LVT LVT8 Buffer/Driver w/-state Output w/high Disabled and/or Up/Down-Translator Buffer/Driver w/-state Outputs w/low Disabled and/or Up/Down-Translator -Input Exclusive-OR (XOR) Gate and/or Up/Down- Translator X X X (DCK) X X X US8 (DCU) SOT (DRL) (DPK) XSON Dual-Supply Function Description SOT- (DBV) (DCK) US8 (DCU) SOT (DRL) (DPK) XSON AVCT Dual-Supply Transceiver w/configurable Voltage Translation and -State Outputs X X X X AVCT Dual-Bit Dual-Supply Transceiver w/configurable Voltage Translation and -State Outputs X X X AVCHT AVCHT Dual-Supply Transceiver w/configurable Voltage Translation and -State Outputs Dual-Bit Dual-Supply Transceiver w/configurable Voltage Translation and -State Outputs X X X X X X T T Dual-Supply Transceiver w/configurable Voltage Translation and -State Outputs Dual-Bit Dual-Supply Transceiver w/configurable Voltage Translation and -State Outputs X X X X X X X Translation Diagrams T00 AUPT LVT T0 AUPT LVT T0 AUPT LVT T08 AUPT LVT T AUPT AUPT AUPT LVT T7 T T AUPT LVT T AVC AVCH 8 7 AVC AVCH AUPT AUPT AUPT LVT AUPT AUPT AUPT LVT T T7 T8 T8 T87 T97 T98 T LVT AUPT AUPT T T7 T8 Little Logic Guide 08 Texas Instruments

17 Cross-Reference Competitor Cross-Reference Devices Function Description TI () Single Gate Fairchild (NC7S/WZ) ON (SZ) ON (NLU) ON (NLX) Toshiba (TC7S/WZ) NXP () Pericom (STX) STMicro (LX) G00 Single -Input NAND SN7G00 NC7SZ00 NL7SZ00 NLUG00 TC7SZ00 7G00 7LXG00 G0 Single -Input NOR SN7G0 NC7SZ0 NL7SZ0 TC7SZ0 7G0 PI7STXG0 7LXG0 G0 Single Inverter SN7G0 NC7SZ0 NL7SZ0 NLUG0 TC7SZ0 7G0 7LXG0 GU0 Single Inverter (Unbuffered) SN7GU0 NC7SZU0 NL7SZU0 NLUGU0 TC7SZU0 7GU0 PI7STXGU0 7LXGU0 GX0 Crystal Driver SN7GX0 7GX0 G0 G07 Single Inverter Buffer/Driver w/open Drain Output Single Buffer/Driver w/open Drain Output SN7G0 NL7SZ0 7G0 SN7G07 NL7SZ07 NLUG07 TCSZ07 7G07 7LXG07 G08 Single -Input AND SN7G08 NC7SZ08 NL7SZ08 NLUG08 TC7SZ08 7G08 PI7STXG08 7LXG08 G0 Single -Input NAND SN7G0 NC7SZ0 7G0 G Single -Input AND SN7G NC7SZ 7G G G7 Single Inverter w/schmitt Trigger Single Buffer w/schmitt Trigger SN7G NC7SZ NL7SZ NLUG TC7SZ 7G 7LXG SN7G7 NL7SZ7 7G7 G8 of Non-Inverting MUX SN7G8 NC7SZ8 NL7SZ8 7G8 G9 of Decoder SN7G9 NC7SZ9 NL7SZ9 7G9 G7 Single -Input NOR SN7G7 NC7SZ7 G9 of Decoder/Demultiplexer SN7G9 G Single -Input OR SN7G NC7SZ NL7SZ NLUG TC7SZ 7G 7LXG G Single Buffer Gate SN7G NL7SZ TC7SZ 7G 7LXG70 G8 Single -Input NAND w/open Drain Output SN7G8 NC7SZ8 TC7SH 7G8 G79 Single D-Type Flip-Flop SN7G79 TC7SZ8 7G79 G80 Single D-Type Flip-Flop SN7G80 7G80 G8 Single -Input Exclusive-OR SN7G8 NC7SZ8 NL7SZ8 NLUG8 7G8 7LXG8 G G G Single Retrig Monostable Multivibrator Single-Bus Buffer Gate w/-state Single-Bus Buffer Gate w/-state G Single -Input NAND w/ Schmitt Trigger SN7G TC7SZ8 SN7G NC7SZ NL7SZ 7G 7LXG SN7G NC7SZ NL7SZ TC7SZ 7G PI7STXG 7LXG SN7G TC7SZ 7LXG G9 -Line to -Line Decoder SN7G9 G7 Single D-Type Flip-Flop w/ Asynch Clear G0 Single Bus Buffer Gate w/- State SN7G7 NC7SZ7 7G7 SN7G0 G Single -Input OR SN7G NC7SZ 7G Texas Instruments Little Logic Guide 08 7

18 Cross-Reference Competitor Cross-Reference Devices (continued) Function Description TI () Single Gate Fairchild (NC7S/WZ) ON (SZ) ON (NLU) ON (NLX) Toshiba (TC7S/WZ) NXP () Pericom (STX) STMicro (LX) G7 Single D-Type Latch w/- SN7G7 NC7SZ7 State G7 Single D-Type Flip-Flop SN7G7 NC7SZ7 w/-state G8 Single -Input Exclusive-OR SN7G8 NC7SZ8 7G8 G08 Single -Input Positive SN7G08 AND-OR Gate G08 Single -Input Positive OR-AND Gate SN7G08 Dual Gate G0 Dual -Input NAND SN7G00 NC7WZ00 NL7WZ00 TC7WZ00 7G00 G0 Dual -Input NOR SN7G0 NC7WZ0 NL7WZ0 TC7WZ0 7G0 G0 Dual Inverter SN7G0 NC7WZ0 NL7WZ0 NLUG0 NLXG0 7G0 GU0 Dual Inverter (Unbuffered) SN7GU0 NC7WZU0 NL7WZU0 NLUGU0 NLXGU0 7GU0 G0 Dual Inverter Buffer SN7G0 NL7WZ0 NLUG0 NLXG0 7G0 Driver w/open Drain Output G07 Dual-Buffer Driver w/open SN7G07 NC7WZ07 NL7WZ07 NLUG07 NLXG07 7G07 Drain Output G08 Dual -Input AND SN7G08 NC7WZ08 NL7WZ08 NLXG08 TC7WZ08 7G08 PI7STXG08 G Dual Inverter w/schmitt SN7G NC7WZ NL7WZ NLUG NLXG 7G Trigger G7 Dual Buffer w/schmitt SN7G7 NC7WZ7 NL7WZ7 NLUG7 NLXG7 7G7 Trigger Input G Dual -Input OR SN7G NCWZ NL7WZ TC7WZ 7G G Dual Buffer Gate SN7G NC7WZ NL7WZ 7G G8 Dual -Input NAND w/ SN7G8 NCWZ8 TC7WZ8 7G8 Open Drain Output G7 D-Type Flip-Flop w/pre SN7G7 NC7SZ7 NL7SZ7 TC7WZ7 7G7 and CLR G79 Dual D-Type Flip-Flop SN7G79 G80 Dual D-Type Flip-Flop SN7G80 G8 Dual -Input Exclusive- SN7G8 NC7WZ8 NL7WZ8 NLXG8 7G8 OR G Dual-Bus Buffer Gate SN7G NC7WZ NL7WZ 7G w/-state G Dual-Bus Buffer Gate SN7G NC7WZ NL7WZ 7G w/-state G Dual -Input NAND w/ SN7G NC7WZ Schmitt Trigger Input G7 -Input Non-Inverting SN7G7 Mux G0 Dual-Bus Buffer Gate SN7G0 NC7WZ0 7G0 w/-state G Dual-Bus Buffer Gate w/-state SN7G NC7WZ 7G Triple Gate G0 Triple Inverter SN7G0 NC7NZ0 NNL7WZ0 TC7WZ0 7G0 GU0 Triple Inverter (Unbuffered) SN7GU0 NC7NZU0 TC7WZU0 7GU0 G0 Triple Inverter Buffer/Driver SN7G0 NL7WZ0 7G0 w/open Drain Output G07 Triple Buffer/Driver w/open SN7G07 NL7WZ07 7G07 Drain Output G Triple Inverter w/schmitt SN7G NC7NZ NL7WZ NLUG NLXG TC7WZ 7G Trigger G7 Triple Buffer w/schmitt SN7G7 NC7NZ7 NL7WZ7 NLUG7 NLXG7 7G7 Trigger G Triple Buffer SN7G NC7NZ NL7WZ TC7WZ 7G PI7STXG08 8 Little Logic Guide 08 Texas Instruments

19 Cross-Reference Competitor Cross-Reference Devices Function Description TI () Single Gate (-pin, unless noted) Fairchild (NC7SV)) ON (SV) Toshiba Pericom G00 Single -Input NAND SN7G00 NL7SV00 TC7SA00 G0 Single -Input NOR SN7G0 NL7SV0 G0 Single Inverter SN7G0 NL7SV0 TC7SA0 GU0 Single Inverter (Unbuffered) SN7GU0 TC7SAU0 G0 Single Inverter Buffer/Driver w/open Drain SN7G0 G07 Single Buffer/Driver w/open Drain Output SN7G07 NL7SV08 NL7WZ00 G08 Single -Input AND SN7G08 NL7WZ0 TC7SA08 PI7STG08 G Single Inverter w/schmitt Trigger SN7G NL7WZ0 G7 Single Buffer w/schmitt Trigger SN7G7 NL7WZU0 G9 of Decoder/Demultiplexer SN7G9 NL7SV NL7WZ0 TC7PA9 G Single -Input OR SN7G NL7WZ07 TC7SA PI7STG G7 D-Type Flip-Flop w/pre and CLR SN7G7 NL7WZ08 G79 Single D-Type Flip-Flop SN7G79 NL7WZ G80 Single D-Type Flip-Flop SN7G80 NL7WZ7 G8 Single -Input Exclusive-OR SN7G8 NL7WZ PI7STG8 G Single-Bus Buffer Gate w/-state SN7G NL7WZ PI7STG G Single-Bus Buffer Gate w/-state SN7G PI7STG G0 Single-Bus Buffer Gate w/-state SN7G0 NL7SZ7 Dual Gate (8-pin, unless noted) G00 Dual -Input NAND SN7G0 G0 Dual -Input NOR SN7GU0 G0 Dual Inverter NC7WV0 TCPA0 GU0 Dual Inverter (Unbuffered) SN7G07 TCPAU0 G0 Dual Inverter Buffer/Driver w/open Drain Output SN7G G07 Dual Buffer/Driver w/open Drain Output SN7G7 NC7WV07 G08 Dual -Input AND SN7G G Dual -Input OR SN7G0 G Dual Buffer SN7GU0 NC7WV TC7PA G79 Dual D-Type Flip-Flop SN7G0 G80 Dual D-Type Flip-Flop SN7G07 G8 Dual -Input Exclusive-OR SN7G G Dual-Bus Buffer Gate w/-state SN7G7 NC7WV G Dual-Bus Buffer Gate w/-state SN7G G0 Dual-Bus Buffer Gate w/-state SN7G7 G Dual-Bus Buffer Gate w/-state SN7G Texas Instruments Little Logic Guide 08 9

20 Cross-Reference Competitor Cross-Reference Signal-Switch Devices Function Description TI Toshiba Fairchild NXP Pericom CBTG Single FET Bus Switch SN7CBTG CBTDG Single FET Bus Switch SN7CBTDG CBTG8 Single Low-Power Bus Switch SN7CBTG8 TC7SB8 NC7SZ8 7G8 CBTDG8 8 Function w/level Shifting SN7CBTDG8 TC7SBD8 NC7SZD8 CBTLVG Single LV FET Bus Switch SN7CBTLVG CBTG Single FET Bus Switch SN7CBTG G Single Analog Switch SN7G G SPDT Analog Switch SN7G TC7PA G Dual Analog Switch SN7G G Single Analog Switch SN7G NC7SZ 7G G7 SPDT Analog Switch SN7G7 NC7SB7 7G7 PISA7 G SPDT Analog Switch SN7G G Dual Analog Switch SN7G NC7WB 7G AUP Devices (-pin, unless noted) Function Description TI (AUP) NXP (AUP) Fairchild (NC7SV) Toshiba Single Gate G00 Single -Input NAND SN7AUPG00 7AUPG00 NC7SP00 TC7SG00 G0 Single -Input NOR SN7AUPG0 7AUPG0 NC7SP0 TC7SG0 G0 Single Inverter SN7AUPG0 7AUPG0 NC7SP0 TC7SG0 G0 Single Inverter Buffer/Driver w/open Drain Output SN7AUPG0 7AUPG0 G07 Single Buffer/Driver w/open Drain Output SN7AUPG07 7AUPG07 TC7SG07 G08 Single -Input AND SN7AUPG08 7AUPG08 NC7SP08 TC7SG08 G Single Inverter w/schmitt Trigger SN7AUPG 7AUPG NC7SP TC7SG G7 Single Buffer w/schmitt Trigger SN7AUPG7 7AUPG7 NC7SP7 TC7SG7 G Single -Input OR SN7AUPG 7AUPG NC7SP TC7SG G Single Buffer SN7AUPG 7AUPG NC7SP TC7SG G7 Single Positive-Edge-Trigger D-Type Flip-Flop SN7AUPG7 7AUPG7 NC7SP7 G79 Single D-Type Flip-Flop SN7AUPG79 7AUPG79 G80 Single D-Type Flip-Flop SN7AUPG80 7AUPG80 G Single-Bus Buffer Gate w/-state SN7AUPG 7AUPG NC7SP TC7SG G Single-Bus Buffer Gate w/-state SN7AUPG 7AUPG NC7SP TC7SG G7 Single -Input Non-Inverting MUX SN7AUPG7 7AUPG7 NC7SP7 G0 Single-Bus Buffer Gate w/-state SN7AUPG0 7AUPG0 Dual Gate (8-pin, unless noted) G00 Dual -Input NAND SN7AUPG00 7AUPG00 NC7WP00 G0 Dual -Input NOR SN7AUPG0 7AUPG0 NC7WP0 G0 Dual Inverter SN7AUPG0 7AUPG0 NC7WP0 G0 Dual Inverter Buffer/Driver w/open Drain Output SN7AUPG0 7AUPG0 G07 Dual Buffer/Driver w/open Drain Output SN7AUPG07 7AUPG07 NC7WP07 G08 Dual -Input AND SN7AUPG08 7AUPG08 NC7WP08 G Dual-Bus Buffer Gate w/-state SN7AUPG 7AUPG NC7WP G Dual-Bus Buffer Gate w/-state SN7AUPG 7AUPG NC7WP G Dual Inverter w/schmitt Trigger SN7AUPG 7AUPG NC7WP G7 Dual Buffer w/schmitt Trigger Input SN7AUPG7 7AUPG7 NC7WV7 G0 Dual-Bus Buffer Gate w/-state SN7AUPG0 7AUPG0 NC7WP0 G Dual-Bus Buffer Gate w/-state SN7AUPG 7AUPG 0 Little Logic Guide 08 Texas Instruments

21 Cross-Reference Competitor Cross-Reference AUP Devices (-pin, unless noted) (continued) Function Description TI (AUP) NXP (AUP) Fairchild (NC7SV) Toshiba G Dual -Input OR SN7AUPG 7AUPG NC7WP G Dual Buffer Gate SN7AUPG 7AUPG G79 Dual D-Type Flip-Flop SN7AUPG79 7AUPG79 G80 Dual D-Type Flip-Flop SN7AUPG80 7AUPG80 Triple gates G0 Triple Inverter SN7AUPG0 7AUPG0 NC7NP0 G0 Triple Inverter Buffer/Driver w/open Drain Output SN7AUPG0 7AUPG0 G07 Triple Buffer/Driver w/open Drain Output SN7AUPG07 7AUPG07 G7 Triple Buffer w/schmitt Trigger SN7AUPG7 7AUPG7 G Triple Buffer SN7AUPG 7AUPG NC7NP AHC Devices Function Description TI (AHC) Toshiba (TC7S/W) Fairchild (NC7S) ON (VHC) STMicro (VG) NXP G00 Single -Input NAND Gate SN7AHCG00 TC7SH00 NC7S00 MC7VHCG00 7VG00 7AHCG00 G0 Single -Input NOR SN7AHCG0 TC7SH0 NC7S0 MC7VHCG0 7VG0 7AHCG0 G0 Single Inverter SN7AHCG0 TC7SH0 NC7S0 MC7VHCG0 7VG0 7AHCG0 GU0 Single Inverter (Unbuffered) SN7AHCGU0 TC7SHU0 NC7SU0 MC7VHCGU0 7VGU0 7AHCGU0 G08 Single -Input AND SN7AHCG08 TC7SH08 NC7S08 MC7VHCG08 7VG08 7AHCG08 G Single Inverter w/schmitt Trigger SN7AHCG TC7SH NC7S MC7VHCG 7VG 7AHCG G Single -Input OR SN7AHCG TC7SH NC7S MC7VHCG 7VG 7AHCG G8 Single -Input Exclusive-OR SN7AHCG8 TC7SH8 NC7S8 MC7VHCG8 7VG8 7AHCG8 G Single-Bus Buffer Gate w/-state SN7AHCG TC7SH MC7VHCG 7VG 7AHCG G Single-Bus Buffer Gate w/-state SN7AHCG TC7SH MC7VHCG 7VG 7AHCG AHCT Devices Function Description TI (AHCT) Toshiba (TC7SE/WT) Fairchild (NC7ST) ON (VHCGT) STMicro (VT) NXP G00 Single -Input NAND SN7AHCTG00 TC7SET00 NC7S00 MC7VHCG00 7VG00 7AHCG00 G0 Single -Input NOR SN7AHCTG0 TC7SET0 NC7S0 MC7VHCG0 7VG0 7AHCG0 G0 Single Inverter SN7AHCTG0 TC7SET0 NC7S0 MC7VHCG0 7VG0 7AHCG0 G08 Single -Input AND SN7AHCTG08 TC7SET08 NC7SU0 MC7VHCGU0 7VGU0 7AHCGU0 G Single Inverter w/schmitt Trigger SN7AHCTG NC7S08 MC7VHCG08 7VG08 7AHCG08 G Single -Input OR SN7AHCTG TC7SET NC7S MC7VHCG 7VG 7AHCG G8 Single -Input Exclusive-OR SN7AHCTG8 TC7SET8 NC7S MC7VHCG 7VG 7AHCG G Single-Bus Buffer Gate w/-state SN7AHCTG NC7S8 MC7VHCG8 7VG8 7AHCG8 G Single-Bus Buffer Gate w/-state SN7AHTCG MC7VHCG 7VG 7AHCG Texas Instruments Little Logic Guide 08

22 Cross-Reference Competitor Cross-Reference Configurable Devices Function Description TI Fairchild NXP G7 Single Configurable ( functions) SN7G7 NC7SZ7 7G7 G8 Single Configurable ( functions) SN7G8 NC7SZ8 7G8 G97 Single Configurable (9 functions) SN7G97 7G97 G98 Single Configurable (9 functions) SN7G98 7G98 G99 Ultra-Configurable (0 functions) SN7G99 AUPG7 Single Configurable ( functions) SN7AUPG7 NC7SP7/7AUPG7 7AUPG7 AUPG8 Single Configurable ( functions) SN7AUPG8 NC7SP8/7AUPG8 7AUPG8 AUPG97 Single Configurable (9 functions) SN7AUPG97 7AUPG97 7AUPG97 AUPG98 Single Configurable (9 functions) SN7AUPG98 7AUPG98 7AUPG98 AUPG99 Ultra-Configurable (0 functions) SN7AUPG99 AUPT Translators Function Description TI ON NXP Fairchild AUPT00 Single -Input Positive-NAND Gate SN7AUPT00 MC7VHCGT00 AUPT0 Single -Input Positive-NOR Gate SN7AUPT0 MC7VHCGT00 AUPT0 Single Inverter Gate SN7AUPT0 MC7VHCGT0 AUPT08 -Input Positive-AND Gate SN7AUPT08 MC7VHCGT08 AUPT Single Schmitt-Trigger Inverter Gate SN7AUPT MC7VHCGT AUPT7 Buffer Multiplexer (Noninverted) SN7AUPT7 AUPT8 Buffer Multiplexer (Inverted) SN7AUPT8 AUPT7 Single Schmitt-Trigger Buffer Gate SN7AUPT7 MC7VHCGT8 AUPT -Input Positive-OR Gate SN7AUPT MC7VHCGT AUPT7 Configurable, Single-Supply Voltage Translator SN7AUPT7 7AUPT7 AUPT8 Configurable, Single-Supply Voltage Translator SN7AUPT8 7AUPT8 AUPT8 -Input Exclusive-OR Gate SN7AUPT8 MC7VHCGT8 AUPT87 -Input Positive Exclusive-NOR Gate SN7AUPT87 AUPT97 Configurable, Single-Supply Voltage Translator SN7AUPT97 7AUPT97 AUPT98 Configurable, Single-Supply Voltage Translator SN7AUPT98 7AUPT98 Little Logic Guide 08 Texas Instruments

23 Cross-Reference Part Number Definition Naming System SN7AUP G 08 DRY R DBV / Leads SOT- R=Tape & Reel T= Small Tape & Reel DCK DRL YZP / Leads SC-70 / Leads SOT/ //8 NanoFree Logic Gate Function YFP YZV //8 NanoFree Leads AHC AHCT AUP CMOS/CMOS TTL to V CMOS Low-Voltage CMOS Low Power Consumption G G G T T Single Gate Dual Gate Triple Gate Single Gate Translation Dual Gate Translation DRY RSE DCT DCU DSF DQE DPW / QFN / QFN 8 Leads 8 Leads US8 / Leads µqfn 8 Leads µqfn Leads µqfn Ultra-Low-Voltage.8 V CBT V Digital Switch CBTD V to. V Translation Switch CBTLV Low-Voltage Digital Switch Competitor Part Prefixes Signal-Switch Devices TI TOSHIBA FAIRCHILD ON ON (NLU) ON (NLX) STMicro NXP Pericom Little Logic SN7AHCG TC7SH NC7S MC7VHCG 7VG 7AHCG SN7AHCTG TC7SET NC7ST MC7VHCGT 7VGT 7AHCTG SN7G TC7SA/PA NC7SV NL7SV SN7G TC7PA NC7WV SN7AUPG TC7SG NC7SP 7AUPG SN7G TC7SZ NC7SZ NL7SZ NLUG NLXG 7LXG 7G PI7STXG SN7G TC7WZ NC7WZ NL7WZ NLUG NLXG 7G PI7STXG SN7G TC7WZ NC7NZ NL7WZ NLUG NLXG 7G Little Logic Signal Switches SN7G TC7PA SN7CBTG TC7SB NC7SZ SN7CBTDG TC7SBD NC7SZD SN7CBTLVG TC7SBL SN7G NC7SZ 7G SN7G NC7WB Little Logic Configurables SN7AUPG NC7SP SN7G NC7SZ Little Logic Translation SN7T NC7SP SN7T NC7SZ Texas Instruments Little Logic Guide 08

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