SN54192, SN54193, SN54LS192, SN54LS193, SN74192, SN74193, SN74LS192, SN74LS193 SYNCHRONOUS 4-BIT UP/DOWN COUNTERS (DUAL CLOCK WITH CLEAR)
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1 SN54192, SN54193, SN54LS192, SN54LS193, SN74192, SN74193, SN74LS192, SN74LS193 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 1988, Texas Instruments Incorporated POST OFFICE BOX DALLAS, TEXAS
2 SN54192, SN54LS192, SN74192, SN74LS192 2 POST OFFICE BOX DALLAS, TEXAS 75265
3 SN54193, SN54LS193, SN74193, SN74LS193 POST OFFICE BOX DALLAS, TEXAS
4 SN54192, SN54193, SN54LS192, SN54LS193, SN74192, SN74193, SN74LS192, SN74LS193 4 POST OFFICE BOX DALLAS, TEXAS 75265
5 SN54192, SN54LS192, SN74192, SN74LS192 POST OFFICE BOX DALLAS, TEXAS
6 SN54193, SN54LS193, SN74193, SN74LS193 6 POST OFFICE BOX DALLAS, TEXAS 75265
7 SN54192, SN54193, SN74192, SN74193 POST OFFICE BOX DALLAS, TEXAS
8 SN54LS192, SN54LS193, SN74LS192, SN74LS193 8 POST OFFICE BOX DALLAS, TEXAS 75265
9 SN54192, SN54193, SN54LS192, SN54LS193, SN74192, SN74193, SN74LS192, SN74LS193 POST OFFICE BOX DALLAS, TEXAS
10 SN54192, SN54193, SN54LS192, SN54LS193, SN74192, SN74193, SN74LS192, SN74LS POST OFFICE BOX DALLAS, TEXAS 75265
11 SN54192, SN54193, SN54LS192, SN54LS193, SN74192, SN74193, SN74LS192, SN74LS193 POST OFFICE BOX DALLAS, TEXAS
12 SN54192, SN54193, SN54LS192, SN54LS193, SN74192, SN74193, SN74LS192, SN74LS POST OFFICE BOX DALLAS, TEXAS 75265
13 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ( CRITICAL APPLICATIONS ). TI SEMICONDUCR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSOD BE FULLY AT THE CUSMER S RISK. In order to minimize risks associated with the customer s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI s publication of information regarding any third party s products or services does not constitute TI s approval, warranty or endorsement thereof. Copyright 1999, Texas Instruments Incorporated
14 1 of 3 Products Development Tools Applications Search PRODUCT FOLDER PRODUCT INFO: FEATURES DESCRIPTION DATASHEETS PRICING/AVAILABILITY APPLICATION NOTES RELATED DOCUMENTS PRODUCT SUPPORT: TRAINING SN54193, Synchronous 4-Bit Up/Down Counters (Dual Clock With Clear) DEVICE STATUS: ACTIVE PARAMETER NAME SN54193 Voltage Nodes (V) 5 Vcc range (V) 4.5 to 5.5 Input Level TTL Output Level TTL Output 2S Clear Async FEATURES Cascading Circuitry Provided Internally Synchronous Operation Individual Preset to Each Flip-Flop Fully Independent Clear Input DESCRIPTION These monolithic circuits are synchronous reversible (up/down) counters having a complexity of 55 equivalent gates. The '192 and 'LS192 circuits are BCD counters and the '193 and 'LS193 are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincidently with each other when so instructed by the steering logic. This mode of operation eliminates the output counting spikes which are normally associated with asynchronous (ripple-clock) counters. The outputs of the four master-slave flip-flops are triggered by a low-to-high-level transition of either count (clock) input. The direction of counting is determined by which count input is pulsed while the other count input is high. All four counters are fully programmable; that is, each output may be preset to either level by entering the desired data at the data inputs while the load input is low. The output will change to agree with the data inputs independently of the count pulses. This featue allows the counters to be used as modulo-n dividers by simply modifying the count length with the
15 2 of 3 preset inputs. A clear input has been provided which forces all outputs to the low level when a high level is applied. The clear function is independent of the count and load inputs. The clear, count, and load inputs are buffered to lower the drive requirements. This reduces the number of clock drivers, etc., required for long words. These counters were designed to be cascaded without the need for external circuitry. Both borrow and carry outputs are available to cascade both the up- and down-counting functions. The borrow output produces a pulse equal in width to the count-down input when the counter underflows. Similarly, the carry output produces a pulse equal in width to the count-up input when an overflow condition exists. The counters can then be easily cascaded by feeding the borrow and carry outputs to the count-down and count-up inputs respectively of the succeeding counter. TECHNICAL DOCUMENTS To view the following documents, Acrobat Reader 3.x is required. To download a document to your hard drive, right-click on the link and choose 'Save'. DATASHEET Full datasheet in Acrobat PDF: sdls074.pdf (438 KB) (Updated: 12/01/1983) Full datasheet in Zipped PostScript: sdls074.psz (854 KB) APPLICATION NOTES View Application Reports for Digital Logic Designing With Logic (SDYA009C - Updated: 06/01/1997) Input and Output Characteristics of Digital Integrated Circuits (SDYA010 - Updated: 10/01/1996) Live Insertion (SDYA012 - Updated: 10/01/1996) RELATED DOCUMENTS Documentation Rules (SAP) And Ordering Information (SZZU001B, 4 KB - Updated: 05/06/1999) Logic Selection Guide Second Half 2000 (SDYU001N, 5035 KB - Updated: 04/17/2000) MicroStar Junior BGA Design Summary (SCET004, 167 KB - Updated: 07/28/2000) More Power In Less Space - Technical Article (SCAU001A, 850 KB - Updated: 03/01/1996) PRICING/AVAILABILITY ORDERABLE DEVICE PACKAGE PINS JM38510/01309BEA J 16 SN54193J J 16 TEMP (ºC) STATUS BUDGETARY PRICE US$/UNIT QTY=1000+ PACK QTY DSCC NUMBER PRICING/AVAILABILITY ACTIVE Check stock or order ACTIVE Check stock or order
16 3 of 3 SNJ54193J J 16 SNJ54193W W 16 ACTIVE Check stock or order ACTIVE Check stock or order Table Data Updated on: 11/30/2000 Copyright 2000 Texas Instruments Incorporated. All rights reserved. Trademarks Privacy Policy Important Notice
17 1 of 3 Products Development Tools Applications Search PRODUCT FOLDER PRODUCT INFO: FEATURES DESCRIPTION DATASHEETS PRICING/AVAILABILITY APPLICATION NOTES RELATED DOCUMENTS PRODUCT SUPPORT: TRAINING SN54LS193, Synchronous 4-Bit Up/Down Counters (Dual Clock With Clear) DEVICE STATUS: ACTIVE PARAMETER NAME SN54LS193 Voltage Nodes (V) 5 Vcc range (V) 4.5 to 5.5 Input Level TTL Output Level TTL Output 2S Clear Async FEATURES Cascading Circuitry Provided Internally Synchronous Operation Individual Preset to Each Flip-Flop Fully Independent Clear Input DESCRIPTION These monolithic circuits are synchronous reversible (up/down) counters having a complexity of 55 equivalent gates. The '192 and 'LS192 circuits are BCD counters and the '193 and 'LS193 are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincidently with each other when so instructed by the steering logic. This mode of operation eliminates the output counting spikes which are normally associated with asynchronous (ripple-clock) counters. The outputs of the four master-slave flip-flops are triggered by a low-to-high-level transition of either count (clock) input. The direction of counting is determined by which count input is pulsed while the other count input is high. All four counters are fully programmable; that is, each output may be preset to either level by entering the desired data at the data inputs while the load input is low. The output will change to agree with the data inputs independently of the count pulses. This featue allows the counters to be used as modulo-n dividers by simply modifying the count length with the
18 2 of 3 preset inputs. A clear input has been provided which forces all outputs to the low level when a high level is applied. The clear function is independent of the count and load inputs. The clear, count, and load inputs are buffered to lower the drive requirements. This reduces the number of clock drivers, etc., required for long words. These counters were designed to be cascaded without the need for external circuitry. Both borrow and carry outputs are available to cascade both the up- and down-counting functions. The borrow output produces a pulse equal in width to the count-down input when the counter underflows. Similarly, the carry output produces a pulse equal in width to the count-up input when an overflow condition exists. The counters can then be easily cascaded by feeding the borrow and carry outputs to the count-down and count-up inputs respectively of the succeeding counter. TECHNICAL DOCUMENTS To view the following documents, Acrobat Reader 3.x is required. To download a document to your hard drive, right-click on the link and choose 'Save'. DATASHEET Full datasheet in Acrobat PDF: sdls074.pdf (438 KB) (Updated: 12/01/1983) Full datasheet in Zipped PostScript: sdls074.psz (854 KB) APPLICATION NOTES View Application Reports for Digital Logic Designing With Logic (SDYA009C - Updated: 06/01/1997) Designing with the SN54/74LS123 (SDLA006A - Updated: 03/01/1997) Input and Output Characteristics of Digital Integrated Circuits (SDYA010 - Updated: 10/01/1996) Live Insertion (SDYA012 - Updated: 10/01/1996) RELATED DOCUMENTS Documentation Rules (SAP) And Ordering Information (SZZU001B, 4 KB - Updated: 05/06/1999) Logic Selection Guide Second Half 2000 (SDYU001N, 5035 KB - Updated: 04/17/2000) MicroStar Junior BGA Design Summary (SCET004, 167 KB - Updated: 07/28/2000) More Power In Less Space - Technical Article (SCAU001A, 850 KB - Updated: 03/01/1996) PRICING/AVAILABILITY ORDERABLE DEVICE PACKAGE PINS TEMP (ºC) A FK 20 STATUS BUDGETARY PRICE US$/UNIT QTY=1000+ PACK QTY DSCC NUMBER PRICING/AVAILABILITY ACTIVE Check stock or order JM38510/31508B2A FK 20 ACTIVE Check stock or order
19 3 of 3 JM38510/31508BEA J 16 JM38510/31508BFA W 16 SN54LS193J J 16 SNJ54LS193FK FK 20 SNJ54LS193J J 16 SNJ54LS193W W 16 ACTIVE Check stock or order ACTIVE Check stock or order ACTIVE Check stock or order ACTIVE A Check stock or order ACTIVE EA Check stock or order ACTIVE FA Check stock or order Table Data Updated on: 11/30/2000 Copyright 2000 Texas Instruments Incorporated. All rights reserved. Trademarks Privacy Policy Important Notice
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