HD66766 Rev. 1.0 / 30 November 2001 HD (132 x 176-dot Graphics LCD Controller/Driver for 65K Colors)

Transcription

1 HD66766 Rev.. / 3 November 2 HD66766 (32 x 76-dot Graphics LCD Controller/Driver for 65K Colors) Rev.. November, 2 Description The HD66766, color-graphics LCD controller and driver LSI, displays 32-by-76-dot graphics for 65K STN colors. A 6-bit high-speed bus interface and high-speed RAM write function enable efficient data transfer and high-speed rewriting of data to the graphics RAM. The HD66766 has various functions for reducing the power consumption of a LCD system, such as lowvoltage operation of 2.2 V/min., a step-up circuit to generate a maximum of 2-times the LCD drive voltage from the supplied voltage, and voltage-followers to decrease the direct current flow in the LCD drive bleeder-resistors. Combining these hardware functions with software functions, such as a partial display with low-duty drive and standby and sleep modes, allows precise power control. The HD66766 is suitable for any mid-sized or small portable battery-driven product requiring long-term driving capabilities, such as digital cellular phones supporting a WWW browser, bi-directional pagers, and small PDAs. Features 32RGB x 76-dot graphics display LCD controller/driver for 65K STN colors low voltage drive and flickerless PWM grayscale drive 6-/8-bit high-speed bus interface and Clock Synchronized Serial Interface ( SPI ) High-speed burst-ram write function Writing to a window-ram address area by using a window-address function Bit-operation functions for graphics processing: - Write-data mask function in bit units. - Logical operation in pixel unit and conditional write function.

2 HD66766 Rev.. / 3 November 2 Various color-display control functions - 65K out of 4K possible colors can be displayed at the same time (grayscale palette incorporated) - Vertical scroll display function in raster-row units Low-power operation supports: - Vcc = 2.2 to 3.6 V (low-voltage) - Common driving voltage = 8 to 44 V - Segment driving voltage = 2 to 4 V - VOUT power voltage = 4.5V to 5.5 V - Maximum 2-times step-up circuit for liquid crystal drives voltage and voltage inverting circuit - 28-step contrast adjuster and voltage followers to decrease direct current flow in the LCD drive bleeder-resistors - Power-save functions such as the standby mode and sleep mode - Partial LCD drive of two screens in any position - Programmable drive duty ratios (/8 /76) and bias values (/2 /3) displayed on LCD Internal RAM capacity: 46,464 bytes 396-segment 76-common liquid crystal display driver n-raster-row AC liquid-crystal drive (C-pattern waveform drive) Internal oscillation and hardware reset Shift change of segment and common drivers COM positioned on both sides in one chip for COG Type Name Types HCD667A66BP HCD667B66BP External Dimensions Au-bumped chip straight bump Au-bumped chip laced bump 2

3 HD66766 Rev.. / 3 November 2 HD66766 PAD Arrangement (Straight Output Arrangement) - Chip Size :8.65mm x 2.63mm Chip thickness : 55µm (Typ) - PAD coordinate : PAD center - Coordinate origin : Chip center - AU bump size : () 8µm x 8µm DUMMY, DUMMY2, RESET* to RESET3, DUMMY,DUMMY,DUMMY2,DUMMY3 (2) 23um x 4m COM to COM76 SEG to SEG396 - AU bump pitch : Refer PAD coordinate - AU bump height : 5µm (Typ) Number in the diagram refers to number on the PAD coordinate - Arrangement mark () Arrangement : 2 places (X,Y) = ( +/- 9, -2 ) 9um 95 9um ( 2 - a ) coordination ( X, Y ) = ( -994, 45 ) 5um ( 2 - b ) coordination ( X, Y ) = ( 994, 45 ) ( 3 - a ) coordination ( X, Y ) = ( -94, 45 ) 8um 7um ( 3 - b ) Coordination ( X, Y ) = (94,45 ) 7um um 8um um 5um NO. COM COM3 COM5 COM7 COM99 COM COM3 COM5 NO.666 DUMMY DUMMY3 DUMMY2 COM7 RESET* COM9 CEP COM CEP COM3 CEM CEM VCL VCL VCL VCL VCH VCH VCH VCH C24+ C24+ C24- COM69 C24- COM7 C23+ COM73 C23+ COM75 C23- SEG C23- SEG2 C22+ SEG3 C22+ SEG4 C22- C22- C2+ C2+ C2- C2- VCI2 VCI2 VCI2 VCI2 GNDDUM GNDDUM4 DB5 DB4 DB3 DB2 DB DB DB9 DB8 GNDDUM5 DB7 DB6 DB5 DB4 HD66766 DB3 DB2 Straight Output Arrangement DB/SDO DB/SDI (TOP View) GNDDUM6 RW/RD* E/WR*/SCL GNDDUM7 Y RS CS* VCC VCC VCC X VCC VCC VCC VCC VCC AGND AGND GND GND GND GND AGND AGND RESET2* OSC2 OSC GNDDUM8 IM2 VCCDUM IM GNDDUM9 IM/ID VCCDUM2 TEST2 TEST GNDDUM DUMMY3 DUMMY9 VREFL VREFL BIASC BIASC VREFM VREFM VM VM VM VM VSH VSH VSH VSH VOUT VOUT VOUT VOUT C2+ C2+ C2+ C2+ C2- SEG393 C2- SEG394 C2- SEG395 C2- SEG396 C+ COM76 C+ COM74 C+ COM72 C+ COM7 C- C- C- C- VCIOUT VCIOUT VCIOUT VCIOUT VCI VCI VCI VCI VCCDUM3 COM4 VCCDUM4 COM2 RESET3* COM DUMMY COM8 DUMMY DUMMY2 NO.45 COM2 COM4 COM6 COM8 COM COM2 COM4 COM6 NO.99 3

4 HD66766 Rev.. / 3 November 2 HCD667A66BP Pad Coordinate No pad name X Y No. pad name X Y No. pad name X Y No. pad name X Y No. pad name X Y DUMMY OSC COM SEG SEG DUMMY GNDDUM COM SEG SEG RESET* IM COM SEG SEG CEP VCCDUM COM SEG SEG CEP IM COM SEG SEG CEM GNDDUM COM SEG SEG CEM IM/ID COM SEG SEG VCL VCCDUM COM SEG SEG VCL TEST COM SEG SEG VCL TEST COM SEG SEG VCL GNDDUM COM SEG SEG VCH DUMMY COM SEG SEG VCH DUMMY COM SEG SEG VCH DUMMY COM SEG SEG VCH DUMMY COM SEG SEG C DUMMY COM SEG SEG C DUMMY COM SEG SEG C DUMMY COM SEG SEG C VREFL COM SEG SEG C VREFL COM SEG SEG C BIASC COM SEG SEG C BIASC COM SEG SEG C VREFM COM SEG SEG C VREFM COM SEG SEG C VM COM SEG SEG C VM COM SEG SEG C VM COM SEG SEG C VM COM SEG SEG C VSH COM SEG SEG C VSH COM SEG SEG C VSH COM SEG SEG VCI VSH COM SEG SEG VCI VOUT COM SEG SEG VCI VOUT COM SEG SEG VCI VOUT COM SEG SEG GNDDUM VOUT COM SEG SEG GNDDUM C COM SEG SEG GNDDUM C COM SEG SEG GNDDUM C DUMMY SEG SEG DB C COM SEG SEG DB C COM SEG SEG DB C COM SEG SEG DB C COM SEG SEG DB C COM SEG SEG DB C COM SEG SEG DB C COM SEG SEG DB C COM SEG SEG GNDDUM C COM SEG SEG DB C COM SEG SEG DB C COM SEG SEG DB C COM SEG SEG DB C COM SEG SEG DB VCIOUT COM SEG SEG DB VCIOUT COM SEG SEG DB/SDO VCIOUT COM SEG SEG DB/SDI VCIOUT COM SEG SEG GNDDUM VCI COM SEG SEG RW/RD* VCI COM SEG SEG E/WR*/SCL VCI COM SEG SEG GNDDUM VCI COM SEG SEG RS VCCDUM COM SEG SEG CS* VCCDUM COM SEG SEG VCC RESET3* COM SEG SEG VCC DUMMY COM SEG SEG VCC DUMMY COM SEG SEG VCC COM COM SEG SEG VCC COM COM SEG SEG VCC COM COM SEG SEG VCC COM COM SEG SEG VCC COM COM SEG SEG AGND COM COM SEG SEG AGND COM COM SEG SEG GND COM COM SEG SEG GND COM COM SEG SEG GND COM SEG SEG SEG GND COM SEG SEG SEG AGND COM SEG SEG SEG AGND COM SEG SEG SEG RESET2* COM SEG SEG SEG OSC COM SEG SEG SEG

5 HD66766 Rev.. / 3 November 2 No. pad name X Y No. pad name X Y No. pad name X Y No. pad name X Y alignment mark type X Y 4 SEG SEG SEG COM Cross Tipe 42 SEG SEG SEG COM SEG SEG SEG COM Circle (Positive) SEG SEG SEG COM Circle (Negative) SEG SEG SEG COM "L" type (Positive) SEG SEG SEG COM "L"type (Negative) SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG DUMMY SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG COM COM SEG SEG COM COM SEG SEG COM COM SEG SEG COM COM SEG SEG COM COM SEG SEG COM COM SEG SEG COM COM SEG SEG COM COM SEG SEG COM COM SEG SEG COM

6 HD66766 Rev.. / 3 November 2 HD66766 PAD Arrangement (Laced Output Arrangement) - Chip Size :8.65mm x 2.63mm Chip thickness : 55µm (Typ) - PAD coordinate : PAD center - Coordinate origin : Chip center - AU bump size : () 8µm x 8µm DUMMY, DUMMY2, RESET* to RESET3, DUMMY,DUMMY,DUMMY2,DUMMY3 (2) 38um x 68um COM to COM76 SEG to SEG396 - AU bump pitch : Refer PAD coordinate - AU bump height : 5µm (Typ) Number in the diagram refers to number on the PAD coordinate - Arrangement mark () Arrangement : 2 places (X,Y) = ( +/- 9, -2 ) 9um 95 9um ( 2 - a ) coordination ( X, Y ) = ( -994, 45 ) 5um ( 2 - b ) coordination ( X, Y ) = ( 994, 45 ) 2 5um NO. COM COM3 COM5 COM7 COM99 COM COM3 COM5 NO.666 ( 3 - a ) coordination ( X, Y ) = ( -94, 45 ) 8um 7um ( 3 - b ) Coordination ( X, Y ) = (94,45 ) 7um um 8um DUMMY DUMMY3 DUMMY2 COM7 RESET* COM9 CEP COM CEP COM3 CEM CEM VCL VCL VCL VCL VCH VCH VCH VCH C24+ C24+ C24- COM69 C24- COM7 C23+ COM73 C23+ COM75 C23- SEG C23- SEG2 C22+ SEG3 C22+ SEG4 C22- C22- C2+ C2+ C2- C2- VCI2 VCI2 VCI2 VCI2 GNDDUM GNDDUM4 DB5 DB4 DB3 DB2 DB HD66766 DB DB9 Laced Output DB8 GNDDUM5 Arrangement DB7 DB6 (Top View) DB5 DB4 DB3 DB2 Y DB/SDO DB/SDI GNDDUM6 RW/RD* E/WR*/SCL X GNDDUM7 RS CS* VCC VCC VCC VCC VCC VCC VCC VCC AGND AGND GND GND GND GND AGND AGND RESET2* OSC2 OSC GNDDUM8 IM2 VCCDUM IM GNDDUM9 IM/ID VCCDUM2 TEST2 TEST GNDDUM DUMMY3 DUMMY9 VREFL VREFL BIASC BIASC VREFM VREFM VM VM VM VM VSH VSH VSH VSH VOUT VOUT VOUT VOUT C2+ C2+ C2+ C2+ C2- SEG393 C2- SEG394 C2- SEG395 C2- SEG396 C+ COM76 C+ COM74 C+ COM72 C+ COM7 C- C- C- C- VCIOUT VCIOUT VCIOUT VCIOUT VCI VCI VCI VCI VCCDUM3 COM4 VCCDUM4 COM2 RESET3* COM DUMMY COM8 DUMMY DUMMY2 7um NO.45 COM2 COM4 COM6 COM8 COM COM2 COM4 COM6 NO.99 6

7 HD66766 Rev.. / 3 November 2 HD66766PAD coordinate ( Laced output pin ) No. pad name X Y No. pad name X Y No. pad name X Y No. pad name X Y No. pad name X Y DUMMY OSC COM SEG SEG DUMMY GNDDUM COM SEG SEG RESET* IM COM SEG SEG CEP VCCDUM COM SEG SEG CEP IM COM SEG SEG CEM GNDDUM COM SEG SEG CEM IM/ID COM SEG SEG VCL VCCDUM COM SEG SEG VCL TEST COM SEG SEG VCL TEST COM SEG SEG VCL GNDDUM COM SEG SEG VCH DUMMY COM SEG SEG VCH DUMMY COM SEG SEG VCH DUMMY COM SEG SEG VCH DUMMY COM SEG SEG C DUMMY COM SEG SEG C DUMMY COM SEG SEG C DUMMY COM SEG SEG C VREFL COM SEG SEG C VREFL COM SEG SEG C BIASC COM SEG SEG C BIASC COM SEG SEG C VREFM COM SEG SEG C VREFM COM SEG SEG C VM COM SEG SEG C VM COM SEG SEG C VM COM SEG SEG C VM COM SEG SEG C VSH COM SEG SEG C VSH COM SEG SEG C VSH COM SEG SEG VCI VSH COM SEG SEG VCI VOUT COM SEG SEG VCI VOUT COM SEG SEG VCI VOUT COM SEG SEG GNDDUM VOUT COM SEG SEG GNDDUM C COM SEG SEG GNDDUM C COM SEG SEG GNDDUM C DUMMY SEG SEG DB C COM SEG SEG DB C COM SEG SEG DB C COM SEG SEG DB C COM SEG SEG DB C COM SEG SEG DB C COM SEG SEG DB C COM SEG SEG DB C COM SEG SEG GNDDUM C COM SEG SEG DB C COM SEG SEG DB C COM SEG SEG DB C COM SEG SEG DB C COM SEG SEG DB VCIOUT COM SEG SEG DB VCIOUT COM SEG SEG DB/SDO VCIOUT COM SEG SEG DB/SDI VCIOUT COM SEG SEG GNDDUM VCI COM SEG SEG RW/RD* VCI COM SEG SEG E/WR*/SCL VCI COM SEG SEG GNDDUM VCI COM SEG SEG RS VCCDUM COM SEG SEG CS* VCCDUM COM SEG SEG VCC RESET3* COM SEG SEG VCC DUMMY COM SEG SEG VCC DUMMY COM SEG SEG VCC COM COM SEG SEG VCC COM COM SEG SEG VCC COM COM SEG SEG VCC COM COM SEG SEG VCC COM COM SEG SEG AGND COM COM SEG SEG AGND COM COM SEG SEG GND COM COM SEG SEG GND COM COM SEG SEG GND COM SEG SEG SEG GND COM SEG SEG SEG AGND COM SEG SEG SEG AGND COM SEG SEG SEG RESET2* COM SEG SEG SEG OSC COM SEG SEG SEG

8 HD66766 Rev.. / 3 November 2 No. pad name X Y No. pad name X Y No. pad name X Y No. pad name X Y alignment mark type X Y 4 SEG SEG SEG COM Cross Type 42 SEG SEG SEG COM SEG SEG SEG COM Circle (Positive SEG SEG SEG COM Circle (Negative) SEG SEG SEG COM "L" type (Positive) SEG SEG SEG COM "L"type (Negative) SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG DUMMY SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG SEG COM SEG SEG COM COM SEG SEG COM COM SEG SEG COM COM SEG SEG COM COM SEG SEG COM COM SEG SEG COM COM SEG SEG COM COM SEG SEG COM COM SEG SEG COM COM SEG SEG COM

9 HD66766 Rev.. / 3 November 2 HD66766 Block Diagram Description Vcc Index Register (IR) Control Register (CR) IM2-, IM/ID 7 6 Address Counter ( AC ) Palette Register (RK, GK, BK) CS* RS E/WR*/SCL RW/RD * DB/SDI, DB/SDO, to DB5 RESET * TEST TEST2 6 System Interface - 6 bit - 8 bit - Clock synchoronized serial Read data latch 6 Bit Operation 2 Write data 64 latch Graphic RAM (GRAM) 46,464 bytes 48 6 PWM Grayscale Circuit Latch Circuit Grayscale selector circuit Latch Circuit GND VSL Segment drivers SEG to SEG396 OSC OSC2 CPG Timinig generator LCD drive power supply circuit generator circuit Scan data Common driver COM to COM76 VCL VM VCH VSH VREF M VREF L CE - CE + C2- to C24- C2+ to C2 4+ Vci2 BIAS C VOUT C- to C2- C+ to C2+ Vci VciOUT Figure : HD66766 Block Diagram Description 9

10 HD66766 Rev.. / 3 November 2 Pin Functions Table Pin Functional Description Signals IM2-, IM/ID Number of Pins I/O Connected to Functions 3 I GND or V CC Selects the MPU interface mode: IM2 IM IM/ID MPU Interface mode GND GND GND 68 system 6-bit bus interface GND GND Vcc 68 system 8-bit bus interface GND Vcc GND 8 system 6-bit bus interface GND Vcc Vcc 8 system 8-bit bus interface Vcc GND ID Clock synchronized serial interface When a serial interface is selected, the IM pin is used as the ID setting for a device code. CS* I MPU Selects the HD66766: Low: HD66766 is selected and can be accessed High: HD66766 is not selected and cannot be accessed Must be fixed at GND level when not in use. RS I MPU Selects the register. Low: Index/status High: Control For a register or a synchronous clock interface, fixed to the Vcc or GND level. E/WR*/SCL I MPU For a 68-system bus interface, serves as an enable signal to activate data read/write operation. For an 8-system bus interface, serves as a write strobe signal and writes data at the low level. For a synchronous clock interface, serves as the synchronous clock signal. RW/RD* I MPU For a 68-system bus interface, serves as a signal to select data read/write operation. Low: Write High: Read For an 8-system bus interface, serves as a read strobe signal and reads data at the low level. For a synchronous clock interface, fixed to the Vcc or GND level. DB/SDI I/O MPU Serves as a 6-bit bi-directional data bus. For an 8-bit bus interface, data transfer uses DB5-DB8; fix unused DB7-DB to the Vcc or GND level. For a clock-synchronous serial interface, serves as the serial data input pin (SDI). The input level is read on the rising edge of the SCL signal. DB/SDO I/O MPU Serves as a 6-bit bi-directional data bus. For an 8-bit bus interface, data transfer uses DB5-DB8; fix unused DB7-DB to the Vcc or GND level. For a clock-synchronous serial interface, serves as a serial data output pin (SDO). Successive bit values are output on the falling edge of the SCL signal.

11 HD66766 Rev.. / 3 November 2 DB2-DB5 4 I/O MPU Serves as a 6-bit bi-directional data bus. For an 8-bit bus interface, data transfer uses DB5-DB8; fix unused DB7-DB to the Vcc or GND level. For a synchronous clock interface or unused pins, fixed to the Vcc or GND level. SEG SEG396 COM COM O LCD Output signals for segment drive. In the display-off period (D =, ) or standby mode (STB = ), all pins output GND level. The SGS bit can change the shift direction of the segment signal. For example, if SGS =, RAM address is output from SEG. If SGS =, it is output from SEG396. SEG, SEG4, SEG7,... display red (R), SEG2, SEG5, SEG8,... display green (G), and SEG3, SEG6, SEG9,... display blue (B) (SGS = ). 76 O LCD Output signals for common drive. In the display-off period (D =, ) sleep mode (SLP = ) or standby mode (STB = ), all pins output GND level. The CMS bit can change the shift direction of the common signal. For example, if CMS =, driver outputs from COM to COM76. If CMS =, driver outputs COM76 to COM. Note that start position of the common driver output is changed by screen diving position function. VCH, VCL 2 Capacitor for stabilization, shot key barrier diode or external power supply VM Capacitor for stabilization or external power supply VSH Capacitor for stabilization or external power supply VciOUT Vci and capacitor for stabilization or open Selection level for the common signal. When internal power supply is used, connect the capacitors for stabilization to VCH AND VCL, and shot key barrier diode to VCL. When internal power supply is not used, supply external voltage. Non-selection level for the common signal. When internal operational amplifier is used, it is output of the internal operational amplifier and connect the capacitors for stabilization. When internal operational amplifier is not used, supply external voltage. Selection level for the segment signal. When internal operational amplifier is used, it is output of the internal operational amplifier and connect the capacitors for stabilization. When internal operational amplifier is not used, supply external voltage. Outputs a regulated voltage derived from Vcc. Connect a capacitor for stabilization. When this pin is not used, leave it open. Vci VciOUT or power supply Vci2 Capacitor for stabilization or open VOUT Step-up capacitance C+, C- 2 Step-up capacitance Voltage-input pin for step-up circuit. When the Vci adjuster is used, input the power supply from VciOUT. When not used, input the external power supply. Connect capacitor for stabilization. When the internal power supply circuit is not used, leave this pin open. A voltage that doubles or triples the voltage between Vci and GND is output here. The step-up factor can be set in an internal register. When step-up circuit is used, connect a step-up capacitor.

12 HD66766 Rev.. / 3 November 2 C2+, C2-2 Step-up capacitance C2+, C2-2 Step-up capacitance C22+, C22-2 Step-up capacitance C23+, C23-2 Step-up capacitance C24+, C24-2 Step-up capacitance CEP, CEM 2 Step-up capacitance or open VREFL VCC or external power supply VREFM Capacitor for stabilization or external power supply BIASC Capacitor for stabilization or open When step-up circuit is used, connect a step-up capacitor. When step-up circuit is used, connect a step-up capacitor. When step-up circuit is used, connect a step-up capacitor. When step-up circuit is used, connect a step-up capacitor. When step-up circuit is used, connect a step-up capacitor. Connect a step-up capacitor to generate VCL level by VCH and VM. When step-up circuit is not used, leave this pin open. Inputs reference voltage for LCD drives power supply. Input lower level than Vcc. Since input current does not run, level input, which is divided by resistors, is also possible. Connect capacitor for stabilization for internal power supply. When internal operational amplifier is not used, supply external voltage. Connect capacitor for stabilization for internal power supply. VCC, GND 2 Power supply VCC: +.7 V to V; GND (logic): V AGND GND for power supply circuit. OSC, OSC2 2 I/O Oscillation-resistor Connect an external resistor for R-C oscillation. When providing clocks from outside, input clock to OCS and leave OSC2 open. RESET* I MPU or external Reset pin. Initializes the LSI when low. Must be reset R-C circuit after power-on. Since HCD66766BP has three RESET Open unused pins pins, use one pin and open unused two pins. VccDUM O Input pins Outputs the internal VCC level; shorting this pin sets the adjacent input pin to the VCC level. GNDDUM O Input pins Outputs the internal GND level; shorting this pin sets the adjacent input pin to the GND level. Dummy Dummy pad. Must be left disconnected. TEST, TEST 2 2 I GND Test pin. Must be fixed at GND level. 2

13 HD66766 Rev.. / 3 November 2 Block Function Description System Interface The HD66766 has five high-speed system interfaces: an 8-system 6-bit/8-bit bus, a 68-system 6-bit/8- bit bus, and a Clock synchronized serial interface. The IM2- pins select the interface mode. The HD66766 has three 6-bit registers: an index register (IR), a write data register (WDR), and a read data register (RDR). The IR stores index information from the control registers and the GRAM. The WDR temporarily stores data to be written into control registers and the GRAM, and the RDR temporarily stores data read from the GRAM. Data written into the GRAM from the MPU is first written into the WDR and then is automatically written into the GRAM by internal operation. Data is read through the RDR when reading from the GRAM, and the first read data is invalid and the second and the following data are normal. Execution time for instruction excluding oscillation start is -clock cycle and instructions can be written in succession. Table 2 Register Selection (8/6 Parallel Interface) 8-series Bus 68-series Bus WR RD R/W RS Operations Writes indexes into IR Reads internal status Writes into control registers and GRAM through WDR Reads from GRAM through RDR Table 3 Register Selection (Clock synchronized Serial Interface) Start bytes R/W Bit RS Bit Operations Writes indexes into IR Reads internal status Writes into control registers and GRAM through WDR Reads from GRAM through RDR Bit Operation The HD66766 supports the following functions. A write data mask function that selects data into the GRAM in bit units, and a logic operation function that performs logic operations or conditional determination on the display data set in the GRAM and writes into the GRAM. With the 6-bit bus interface, these functions can greatly reduce the processing lord of the MPU graphics software the display data in the GRAM at high speed. For details, see the Graphics Operation Function section. Address Counter (AC) The address counter (AC) assigns address to the GRAM. When an address set instruction is written into the IR, the address information is sent from the IR to the AC. After writing into the GRAM, the AC is automatically incremented by (or decrement by ). After reading from the GRAM, the AC is not updated. 3

14 HD66766 Rev.. / 3 November 2 Graphics RAM (GRAM) The graphics RAM (GRAM) has twelve bits/pixel and stores the bit-pattern data of 32 x 76 bytes. PWM Grayscale Palette Circuit The grayscale palette generates a PWM signal, which corresponds to specified grayscale level. Any 65K out of the 4K possible colors can be displayed at the same time. Grayscale Control Circuit The grayscale control circuit performs 6-grayscale control with the pulse width modulation (PWM) method for grayscale display for each color. Timing Generator The timing generator generates timing signals for the operation of internal circuits such as the GRAM. The RAM read timing for display and internal operation timing by MPU access is generated separately to avoid interference with one another. Oscillation Circuit (OSC) The HD66766 can provide R-C oscillation simply through the addition of an external oscillation-resistor between the OSC and OSC2 pins. The appropriate oscillation frequency for operating voltage, display size, and frame frequency can be obtained by adjusting the external-resistor value. Clock pulses can also be supplied externally. Since R-C oscillation stops during the standby mode, current consumption can be reduced. Liquid Crystal Display Driver Circuit The liquid crystal display driver circuit consists of 76 common signal drivers (COM to COM76) and 396 segment signal drivers (SEG to SEG396). Display pattern data from GRAM is latched to the 396-bit latch circuit. The latched data then enables the segment signal drivers to generate drive waveform outputs. The common driver outputs one of the VCH, VM or VCL voltage level. The SGS bit can change the shift direction of 396-bit data for the segment. The CMS bit can also change the shift direction for the common by selecting an appropriate direction for the device-mounting configuration. When display is off, or during the standby or sleep mode, all the above common and segment signal drivers output the GND level, halting the display. LCD drive power supply circuit LCD drive power supply circuit generates VCH, VSH, VM and VCL voltage level to drive LCD panel. 4

15 HD66766 Rev.. / 3 November 2 GRAM ADDRESS DIAGRAM (HD66766) Table 4 Relationship between GRAM address and display position (SGS = ) SEG/COM pins S S2 S3 S4 S5 S6 S7 S8 S9 S S S2 S385 S386 S387 S388 S389 S39 S39 S392 S393 S394 S395 S396 CMS= COM COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM COM COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM2 CMS= COM76 COM75 COM74 COM73 COM72 COM7 COM7 COM69 COM68 COM67 COM66 COM65 COM64 COM63 COM62 COM6 COM6 COM59 COM58 COM57 DB 5 DB ""H ""H "2"H "3"H "4"H "5"H "6"H "7"H "8"H "9"H "A"H "B"H "C"H "D"H "E"H "F"H ""H ""H "2"H "3"H DB 5 DB ""H ""H "2"H "3"H "4"H "5"H "6"H "7"H "8"H "9"H "A"H "B"H "C"H "D"H "E"H "F"H ""H ""H "2"H "3"H DB 5 DB "2"H "2"H "22"H "32"H "42"H "52"H "62"H "72"H "82"H "92"H "A2"H "B2"H "C2"H "D2"H "E2"H "F2"H "2"H "2"H "22"H "32"H DB 5 DB "3"H "3"H "23"H "33"H "43"H "53"H "63"H "73"H "83"H "93"H "A3"H "B3"H "C3"H "D3"H "E3"H "F3"H "3"H "3"H "23"H "33"H DB 5 "8"H "8"H "28"H "38"H "48"H "58"H "68"H "78"H "88"H "98"H "A8"H "B8"H "C8"H "D8"H "E8"H "F8"H "8"H "8"H "28"H "38"H DB DB 5 "8"H "8"H "28"H "38"H "48"H "58"H "68"H "78"H "88"H "98"H "A8"H "B8"H "C8"H "D8"H "E8"H "F8"H "8"H "8"H "28"H "38"H DB DB 5 DB "82"H "82"H "282"H "382"H "482"H "582"H "682"H "782"H "882"H "982"H "A82"H "B82"H "C82"H "D82"H "E82"H "F82"H "82"H "82"H "282"H "382"H DB 5 DB "83"H "83"H "283"H "383"H "483"H "583"H "683"H "783"H "883"H "983"H "A83"H "B83"H "C83"H "D83"H "E83"H "F83"H "83"H "83"H "283"H "383"H COM69 COM7 COM7 COM72 COM73 COM74 COM75 COM76 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM "A8"H "A9"H "AA"H "AB"H "AC"H "AD"H "AE"H "AF"H "A8"H "A9"H "AA"H "AB"H "AC"H "AD"H "AE"H "AF"H "A82"H "A83"H "A92"H "A93"H "AA2"H "AA3"H "AB2"H "AB3"H "AC2"H "AC3"H "AD2"H "AD3"H "AE2"H "AE3"H "AF2"H "AF3"H "A88"H "A98"H "AA8"H "AB8"H "AC8"H "AD8"H "AE8"H "AF8"H "A88"H "A98"H "AA8"H "AB8"H "AC8"H "AD8"H "AE8"H "AF8"H "A882"H "A883"H "A982"H "A983"H "AA82"H "AA83"H "AB82"H "AB83"H "AC82"H "AC83"H "AD82"H "AD83"H "AE82"H "AE83"H "AF82"H "AF83"H Table 5 Relationship between GRAM data and output pin GRAM DATA DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB Selected palette palette palette + FRC palette Output pin SEG (3n+) SEG (3n+2) SEG (3n+3) Note: n = Lower 8 bits address ( to 3) DB 5

16 HD66766 Rev.. / 3 November 2 Table 6 Relationship between GRAM address and display position (SGS = ) SEG/COM pins S S2 S3 S4 S5 S6 S7 S8 S9 S CMS= COM COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM COM COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 CMS= COM76 COM75 COM74 COM73 COM72 COM7 COM7 COM69 COM68 COM67 COM66 COM65 COM64 COM63 COM62 COM6 COM6 COM59 COM58 "83"H "83"H "283"H "383"H "483"H "583"H "683"H "783"H "883"H "983"H "A83"H "B83"H "C83"H "D83"H "E83"H "F83"H "83"H "83"H "283"H "82"H "82"H "282"H "382"H "482"H "582"H "682"H "782"H "882"H "982"H "A82"H "B82"H "C82"H "D82"H "E82"H "F82"H "82"H "82"H "282"H COM2 COM57 "383"H "382"H S S2 DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB "8"H "8"H "8"H "8"H "28"H "28"H "38"H "38"H "48"H "48"H "58"H "58"H "68"H "68"H "78"H "78"H "88"H "88"H "98"H "98"H "A8"H "A8"H "B8"H "B8"H "C8"H "C8"H "D8"H "D8"H "E8"H "E8"H "F8"H "F8"H "8"H "8"H "8"H "8"H "28"H "28"H "38"H "38"H S385 S386 S387 S388 S389 S39 S39 S392 S393 S394 S395 S396 "3"H "2"H "3"H "2"H "23"H "22"H "33"H "32"H "43"H "42"H "53"H "52"H "63"H "62"H "73"H "72"H "83"H "82"H "93"H "92"H "A3"H "A2"H "B3"H "B2"H "C3"H "C2"H "D3"H "D2"H "E3"H "E2"H "F3"H "F2"H "3"H "2"H "3"H "2"H "23"H "22"H "33"H "32"H ""H ""H ""H ""H "2"H "2"H "3"H "3"H "4"H "4"H "5"H "5"H "6"H "6"H "7"H "7"H "8"H "8"H "9"H "9"H "A"H "A"H "B"H "B"H "C"H "C"H "D"H "D"H "E"H "E"H "F"H "F"H ""H ""H ""H "2"H "3"H ""H "2"H "3"H COM69 COM7 COM7 COM72 COM73 COM74 COM75 COM76 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM "A883"H "A983"H "AA83"H "AB83"H "AC83"H "AD83"H "AE83"H "AF83"H "A882"H "A982"H "AA82"H "AB82"H "AC82"H "AD82"H "AE82"H "AF82"H "A88"H "A88"H "A98"H "A98"H "AA8"H "AA8"H "AB8"H "AB8"H "AC8"H "AC8"H "AD8"H "AD8"H "AE8"H "AE8"H "AF8"H "AF8"H "A83"H "A93"H "AA3"H "AB3"H "AC3"H "AD3"H "AE3"H "AF3"H "A82"H "A92"H "AA2"H "AB2"H "AC2"H "AD2"H "AE2"H "AF2"H "A8"H "A9"H "AA"H "AB"H "AC"H "AD"H "AE"H "AF"H "A8"H "A9"H "AA"H "AB"H "AC"H "AD"H "AE"H "AF"H Table 7 Relationship between GRAM data and output pin GRAM DATA DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB Selected palette palette palette + FRC palette Output pin SEG (396-3n) SEG (395-3n) SEG (394-3n) Note: n = Lower 8 bits address ( to 3) DB 6

17 HD66766 Rev.. / 3 November 2 Instructions Outline The HD66766 uses the 6-bit bus architecture. Before the internal operation of the HD66766 starts, control information is temporarily stored in the registers described below to allow high-speed interfacing with a high-performance microcomputer. The internal operation of the HD66766 is determined by signals sent from the microcomputer. These signals, which include the register selection signal (RS), the read/write signal (R/W), and the data bus signals (DB5 to DB), make up the HD66766 instructions. There are eight categories of instructions that: Specify the index Read the status Control the display Control power management Process the graphics data Set internal GRAM addresses Transfer data to and from the internal GRAM Set grayscale level for the internal grayscale palette table Normally, instructions that write data are used the most. However, an auto-update of internal GRAM addresses after each data write can lighten the microcomputer program load. Because instructions are executed in cycles, they can be written in succession. 7

18 HD66766 Rev.. / 3 November 2 Instruction Descriptions Index: IR The index instruction specifies the RAM control indexes (Rh to R3Fh). It sets the register number in the range of to in binary form. However, R4 to R44 are disabled since they are test registers. R/W RS DB5 DB4 DB3 DB2 DB DB DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB W * * * * * * * * * ID6 ID5 ID4 ID3 ID2 ID ID Figure 2 Index Instruction Status Read: SR The status read instruction reads the internal status of the HD L7 : Indicate the driving raster-row position where the liquid crystal display is being driven. C6 : Read the contrast setting values (CT6-) R/W RS DB5 DB4 DB3 DB2 DB DB DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB R L7 L6 L5 L4 L3 L2 L L C6 C5 C4 C3 C2 C C Figure 3 Status Read Instruction Start Oscillation (Rh) The start oscillation instruction restarts the oscillator from the halt state in the standby mode. After issuing this instruction, wait at least ms for oscillation to stabilize before issuing the next instruction. (See the Standby Mode section.) If this register is read forcibly, 766 H is read. R/W RS DB5 DB4 DB3 DB2 DB DB DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB w * * * * * * * * * * * * * * * R Figure 4 Start Oscillation Instruction 8

19 HD66766 Rev.. / 3 November 2 Driver Output Control (Rh) R/W RS DB5 DB4 DB3 DB2 DB DB DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB w CMS SGS NL4 NL3 NL2 NL NL Figure 5 Driver Output Control Instruction CMS: Selects the output shift direction of a common driver. When CMS =, COM shifts to COM76. When CMS =, COM76 shifts to COM. SGS: Selects the output shift direction of the segment driver. When SGS =, data are output SEG to SEG396. When SGS =, data are output SEG396 to SEG. When SGS =, SEG pin assigns the color display to <R><G><B>. When SGS =, SEG396 pin assigns <R><G><B>. Re-write to the RAM when intending to change the SGS bit. NL4-: Specify the LCD drive duty ratio. The duty ratio can be adjusted for every eight raster-rows. GRAM address mapping does not depend on the setting value of the drive duty ratio. 9