GS1531 HD-LINX II Multi-Rate Serializer with ClockCleaner

Transcription

1 GS1531 HD-LINX II Multi-Rate Serializer with ClockCleaner GS1531 Data Sheet Key Features SMPTE 292M and SMPTE 259M-C compliant scrambling and NRZ NRZI encoding (with bypass) DVB-ASI sync word insertion and 8b/10b encoding Rejection of more than 300ps jitter on the input PCLK User selectable additional processing features including: CRC, ANC data checksum, and line number calculation and insertion TRS and EDH packet generation and insertion illegal code remapping Internal flywheel for noise immune TRS generation 20-bit / 10-bit CMOS parallel input data bus 148.5MHz / 74.25MHz / 27MHz / 13.5MHz parallel digital input Automatic standards detection and indication 1.8V core power supply and 3.3V charge pump power supply 3.3V digital I/O supply JTAG test interface Available in a Pb-free package small footprint (11mm x 11mm) Applications SMPTE 292M Serial Digital Interfaces SMPTE 259M-C Serial Digital Interfaces DVB-ASI Serial Digital Interfaces Description The GS1531 is a multi-standard serializer with an integrated cable driver. When used in conjunction with the GO1555/GO1525* Voltage Controlled Oscillator, a transmit solution can be realized for HD-SDI, SD-SDI and DVB-ASI applications. The device features an internal PLL, which can be configured for loop bandwidth as narrow as 100kHz. Thus the GS1531 can tolerate in excess of 300ps jitter on the input PCLK and still provide output jitter well within SMPTE specification. Connect the output clocks from Gennum s GS4911 clock generator directly to the GS1531 s PCLK input and configure the GS1531 s loop bandwidth accordingly. In addition to serializing the input, the GS1531 performs NRZ-to-NRZI encoding and scrambling as per SMPTE 292M/259M-C when operating in SMPTE mode. When operating in DVB-ASI mode, the device will insert K28.5 sync characters and 8b/10b encode the data prior to serialization. Parallel data inputs are provided for 10-bit multiplexed or 20-bit demultiplexed formats at both HD and SD signal rates. An appropriate parallel clock input signal is also required. The integrated cable driver features an output mute on loss of parallel clock, high impedance mode, adjustable signal swing, and automatic dual slew rate selection depending on HD/SD operational requirements. The GS1531 also includes a range of data processing functions including automatic standards detection and EDH support. The device can also insert TRS signals, calculate and insert line numbers and CRC s, re-map illegal code words and insert SMPTE 352M payload identifier packets. All processing features are optional and may be enabled/disabled via external control pin(s) and/or host interface programming. *For new designs use GO February of 50

2 VCO_GND VCO_VCC LF LB_CONT VCO VCO CP_CAP LOCKED PCLK F V H DETECT_TRS DVB_ASI IOPROC_EN/DIS SMPTE_BYPASS BLANK SD/HD 20bit/10bit RESET_TRST SDOUT_TDO SDIN_TDI SCLK_TCK CS_TMS JTAG/HOST GS1531 Data Sheet Functional Block Diagram Phase detector, charge pump, VCO control & power supply ClockCleaner bypass dvb-asi sd/hd DIN[19:0] I/O Buffer & demux TRS insertion, Line number insertion, CRC insertion, data blank, codere-map and flywheel DVB-ASI sync word insert & 8b/10b encode SMPTE 352M generation EDH generation & SMPTE scramble P -> S SDO_EN/DIS SDO SDO RSET HOST Interface / JTAG test Reset GS1531 Functional Block Diagram February of 50

3 Contents Key Features...1 Applications...1 Description...1 Functional Block Diagram Pin Out Pin Assignment Pin Descriptions Electrical Characteristics Absolute Maximum Ratings DC Electrical Characteristics AC Electrical Characteristics Solder Reflow Profiles Input/Output Circuits Host Interface Maps Host Interface Map (Read Only Registers) Host Interface Map (R/W Configurable Registers) Detailed Description Functional Overview Parallel Data Inputs Parallel Input in SMPTE Mode Parallel Input in DVB-ASI Mode Parallel Input in Data-Through Mode Parallel Input Clock (PCLK) SMPTE Mode Internal Flywheel HVF Timing Signal Extraction DVB-ASI mode Control Signal Inputs Data-Through Mode Additional Processing Functions Input Data Blank Automatic Video Standard Detection Packet Generation and Insertion Parallel-To-Serial Conversion Serial Digital Data PLL External VCO Lock Detect Output Loop Bandwidth Adjustment Serial Digital Output Output Swing February of 50

4 4.9.2 Serial Digital Output Mute GSPI Host Interface Command Word Description Data Read and Write Timing Configuration and Status Registers JTAG Device Power Up Device Reset Application Reference Design Typical Application Circuit References & Relevant Standards Package & Ordering Information Package Dimensions Packaging Data Ordering Information Revision History February of 50

5 1. Pin Out 1.1 Pin Assignment A LF VCO_ VCC VCO_ GND VCO VCO NC PCLK IO_VDD DIN18 DIN19 B CP_CAP CP_VDD CP_GND LB_ CONT NC NC DETECT _TRS IO_GND DIN16 DIN17 C NC PD_VDD PD_GND NC NC NC NC NC DIN14 DIN15 D NC NC NC NC DVB_ASI LOCKED NC NC DIN12 DIN13 E NC NC NC SD/HD CORE _GND CORE _VDD NC IO_VDD DIN10 DIN11 F RSV NC NC 20bit/ 10bit CORE _GND CORE _VDD NC IO_GND DIN8 DIN9 G NC SMPTE_ NC NC IOPROC RESET NC _EN/DIS BYPASS _TRST BLANK DIN6 DIN7 H SCLK SDOUT NC NC NC CS_ NC TMS _TCK _TDO H DIN4 DIN5 J NC SDIN NC NC NC SDO_EN V IO_GND /DIS _TDI DIN2 DIN3 K RSET CD_VDD SDO SD0 CD_GND JTAG/ HOST F IO_VDD DIN0 DIN February of 50

6 1.2 Pin Descriptions Table 1-1: Pin Descriptions Pin Number Name Timing Type Description A1 LF Analog Output Control voltage to external voltage controlled oscillator. Nominally +1.25V DC. A2 VCO_VCC Output Power A3 VCO_GND Output Power Power supply for the external voltage controlled oscillator. Connect to pin 7 of the GO1555/GO1525*. This pin is an output. Should be isolated from all other power supplies. *For new designs use GO1555 Ground reference for the external voltage controlled oscillator. Connect to pins 2, 4, 6, and 8 of the GO1555/GO1525*. This pin is an output. Should be isolated from all other grounds. *For new designs use GO1555 A4, A5 VCO, VCO Analog Input Differential inputs for the external VCO reference signal. For single ended devices such as the GO1555/GO1525*, VCO should be AC coupled to VCO_GND. VCO is nominally 1.485GHz. *For new designs use GO1555 A6, B5, B6, C1, C4, C5, C6, C7, C8, D1, D2, D3, D4, D7, D8, E1, E2, E3, E7, F2, F3, F7, G1, G2, G3, G7, H1, H2, H3, H7, J1, J2, J3, J4 NC No connect. A7 PCLK Input PARALLEL DATA BUS CLOCK Signal levels are LVCMOS/LVTTL compatible. HD 20-bit mode HD 10-bit mode SD 20-bit mode SD 10-bit mode PCLK = 74.25MHz or 74.25/1.001MHz PCLK = 148.5MHz or 148.5/1.001MHz PCLK = 13.5MHz PCLK = 27MHz A8, E8, K8 IO_VDD Power Power supply connection for digital I/O buffers. Connect to +3.3V DC digital February of 50

7 Table 1-1: Pin Descriptions (Continued) Pin Number Name Timing Type Description A10, A9, B10, B9, C10, C9, D10, D9, E10, E9 DIN[19:10] Synchronous with PCLK Input PARALLEL DATA BUS Signal levels are LVCMOS/LVTTL compatible. DIN19 is the MSB and DIN10 is the LSB. HD 20-bit mode SD/HD = LOW 20bit/10bit = HIGH Luma data input in SMPTE mode SMPTE_BYPASS = HIGH DVB_ASI = LOW Data input in Data-Through mode SMPTE_BYPASS = LOW DVB_ASI = LOW HD 10-bit mode SD/HD = LOW 20bit/10bit = LOW SD 20-bit mode SD/HD = HIGH 20bit/10bit = HIGH SD 10-bit mode SD/HD = HIGH 20bit/10bit = LOW Multiplexed Luma and Chroma data input in SMPTE mode SMPTE_BYPASS = HIGH DVB_ASI = LOW Data input in Data-Through mode SMPTE_BYPASS = LOW DVB_ASI = LOW Luma data input in SMPTE mode SMPTE_BYPASS = HIGH DVB_ASI = LOW Data input in Data-Through mode SMPTE_BYPASS = LOW DVB_ASI = LOW DVB-ASI data input in DVB-ASI mode SMPTE_BYPASS = LOW DVB_ASI = HIGH Multiplexed Luma and Chroma data input in SMPTE mode SMPTE_BYPASS = HIGH DVB_ASI = LOW Data input in data through mode SMPTE_BYPASS = LOW DVB_ASI = LOW DVB-ASI data input in DVB-ASI mode SMPTE_BYPASS = LOW DVB_ASI = HIGH B1 CP_CAP Analog Input PLL lock time constant capacitor connection. B2 CP_VDD Power Power supply connection for the charge pump. Connect to +3.3V DC analog. B3 CP_GND Power Ground connection for the charge pump. Connect to analog GND. B4 LB_CONT Analog Input Control voltage to set the loop bandwidth of the integrated reclocker. B7 DETECT_TRS Non Synchronous Input CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Used to select the timing mode of the device. When set HIGH, the device will lock the internal flywheel to the embedded TRS timing signals in the parallel input data. When set LOW, the device will lock the internal flywheel to the externally supplied H, V, and F input signals February of 50

8 Table 1-1: Pin Descriptions (Continued) Pin Number Name Timing Type Description B8, F8, J8 IO_GND Power Ground connection for digital I/O buffers. Connect to digital GND. C2 PD_VDD Power Power supply connection for the phase detector. Connect to +1.8V DC analog. C3 PD_GND Power Ground connection for the phase detector. Connect to analog GND. D5 DVB_ASI Non Synchronous D6 LOCKED Synchronous with PCLK E4 SD/HD Non Synchronous Input Output Input CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. When set HIGH in conjunction with SD/HD = HIGH and SMPTE_BYPASS = LOW, the device will be configured to operate in DVB-ASI mode. When set LOW, the device will not support the encoding of received DVB-ASI data. STATUS SIGNAL OUTPUT Signal levels are LVCMOS / LVTTL compatible. The LOCKED signal will be HIGH whenever the device has correctly received and locked to SMPTE compliant data in SMPTE mode or DVB-ASI compliant data in DVB-ASI mode, or when the device has achieved lock in Data-Through mode. It will be LOW otherwise. CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. When set LOW, the device will be configured to transmit signal rates of 1.485Gb/s or 1.485/1.001Gb/s only. When set HIGH, the device will be configured to transmit signal rates of 270Mb/s only. E5, F5 CORE_GND Power Ground connection for the digital core logic. Connect to digital GND. E6, F6 CORE_VDD Power Power supply connection for the digital core logic. Connect to +1.8V DC digital. F1 RSV Connect to Analog GND. F4 20bit/10bit Non Synchronous Input CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Used to select the input data bus width in SMPTE or Data-Through modes. When set HIGH, the parallel input will be 20-bit demultiplexed data. When set LOW, the parallel input will be 10-bit multiplexed data February of 50

9 Table 1-1: Pin Descriptions (Continued) Pin Number Name Timing Type Description F10, F9, G10, G9, H10, H9, J10, J9, K10, K9 DIN[9:0] Synchronous with PCLK Input PARALLEL DATA BUS Signal levels are LVCMOS/LVTTL compatible. DIN9 is the MSB and DIN0 is the LSB. HD 20-bit mode SD/HD = LOW 20bit/10bit = HIGH Chroma data input in SMPTE mode SMPTE_BYPASS =HIGH DVB_ASI = LOW Data input in Data-Through mode SMPTE_BYPASS = LOW DVB_ASI = LOW HD 10-bit mode SD/HD = LOW 20bit/10bit = LOW SD 20-bit mode SD/HD = HIGH 20bit/10bit = HIGH SD 10-bit mode SD/HD = HIGH 20bit/10bit = LOW High impedance in all modes. Chroma data input in SMPTE mode SMPTE_BYPASS = HIGH DVB_ASI = LOW Data input in Data-Through mode SMPTE_BYPASS = LOW DVB_ASI = LOW High impedance in DVB-ASI mode SMPTE_BYPASS = LOW DVB_ASI = HIGH High impedance in all modes. G4 IOPROC_EN/DIS Non Synchronous Input CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Used to enable or disable I/O processing features. When set HIGH, the following I/O processing features of the device are enabled: EDH Packet Generation and Insertion (SD-only) SMPTE 352M Packet Generation and Insertion ANC Data Checksum Calculation and Insertion Line-based CRC Generation and Insertion (HD-only) Line Number Generation and Insertion (HD-only) TRS Generation and Insertion Illegal Code Remapping To enable a subset of these features, keep IOPROC_EN/DIS HIGH and disable the individual feature(s) in the IOPROC_DISABLE register accessible via the host interface. When set LOW, the I/O processing features of the device are disabled, regardless of whether the features are enabled in the IOPROC_DISABLE register February of 50

10 Table 1-1: Pin Descriptions (Continued) Pin Number Name Timing Type Description G5 SMPTE_BYPASS Non Synchronous G6 RESET_TRST Non Synchronous G8 BLANK Synchronous with PCLK H4 CS_TMS Synchronous with SCLK_TCK H5 SCLK_TCK Non Synchronous Input Input Input Input Input CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. When set HIGH in conjunction with DVB_ASI = LOW, the device will be configured to operate in SMPTE mode. All I/O processing features may be enabled in this mode. When set LOW, the device will not support the scrambling or encoding of received SMPTE data. No I/O processing features will be available. CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Used to reset the internal operating conditions to default settings and to reset the JTAG test sequence. Host Mode (JTAG/HOST = LOW) When asserted LOW, all functional blocks will be set to default conditions and all input and output signals become high impedance, including the serial digital outputs SDO and SDO. Must be set HIGH for normal device operation. JTAG Test Mode (JTAG/HOST = HIGH) When asserted LOW, all functional blocks will be set to default and the JTAG test sequence will be held in reset. When set HIGH, normal operation of the JTAG test sequence resumes. CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Used to enable or disable input data blanking. When set LOW, the luma and chroma input data is set to the appropriate blanking levels. Horizontal and vertical ancillary spaces will also be set to blanking levels. When set HIGH, the luma and chroma input data pass through the device unaltered. CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Chip Select / Test Mode Select Host Mode (JTAG/HOST = LOW) CS_TMS operates as the host interface chip select, CS, and is active LOW. JTAG Test Mode (JTAG/HOST = HIGH) CS_TMS operates as the JTAG test mode select, TMS, and is active HIGH. NOTE: If the host interface is not being used, tie this pin HIGH. CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Serial Data Clock / Test Clock. Host Mode (JTAG/HOST = LOW) SCLK_TCK operates as the host interface burst clock, SCLK. Command and data read/write words are clocked into the device synchronously with this clock. JTAG Test Mode (JTAG/HOST = HIGH) SCLK_TCK operates as the JTAG test clock, TCK. NOTE: If the host interface is not being used, tie this pin HIGH February of 50

11 Table 1-1: Pin Descriptions (Continued) Pin Number Name Timing Type Description H6 SDOUT_TDO Synchronous with SCLK_TCK H8 H Synchronous with PCLK J5 SDO_EN/DIS Non Synchronous J6 SDIN_TDI Synchronous with SCLK_TCK Output Input Input Input CONTROL SIGNAL OUTPUT Signal levels are LVCMOS/LVTTL compatible. Serial Data Output / Test Data Output Host Mode (JTAG/HOST = LOW) SDOUT_TDO operates as the host interface serial output, SDOUT, used to read status and configuration information from the internal registers of the device. JTAG Test Mode (JTAG/HOST = HIGH) SDOUT_TDO operates as the JTAG test data output, TDO. CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Used to indicate the portion of the video line containing active video data when DETECT_TRS is set LOW. The device will set the H bit in all outgoing TRS signals for the entire period that the H input signal is HIGH (IOPROC_EN/DIS must also be HIGH). H signal timing is configurable via the H_CONFIG bit of the IOPROC_DISABLE register, accessible via the host interface. Active Line Blanking (H_CONFIG = 0 h ) The H signal should be set HIGH for the entire horizontal blanking period, including the EAV and SAV TRS words, and LOW otherwise. This is the default setting. TRS Based Blanking (H_CONFIG = 1 h ) The H signal should be set HIGH for the entire horizontal blanking period as indicated by the H bit in the received TRS ID words, and LOW otherwise. CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Used to enable or disable the serial digital output stage. When set LOW, the serial digital output signals SDO and SDO are disabled and become high impedance. When set HIGH, the serial digital output signals SDO and SDO are enabled. CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Serial Data In / Test Data Input Host Mode (JTAG/HOST = LOW) SDIN_TDI operates as the host interface serial input, SDIN, used to write address and configuration information to the internal registers of the device. JTAG Test Mode (JTAG/HOST = HIGH) SDIN_TDI operates as the JTAG test data input, TDI. NOTE: If the host interface is not being used, tie this pin HIGH February of 50

12 Table 1-1: Pin Descriptions (Continued) Pin Number Name Timing Type Description J7 V Synchronous with PCLK Input CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Used to indicate the portion of the video field / frame that is used for vertical blanking when DETECT_TRS is set LOW. The device will set the V bit in all outgoing TRS signals for the entire period that the V input signal is HIGH (IOPROC_EN/DIS must also be HIGH). The V signal should be set HIGH for the entire vertical blanking period and should be set LOW for all lines outside of the vertical blanking interval. The V signal is ignored when DETECT_TRS = HIGH. K1 RSET Analog Input Used to set the serial digital output signal amplitude. Connect to CD_VDD through 281Ω +/- 1% for 800mV p-p single-ended output swing. K2 CD_VDD Power Power supply connection for the serial digital cable driver. Connect to +1.8V DC analog. K3, K4 SDO, SDO Analog Output Serial digital output signal operating at 1.485Gb/s, 1.485/1.001Gb/s, or 270Mb/s. The slew rate of these outputs is automatically controlled to meet SMPTE 292M and 259M requirements according to the setting of the SD/HD pin. K5 CD_GND Power Ground connection for the serial digital cable driver. Connect to analog GND. K6 JTAG/HOST Non Synchronous K7 F Synchronous with PCLK Input Input CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Used to select JTAG Test Mode or Host Interface Mode. When set HIGH, CS_TMS, SDOUT_TDO, SDI_TDI and SCLK_TCK are configured for JTAG boundary scan testing. When set LOW, CS_TMS, SDOUT_TDO, SDI_TDI and SCLK_TCK are configured as GSPI pins for normal host interface operation. CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Used to indicate the ODD / EVEN field of the video signal when DETECT_TRS is set LOW. The device will set the F bit in all outgoing TRS signals for the entire period that the F input signal is HIGH (IOPROC_EN/DIS must also be HIGH). The F signal should be set HIGH for the entire period of field 2 and should be set LOW for all lines in field 1 and for all lines in progressive scan systems. The F signal is ignored when DETECT_TRS = HIGH February of 50

13 2. Electrical Characteristics 2.1 Absolute Maximum Ratings Parameter Supply Voltage Core Supply Voltage I/O Value/Units -0.3V to +2.1V -0.3V to +4.6V Input Voltage Range (any input) -2.0V to V Ambient Operating Temperature -20 C < T A < 85 C Storage Temperature -40 C < T STG < 125 C ESD Protection On All Pins (see Note 1) 1kV NOTES: 1. HBM, per JESDA-114B. 2.2 DC Electrical Characteristics Table 2-1: DC Electrical Characteristics T A = 0 C to 70 C, unless otherwise specified. Parameter Symbol Conditions Min Typ Max Units Test Level Notes System Operation Temperature Range T A 0 70 C 3 1 Digital Core Supply Voltage CORE_VDD V 3 1 Digital I/O Supply Voltage IO_VDD V 3 1 Charge Pump Supply Voltage CP_VDD V 3 1 Phase Detector Supply Voltage PD_VDD V 3 1 Input Buffer Supply Voltage BUFF_VDD V 3 1 Cable Driver Supply Voltage CD_VDD V 3 1 External VCO Supply Voltage Output VCO_VCC V V Supply Current I 1V8 SDO Enabled 245 ma V Supply Current I 3V3 45 ma 3 4 Total Device Power P D SDO Enabled 590 mw February of 50

14 Table 2-1: DC Electrical Characteristics (Continued) T A = 0 C to 70 C, unless otherwise specified. Parameter Symbol Conditions Min Typ Max Units Test Level Notes Digital I/O Input Logic LOW V IL 0.8 V 4 Input Logic HIGH V IH 2.1 V 4 Output Logic LOW V OL +8mA V 4 Output Logic HIGH V OH -8mA IO_VDD V 4 Input RSET Voltage V RSET RSET=281Ω V 1 2 Output Output Common Mode Voltage V CMOUT 75Ω load, RSET=281Ω, SD and HD TEST LEVELS 1. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges. 2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated test. 3. Production test at room temperature and nominal supply voltage. 4. QA sample test. 5. Calculated result based on Level 1, 2, or Not tested. Guaranteed by design simulations. 7. Not tested. Based on characterization of nominal parts. 8. Not tested. Based on existing design/characterization data of similar product. 9. Indirect test V 1 NOTES 1. All DC and AC electrical parameters within specification. 2. Set by the value of the RSET resistor. 3. Sum of all 1.8V supplies. 4. Sum of all 3.3V supplies. 2.3 AC Electrical Characteristics Table 2-2: AC Electrical Characteristics T A = 0 C to 70 C, unless otherwise shown Parameter Symbol Conditions Min Typ Max Units Test Level Notes System Device Latency 10-bit SD 21 PCLK 8 20-bit HD 19 PCLK 8 DVB-ASI 11 PCLK 8 Reset Pulse Width t reset 1 ms February of 50

15 Table 2-2: AC Electrical Characteristics (Continued) T A = 0 C to 70 C, unless otherwise shown Parameter Symbol Conditions Min Typ Max Units Test Level Notes Parallel Input Parallel Clock Frequency f PCLK MHz 4 Parallel Clock Duty Cycle DC PCLK % 6 Input Data Setup Time t su 2.0 ns 5 Input Data Hold Time t ih 1.5 ns 5 Serial Digital Output Serial Output Data Rate DR SDO Gb/s /1.001 Gb/s Mb/s 1 Serial Output Swing ΔV SDD RSET = 281Ω 75Ω load mvp-p 1 Serial Output Rise Time 20% ~ 80% Serial Output Fall Time 20% ~ 80% tr SDO HD signal 260 ps 1 tr SDO SD signal ps 1 tf SDO HD signal 260 ps 1 tf SDO SD signal ps 1 Serial Output Intrinsic Jitter t IJ Pseudorandom and pathological HD signal GSPI t IJ Pseudorandom and pathological SD signal ps ps 5 GSPI Input Clock Frequency f SCLK 6.6 MHz 8 GSPI Input Clock Duty Cycle DC SCLK % 8 GSPI Input Data Setup Time 0 ns 8 GSPI Input Data Hold Time 1.43 ns 8 GSPI Output Data Hold Time 2.1 ns 8 GSPI Output Data Delay 7.27 ns 8 Time TEST LEVELS NOTES 1. Production test at room temperature and nominal supply voltage 1. See Device Power Up on page 45, Figure with guardbands for supply and temperature ranges. 2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated test. 3. Production test at room temperature and nominal supply voltage. 4. QA sample test. 5. Calculated result based on Level 1, 2, or Not tested. Guaranteed by design simulations. 7. Not tested. Based on characterization of nominal parts. 8. Not tested. Based on existing design/characterization data of similar product. 9. Indirect test February of 50

16 2.4 Solder Reflow Profiles The GS1531 is available in a Pb or Pb-free package. It is recommended that the Pb package be soldered with Pb paste using the Standard Eutectic profile shown in Figure 2-1, and the Pb-free package be soldered with Pb-free paste using the reflow profile shown in Figure 2-2. NOTE: It is possible to solder a Pb-free package with Pb paste using a Standard Eutectic profile with a reflow temperature maintained at 245 o C 250 o C. Temperature sec sec. 230 C 220 C 183 C 3 C/sec max 6 C/sec max 150 C 100 C 25 C 120 sec. max Time 6 min. max Figure 2-1: Standard Eutectic Solder Reflow Profile (Pb package, Pb paste) Temperature sec sec. 260 C 250 C 217 C 3 C/sec max 6 C/sec max 200 C 150 C 25 C sec. max Time 8 min. max Figure 2-2: Maximum Pb-free Solder Reflow Profile (Pb-free package, Pb-free paste) February of 50

17 3. Input/Output Circuits All resistors in ohms, all capacitors in farads, unless otherwise shown. SDO SDO Figure 3-1: Serial Digital Output LF 300 CP_CAP Figure 3-2: VCO Control Output & PLL Lock Time Capacitor VDD 42K 63K PCLK Figure 3-3: PCLK Input February of 50

18 VCO 25 VDD 1.5K 25 5K VCO Figure 3-4: VCO Input LB_CONT 865mV 7.2K Figure 3-5: PLL Loop Bandwidth Control February of 50

19 3.1 Host Interface Maps REGISTER NAME ADDRESS LINE_352M_f2 1Ch Not Used Not Used Not Used Not Used Not Used b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 LINE_352M_f1 1Bh Not Used Not Used Not Used Not Used Not Used b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 1Ah FF_LINE_END_F1 19h Not Used Not Used Not Used Not Used Not Used Not Used b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 FF_LINE_START_F1 18h Not Used Not Used Not Used Not Used Not Used Not Used b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 FF_LINE_END_F0 17h Not Used Not Used Not Used Not Used Not Used Not Used b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 FF_LINE_START_F0 16h Not Used Not Used Not Used Not Used Not Used Not Used b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 AP_LINE_END_F1 15h Not Used Not Used Not Used Not Used Not Used Not Used b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 AP_LINE_START_F1 14h Not Used Not Used Not Used Not Used Not Used Not Used b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 AP_LINE_END_F0 13h Not Used Not Used Not Used Not Used Not Used Not Used b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 AP_LINE_START_F0 12h Not Used Not Used Not Used Not Used Not Used Not Used b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 RASTER_STRUCTURE4 11h Not Used Not Used Not Used Not Used Not Used b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 RASTER_STRUCTURE3 10h Not Used Not Used Not Used Not Used Not Used b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 RASTER_STRUCTURE2 0Fh Not Used Not Used Not Used Not Used b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 RASTER_STRUCTURE1 0Eh Not Used Not Used Not Used Not Used b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0Dh 0Ch VIDEO_FORMAT_B 0Bh VF4-b7 VF4-b6 VF4-b5 VF4-b4 VF4-b3 VF4-b2 VF4-b1 VF4-b0 VF3-b7 VF3-b6 VF3-b5 VF3-b4 VF3-b3 VF3-b2 VF3-b1 VF3-b0 VIDEO_FORMAT_A 0Ah VF2-b7 VF2-b6 VF2-b5 VF2-b4 VF2-b3 VF2-b2 VF2-b1 VF2-b0 VF1-b7 VF1-b6 VF1-b5 VF1-b4 VF1-b3 VF1-b2 VF1-b1 VF1-b0 09h 08h 07h 06h 05h VIDEO_STANDARD 04h Not Used VDS-b4 VDS-b3 VDS-b2 VDS-b1 VDS-b0 INT_PROG STD_ NOT USED NOT USED NOT USED NOT USED NOT USED NOT USED NOT USED NOT USED LOCK 03h EDH_FLAG 02h Not Used ANC-UES ANC-IDA ANC-IDH ANC-EDA ANC-EDH FF-UES FF-IDA FF-IDH FF-EDA FF-EDH AP-UES AP-IDA AP-IDH AP-EDA AP-EDH 01h IOPROC_DISABLE 00h Not Used Not Used Not Used Not Used Not Used Not Used Not Used H_CONFIG Not Used 352M_INS ILLEGAL_RE EDH_CRC_IN ANC_ CRC_INS LNUM_ INS TRS_INS MAP S CSUM_INS February of 50

20 3.1.1 Host Interface Map (Read Only Registers) REGISTER NAME ADDRESS Ch 1Bh 1Ah 19h 18h 17h 16h 15h 14h 13h 12h RASTER_STRUCTURE4 11h b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 RASTER_STRUCTURE3 10h b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 RASTER_STRUCTURE2 0Fh b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 RASTER_STRUCTURE1 0Eh b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0Dh 0Ch 0Bh 0Ah 09h 08h 07h 06h 05h VIDEO_STANDARD 04h VDS-b4 VDS-b3 VDS-b2 VDS-b1 VDS-b0 INT_PROG STD_ LOCK 03h 02h 01h 00h February of 50

21 3.1.2 Host Interface Map (R/W Configurable Registers) REGISTER NAME ADDRESS LINE_352M_f2 1Ch b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 LINE_352M_f1 1Bh b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 1Ah FF_LINE_END_F1 19h b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 FF_LINE_START_F1 18h b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 FF_LINE_END_F0 17h b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 FF_LINE_START_F0 16h b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 AP_LINE_END_F1 15h b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 AP_LINE_START_F1 14h b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 AP_LINE_END_F0 13h b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 AP_LINE_START_F0 12h b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 11h 10h 0Fh 0Eh 0Dh 0Ch VIDEO_FORMAT_B 0Bh VF4-b7 VF4-b6 VF4-b5 VF4-b4 VF4-b3 VF4-b2 VF4-b1 VF4-b0 VF3-b7 VF3-b6 VF3-b5 VF3-b4 VF3-b3 VF3-b2 VF3-b1 VF3-b0 VIDEO_FORMAT_A 0Ah VF2-b7 VF2-b6 VF2-b5 VF2-b4 VF2-b3 VF2-b2 VF2-b1 VF2-b0 VF1-b7 VF1-b6 VF1-b5 VF1-b4 VF1-b3 VF1-b2 VF1-b1 VF1-b0 09h 08h 07h 06h 05h 04h 03h EDH_FLAG 02h ANC-UES ANC-IDA ANC-IDH ANC-EDA ANC-EDH FF-UES FF-IDA FF-IDH FF-EDA FF-EDH AP-UES AP-IDA AP-IDH AP-EDA AP-EDH 01h IOPROC_DISABLE 00h H_CONFIG 352M_INS ILLEGAL_RE EDH_CRC_IN ANC_ CRC_INS LNUM_ INS TRS_INS MAP S CSUM_INS February of 50

22 4. Detailed Description 4.1 Functional Overview The GS1531 is a multi-rate serializer with an integrated cable driver. When used in conjunction with the external GO1555/GO1525* Voltage Controlled Oscillator, a transmit solution at 1.485Gb/s, 1.485/1.001Gb/s or 270Mb/s is realized. The device has three different modes of operation which must be set through external device pins. When SMPTE mode is enabled, the device will accept 10-bit multiplexed or 20-bit demultiplexed SMPTE compliant data at both HD and SD signal rates. The device s additional processing features are also enabled in this mode. In DVB-ASI mode, the GS1531 will accept an 8-bit parallel DVB-ASI compliant transport stream on its upper input bus. The serial output data stream will be 8b/10b encoded and stuffed. The GS1531 s third mode allows for the serializing of data not conforming to SMPTE or DVB-ASI streams. The provided serial digital outputs feature a high impedance mode, output mute on loss of parallel clock and adjustable signal swing. The output slew rate is automatically controlled by the SD/HD setting. In the digital signal processing core, several data processing functions are implemented including SMPTE 352M and EDH data packet generation and insertion, and automatic video standards detection. These features are all enabled by default, but may be individually disabled via internal registers accessible through the GSPI host interface. Finally, the GS1531 contains a JTAG interface for boundary scan test implementations. *For new designs use GO Parallel Data Inputs Data inputs enter the device on the rising edge of PCLK as shown in Figure 4-1. The input data format is defined by the setting of the external SD/HD, SMPTE_BYPASS and DVB_ASI pins and may be presented in 10-bit or 20-bit format. The input data bus width is controlled independently from the internal data bus width by the 20bit/10bit input pin February of 50

23 PCLK DIN[19:0] DATA Control signal input tsu tih Figure 4-1: PCLK to Data Timing Parallel Input in SMPTE Mode When the device is operating in SMPTE mode, see SMPTE Mode on page 25, both SD and HD data may be presented to the input bus in either multiplexed or demultiplexed form depending on the setting of the 20bit/10bit input pin. In 20-bit mode, (20bit/10bit = HIGH), the input data format should be word aligned, demultiplexed luma and chroma data. Luma words should be presented to DIN[19:10] while chroma words should occupy DIN[9:0]. In 10-bit mode, (20bit/10bit = LOW), the input data format should be word aligned, multiplexed luma and chroma data. The data should be presented to DIN[19:10]. DIN[9:0] will be high impedance in this mode Parallel Input in DVB-ASI Mode When operating in DVB-ASI mode, see DVB-ASI mode on page 26, the GS1531 requires the input data bus to be configured for 10-bit operation (20bit/10bit = LOW). The device accepts 8-bit data words on DIN[17:10] such that DIN17 = HIN is the most significant bit of the encoded transport stream data and DIN10 = AIN is the least significant bit. In addition, DIN19 and DIN18 are configured as the DVB-ASI control signals INSSYNCIN and KIN respectively. See DVB-ASI mode on page 26 for a description of these DVB-ASI specific input signals. The pins DIN[9:0] are high impedance when the GS1531 is operating in DVB-ASI mode Parallel Input in Data-Through Mode When operating in Data-Through mode, see Data-Through Mode on page 28, the GS1531 passes data presented to the parallel input bus to the serial output without performing any encoding or scrambling. The input data bus width accepted by the device in this mode is controlled by the setting of the 20bit/10bit pin February of 50

24 4.2.4 Parallel Input Clock (PCLK) The frequency of the PCLK input signal required by the GS1531 is determined by the input data format. Table 4-1 below lists the possible input signal formats and their corresponding parallel clock rates. NOTE: DVB-ASI input requires a 10-bit wide input data bus (20bit/10bit = LOW). Table 4-1: Parallel Data Input Format Control Signals Input Data Format DIN [19:10] DIN [9:0] PCLK 20bit/ 10bit SD/ HD SMPTE_BYPASS DVB_ASI SMPTE MODE 20bit DEMULTIPLEXED SD LUMA CHROMA 13.5MHz HIGH HIGH HIGH LOW 10bit MULTIPLEXED SD LUMA / CHROMA HIGH IMPEDANCE 27MHz LOW HIGH HIGH LOW 20bit DEMULTIPLEXED HD LUMA CHROMA or 74.25/ 1.001MHz HIGH LOW HIGH LOW 10bit MULTIPLEXED HD LUMA / CHROMA HIGH IMPEDANCE or 148.5/ 1.001MHz LOW LOW HIGH LOW DVB-ASI MODE 10bit DVB-ASI DVB-ASI DATA HIGH IMPEDANCE 27MHz LOW HIGH LOW HIGH LOW HIGH LOW HIGH DATA-THROUGH MODE 20bit DEMULTIPLEXED SD DATA DATA 13.5MHz HIGH HIGH LOW LOW 10bit MULTIPLEXED SD DATA HIGH IMPEDANCE 27MHz LOW HIGH LOW LOW 20bit DEMULTIPLEXED HD DATA DATA or 74.25/ 1.001MHz HIGH LOW LOW LOW 10bit MULTIPLEXED HD DATA HIGH IMPEDANCE or 148.5/ 1.001MHz LOW LOW LOW LOW February of 50

25 4.3 SMPTE Mode The GS1531 is said to be in SMPTE mode when the SMPTE_BYPASS pin is set HIGH and the DVB_ASI pin is set LOW. In this mode, the parallel data will be scrambled according to SMPTE 259M or 292M, and NRZ-to-NRZI encoded prior to serialization Internal Flywheel The GS1531 has an internal flywheel which is used in the generation of internal / external timing signals, and in automatic video standards detection. It is operational in SMPTE mode only. The flywheel consists of a number of counters and comparators operating at video pixel and video line rates. These counters maintain information about the total line length, active line length, total number of lines per field / frame and total active lines per field / frame for the received video standard. When DETECT_TRS is LOW, the flywheel will be locked to the externally supplied H, V, and F timing signals. When DETECT_TRS is HIGH, the flywheel will be locked to the embedded TRS signals in the parallel input data. Both 8-bit and 10-bit TRS code words will be identified by the device. The flywheel 'learns' the video standard by timing the horizontal and vertical reference information supplied a the H, V, and F input pins, or contained in the TRS ID words of the received video data. Full synchronization of the flywheel to the received video standard therefore requires one complete video frame. Once synchronization has been achieved, the flywheel will continue to monitor the received TRS timing or the supplied H, V, and F timing information to maintain synchronization HVF Timing Signal Extraction As discussed above, the GS1531's internal flywheel may be locked to externally provided H, V, and F signals when DETECT_TRS is set LOW. The H signal timing should also be configured via the H_CONFIG bit of the internal IOPROC_DISABLE register as either active line based blanking or TRS based blanking, see Packet Generation and Insertion on page 30. Active line based blanking is enabled when the H_CONFIG bit is set LOW. In this mode, the H input should be HIGH for the entire horizontal blanking period, including the EAV and SAV TRS words. This is the default H timing assumed by the device. When H_CONFIG is set HIGH, TRS based blanking is enabled. In this case, the H input should be set HIGH for the entire horizontal blanking period as indicated by the H bit in the associated TRS words. The timing of these signals is shown in Figure February of 50

26 PCLK LUMA DATA OUT 3FF XYZ (eav) 3FF XYZ (sav) CHROMA DATA OUT 3FF XYZ (eav) 3FF XYZ (sav) H V F H:V:F TIMING - HD 20-BIT INPUT MODE PCLK MULTIPLEXED Y/Cr/Cb DATA OUT 3FF 3FF XYZ (eav) XYZ (eav) H V F H:V:F TIMING AT EAV - HD 10-BIT INPUT MODE PCLK MULTIPLEXED Y/Cr/Cb DATA OUT 3FF 3FF XYZ (sav) XYZ (sav) H V F H;V:F TIMING AT SAV - HD 10-BIT INPUT MODE PCLK CHROMA DATA OUT 3FF 000 3FF 000 LUMA DATA OUT 000 XYZ (eav) 000 XYZ (SAV) H H SIGNAL TIMING: H_CONFIG = LOW H_CONFIG = HIGH V F H:V:F TIMING - SD 20-BIT INPUT MODE PCLK MULTIPLEXED Y/Cr/Cb DATA OUT 3FF XYZ (eav) 3FF XYZ (sav) H V F H:V:F TIMING - SD 10-BIT INPUT MODE Figure 4-2: H, V, F Timing 4.4 DVB-ASI mode To operate the GS1531 in DVB-ASI mode, set the SMPTE_BYPASS and 20bit/10bit pins LOW, and the DVB_ASI and SD/HD pins HIGH February of 50

27 4.4.1 Control Signal Inputs In DVB-ASI mode, the DIN19 and DIN18 pins will be configured as DVB-ASI control signals INSSYNCIN and KIN respectively. When INSSYNCIN is set HIGH, the device will insert K28.5 sync characters into the data stream. This function is used to assist system implementations where the GS1531 may be preceded by an external data FIFO. Parallel DVB-ASI data may be clocked into the FIFO at some rate less than 27MHz. The INSSYNCIN input may then be connected to the FIFO empty signal, thus providing a means of padding up the data transmission rate to 27MHz. See Figure 4-3. NOTE: 8b/10b encoding will take place after K28.5 sync character insertion. KIN should be set HIGH whenever the parallel data input is to be interpreted as any special character defined by the DVB-ASI standard (including the K28.5 sync character). This pin should be set LOW when the input is to be interpreted as data. NOTE: When operating in DVB-ASI mode, DIN[9:0] become high impedance. TS 8 FIFO AIN ~ HIN 8 GS1531 SDO SDO KIN KIN WRITE_CLK <27MHz CLK_IN FE INSSYNCIN READ CLK =27MHz CLK_OUT PCLK = 27MHz Figure 4-3: DVB-ASI FIFO Implementation using the GS February of 50

28 4.5 Data-Through Mode The GS1531 may be configured to operate as a simple parallel-to-serial converter. In this mode, the device presents data to the output buffer without performing any scrambling or encoding. Data-through mode is enabled only when both the SMPTE_BYPASS and DVB_ASI pins are set LOW. 4.6 Additional Processing Functions The GS1531 contains an additional data processing block which is available in SMPTE mode only, see SMPTE Mode on page Input Data Blank The video input data may be 'blanked' by the GS1531. In this mode, all input video data except TRS words are set to the appropriate blanking levels by the device. Both the horizontal and vertical ancillary data spaces will also be set to blanking levels. This function is enabled by setting the BLANK pin LOW Automatic Video Standard Detection The GS1531 can detect the input video standard by using the timing parameters extracted from the received TRS ID words or supplied H, V, and F timing signals, see Internal Flywheel on page 25. This information is presented to the host interface via the VIDEO_STANDARD register (Table 4-2). Total samples per line, active samples per line, total lines per field/frame and active lines per field/frame are also calculated and presented to the host interface via the RASTER_STRUCTURE registers (Table 4-3). These line and sample count registers are updated once per frame at the end of line 12. This is in addition to the information contained in the VIDEO_STANDARD register. After device reset, the four RASTER_STRUCTURE registers default to zero. Table 4-2: Host Interface Description for Video Standard Register Register Name Bit Name Description R/W Default VIDEO_STANDARD Address: 004h 15 Not Used VD_STD[4:0] Video Data Standard (see Table 4-4). R 0 9 INT_PROG Interlace/Progressive: Set LOW if detected video standard is PROGRESSIVE and is set HIGH if it is INTERLACED. 8 STD_LOCK Standard Lock: Set HIGH when flywheel has achieved full synchronization. R 0 R Not Used February of 50

29 Table 4-3: Host Interface Description for Raster Structure Registers Register Name Bit Name Description R/W Default RASTER_STRUCTURE1 Address: 00Eh RASTER_STRUCTURE2 Address: 00Fh RASTER_STRUCTURE3 Address: 010h RASTER_STRUCTURE4 Address: 011h Not Used RASTER_STRUCTURE_1[11:0] Words Per Active Line R Not Used RASTER_STRUCTURE_2[12:0] Words Per Total Line. R Not Used RASTER_STRUCTURE_3[10:0] Total Lines Per Frame R Not Used RASTER_STRUCTURE_4[10:0] Active Lines Per Field R Video Standard Indication The video standard codes reported in the VD_STD[4:0] bits of the VIDEO_STANDARD register represent the SMPTE standards as shown in Table 4-4. In addition to the 5-bit video standard code word, the VIDEO_STANDARD register also contains two status bits. The STD_LOCK bit will be set HIGH whenever the flywheel has achieved full synchronization. The INT_PROG bit will be set LOW if the detected video standard is progressive and HIGH if the detected video standard is interlaced. The VD_STD[4:0], STD_LOCK and INT_PROG bits of the VIDEO_STANDARD register will default to zero after device reset. The VD_STD[4:0] and INT_PROG bits will also default to zero if the SMPTE_BYPASS pin is asserted LOW or if the LOCKED output is LOW. The STD_LOCK bit will retain its previous value if the PCLK is removed. Table 4-4: Supported Video Standards VD_STD[4:0] SMPTE Standard Video Format Length of HANC Length of Active Video Total Samples SMPTE352M Lines 00h 296M (HD) 1280x720/60 (1:1) h 296M (HD) 1280x720/60 (1:1) - EM h 296M (HD) 1280x720/30 (1:1) h 296M (HD) 1280x720/30 (1:1) - EM h 296M (HD) 1280x720/50 (1:1) h 296M (HD) 1280x720/50 (1:1) - EM h 296M (HD) 1280x720/25 (1:1) h 296M (HD) 1280x720/25 (1:1) - EM February of 50

30 Table 4-4: Supported Video Standards (Continued) VD_STD[4:0] SMPTE Standard Video Format Length of HANC Length of Active Video Total Samples SMPTE352M Lines 08h 296M (HD) 1280x720/24 (1:1) h 296M (HD) 1280x720/24 (1:1) - EM Ah 274M (HD) 1920x1080/60 (2:1) or 1920x1080/30 (PsF) , 572 0Bh 274M (HD) 1920x1080/30 (1:1) Ch 274M (HD) 1920x1080/50 (2:1) or 1920x1080/25 (PsF) , 572 0Dh 274M (HD) 1920x1080/25 (1:1) Eh 274M (HD) 1920x1080/25 (1:1) - EM Fh 274M (HD) 1920x1080/25 (PsF) - EM , h 274M (HD) 1920x1080/24 (1:1) h 274M (HD) 1920x1080/24 (PsF) , h 274M (HD) 1920x1080/24 (1:1) - EM h 274M (HD) 1920x1080/24 (PsF) - EM , h 295M (HD) 1920x1080/50 (2:1) , h 260M (HD) 1920x1035/60 (2:1) , h 125M (SD) 1440x487/60 (2:1) (Or dual link progressive) , h 125M (SD) 1440x507/60 (2:1) , h 125M (SD) 525-line 487 generic , 276 1Bh 125M (SD) 525-line 507 generic , h ITU-R BT.656 (SD) 1440x576/50 (2:1) (Or dual link progressive) , 322 1Ah ITU-R BT.656 (SD) 625-line generic (EM) , 322 1Dh Unknown HD 1Eh Unknown SD 1Ch, 1Fh Reserved NOTE: Though the GS1531 will work correctly on and serialize both 59.94Hz and 60Hz formats, it will not distinguish between them Packet Generation and Insertion In addition to input data blanking and automatic video standards detection, the GS1531 may also calculate, assemble and insert into the data stream various types of ancillary data packets and TRS ID words February of 50

31 These features are only available when the device is set to operated in SMPTE mode and the IOPROC_EN/DIS pin is set HIGH. Individual insertion features may be enabled or disabled via the IOPROC_DISABLE register (Table 4-5). All of the IOPROC_DISABLE register bits default to '0' after device reset, enabling all of the processing features. To disable any individual error correction feature, the host interface must set the corresponding bit HIGH in this register. Table 4-5: Host Interface Description for Internal Processing Disable Register Register Name Bit Name Description R/W Default IOPROC_DISABLE Address: 000h 15-9 Not Used. 8 H_CONFIG Horizontal sync timing input configuration. Set LOW when the H input timing is based on active line blanking (default). Set HIGH when the H input timing is based on the H bit of the TRS words. See Figure Not Used M_INS SMPTE352M packet insertion. In HD mode, 352M packets are inserted in the Y channel only when one of the bytes in the VIDEO_FORMAT_A or VIDEO_FORMAT_B registers are programmed with non-zero values. The IOPROC_EN/DIS pin and SMPTE_BYPASS pin must also be set HIGH. Set HIGH to disable. 5 ILLEGAL_REMAP Illegal Code Remapping. Detection and correction of illegal code words within the active picture area (AP). The IOPROC_EN/DIS pin and SMPTE_BYPASS pin must also be set HIGH. Set HIGH to disable. 4 EDH_CRC_INS Error Detection & Handling (EDH) Cyclical Redundancy Check (CRC) error correction. In SD mode the GS1531 will generate and insert EDH packets. The IOPROC_EN/DIS pin and SMPTE_BYPASS pin must also be set HIGH. Set HIGH to disable. 3 ANC_CSUM_INS Ancillary Data Checksum insertion. The IOPROC_EN/DIS pin and SMPTE_BYPASS pin must also be set HIGH. Set HIGH to disable. 2 CRC_INS Y and C line-based CRC insertion. In HD mode, line-based CRC words are inserted in both the Y and C channels. The IOPROC_EN/DIS pin and SMPTE_BYPASS pin must be also set HIGH. Set HIGH to disable 1 LNUM_INS Y and C line number insertion - HD mode only. The IOPROC_EN/DIS pin and SMPTE_BYPASS pin must be set HIGH. Set HIGH to disable. 0 TRS_INS Timing Reference Signal Insertion. Occurs only when IOPROC_EN/DIS is HIGH and SMPTE_BYPASS is HIGH. Set HIGH to disable February of 50

32 SMPTE 352M Payload Identifier Insertion The GS1531 can generate and insert SMPTE 352M payload identifier ancillary data packets into the data stream, based on information programmed into the host interface. When this feature is enabled, the device will automatically generate the ancillary data preambles, (DID, SDID, DBN, DC), and calculate the checksum. The SMPTE 352M packet will be inserted into the data stream according to the line numbers programmed in the LINE_352M registers (Table 4-6). The insertion process will only take place if one or more of the four VIDEO_FORMAT registers (Table 4-7) have been programmed with non-zero values. In addition, the GS1531 requires the 352M_INS bit of the IOPROC_DISABLE register be set LOW. NOTE 1: For the purpose of determining the line and pixel position for insertion, the GS1531 will differentiate between PsF and interlaced formats by interrogating bits 14 and 15 of the VIDEO_FORMAT_A register. The packets will be inserted immediately after the EAV word in SD video streams and immediately after the line-based CRC word in the Y channel of HD video streams. NOTE 2: It is the responsibility of the user to ensure that there is sufficient space in the horizontal blanking interval for the insertion of the SMPTE 352M packets. If there are other ancillary data packets present, the SMPTE 352M packet will be inserted in the first available location in the horizontal ancillary space. Ancillary data must be adjacent to the EAV in SD streams or to the line based-crc in HD streams. Where there is insufficient space available, the 352M packets will not be inserted. Table 4-6: Host Interface Description for SMPTE 352M Packet Line Number Insertion Registers Register Name Bit Name Description R/W Default LINE_352M_f1 Address: 01Bh LINE_352M_f2 Address: 01Ch Not Used LINE_0_352M[10:0] Line number where SMPTE352M packet is inserted in field Not Used LINE_1_352M[10:0] Line number where SMPTE352M packet is inserted in field February of 50

33 Table 4-7: Host Interface Description for SMPTE 352M Payload Identifier Registers Register Name Bit Name Description R/W Default VIDEO_FORMAT_B Address: 00Bh 15-8 SMPTE352M Byte 4 SMPTE 352M Byte 4 information must be programmed in this register when 352M_INS = LOW. 7-0 SMPTE352M Byte 3 SMPTE 352M Byte 3 information must be programmed in this register when 352M_INS = LOW. VIDEO_FORMAT_A Address: 00Ah 15-8 SMPTE352M Byte 2 SMPTE 352M Byte 2 information must be programmed in this register when 352M_INS = LOW. 7-0 SMPTE 352M Byte 1 SMPTE 352M Byte 1 information must be programmed in this register when 352M_INS = LOW Illegal Code Remapping If the ILLEGAL_REMAP bit of the IOPROC_DISABLE register is set LOW, the GS1531 will remap all codes within the active picture between the values of 3FCh and 3FFh to 3FBh. All codes within the active picture area between the values of 000h and 003h will be remapped to 004h. In addition, 8-bit TRS and ancillary data preambles will be remapped to 10-bit values if this feature is enabled EDH Generation and Insertion When operating in SD mode, (SD/HD = HIGH), the GS1531 will generate and insert complete EDH packets into the data stream. Packet generation and insertion will only take place if the EDH_CRC_INS bit of the IOPROC_DISABLE register is set LOW. The GS1531 will generate all of the required EDH packet data including all ancillary data preambles, (DID, DBN, DC), reserved code words and checksum. Calculation of both full field (FF) and active picture (AP) CRC's will be carried out by the device. SMPTE RP165 specifies the calculation ranges and scope of EDH data for standard 525 and 625 component digital interfaces. The GS1531 will utilize these standard ranges by default. If the received video format does not correspond to 525 or 625 digital component video standards as determined by the flywheel pixel and line counters, then one of two schemes for determining the EDH calculation ranges will be employed: 1. Ranges will be based on the line and pixel ranges programmed by the host interface; or 2. In the absence of user-programmed calculation ranges, ranges will be determined from the received TRS ID words or supplied H, V, and F timing signals, see Internal Flywheel on page February of 50