SUBJECT NAME : DIGITAL ELECTRONICS SUBJECT CODE : EC8392 1. State Demorgan s Theorem. QUESTION BANK PART A UNIT - I DIGITAL FUNDAMENTALS De Morgan suggested two theorems that form important part of Boolean algebra. They are, i. The complement of a product is equal to the sum of the complements. (AB)' = A' + B' ii. The complement of a sum term is equal to the product of the complements. (A + B)' = A'B' 2. Implement using NAND gates only, F = x y z + x y.

3. What are Don t care terms? In some logic circuits certain input conditions never occur, therefore the corresponding output never appears. In such cases the output level is not defined, it can be either high or low. These output levels are indicated by X or d in the truth tables and are called don t care conditions or incompletely specified functions. 4. Apply De-Morgan s theorem to [ (A+B) + C ]. Given [(A+B)+C] = (A+B).C = (A.B ).C [(A+B)+C] = A B C 5. Convert 0.35 to equivalent hexadecimal number. Given (0.35) 10 =0.35 x 16=5.60 =0.60 x 16=9.60 =0.60 x 16=9.60 (0.35) 10 = (0.599) 16 6. Convert Y=A+BC +AB+A BC into canonical form. Given Y=A+BC +AB+A BC Y=A(B+B )(C+C )+(A+A )BC +AB(C+C )+A BC Y=ABC+ABC +AB C+AB C +ABC +A BC +ABC+ABC +A BC Y=ABC+ABC +AB C+AB C +A BC +A BC 7. Define min term and max term. A product term containing all the variables of the function in either complemented or uncomplemented form is called a min term. A sum term containing all the variables of the function in either complemented or uncomplemented form is called a max term. 8. Prove that the logical sum of all min terms of a Boolean function of 2 variables is 1. Consider two variables as A and B. For two variables A and B minterms are: A B,A B,AB,AB. The logical sum of these minterms are given by F= A B +A B+AB +AB = A (B +B)+A(B +B) (B +B=1) = A (1)+A(1) (A +A=1) F=1 Hence it is to be proved.

9. Show that a positive logic NAND gate is a negative logic NOR gate. Truth table for positive logic NAND gate and negative logic NOR gates are same and hence a positive logic NAND gate is negative logic NOR gate. 10. Simplify the following Boolean Expression to a minimum number of literals. (BC +A D)(AB +CD ) F=(BC +A D)(AB +CD ) =BC AB +BC CD +A DAB +A DCD (A.A =0) = AB B C +BCC D +AA B D+A CDD F=0 11. Simplify the given Boolean Expression F=x +xy+xz +xy z. F=x +xy+xz +xy z = x +x(y+z +y z ) (A+A B=A+B) = x +y+z +y z = x +y+z (1+y ) (1+A =1) F = x +y+z

12. Implement the given function using NAND gates F(x,y,z)= Σm(0,6). F(x,y,z)=x y z +xyz 13. State Distributive Law. Distributive law of dot(.) over plus(+) is given by a.(b+c) = a.b + a.c Distributive law of plus(+) over dot(.) is given by a+b.c = (a+b).(a+c) 14. What is Prime Implicant? A prime implicant is a group of minterms which cannot be combined with any other minterms or groups. 15. Simplify the following Boolean expression into one literal. W X(Z +YZ)+X(W+ Y Z) F= W X(Z +YZ)+X(W+ Y Z) = W XZ +W XYZ+WX+XY Z =X(W Z +W YZ+W+Y Z) = X(W Z +W+Z(Y +W Y)) = X(W Z +W+Z(Y + Y )( Y +W )) = X(W Z +W+Z( Y +W )) = X(W Z +W+ZY +W Z) = X(W (Z +Z)+W+ZY ) = X(W +W+ZY ) = X(1+ZY )=X.1 F =X

UNIT - 2 COMBINATIONAL CIRCUIT DESIGN 1 Write an expression for borrow and difference in a full subtractor circuit. Difference = A B+AB =A B Borrow = A B 2 Design a single bit magnitude comparator to compare two words A and B. 3 What is an encoder? An encoder has 2 n input lines and n output lines. In encoder the output lines generate the binary code corresponding to the input value. 4 List few applications of multiplexer. Data Selector. Implement combinational logic circuit. Time multiplexing systems Frequency multiplexing systems. D/A and A/D converter Data acquisition systems.

5 Design a half subtractor using basic gates. Difference=A B+AB =A B Borrow=A B 6 Draw the logic diagram of a 4 line to 1 line multiplexer. 7. What is priority Encoder? A priority encoder is an encoder circuit that includes the priority function. In priority encoder, if 2 or more inputs are equal to 1 at the same time, the input having the highest priority will take precedence.

8. Write down the difference between demultiplexer and decoder. Definition Characteristic Demultiplexer 1 data input 2^n outputs Connects the data input to the data output Decoder It has n inputs 2^n outputs It has n control inputs Selects one of the 2^n outputs by decoding the binary value on the basis of n inputs Reverse of Multiplexer Encoder 9 Give the logic expression for sum and carry in full adder circuit. SUM = (A B) C IN CARRY = AB+BC IN +A C IN 10 Give examples for combinational circuit. i. Adders ii. Subtractors iii. Multiplexers iv. Demultiplexers v. Encoders vi. Decoders 11 Draw the logic circuit of a 2-bit comparator.[april/may-2015,2014]

12 Suggest a solution to overcome the limitation on the speed of an adder. It is possible to increase speed of adder by eliminating inter-stage carry delay. This method utilizes logic gates to look at the lower-order bits of the augend and addend to see if a higher-order carry is to be generated. 13 Relate carry generate, Carry propagate, Sum and Carry-out of a Carry look a head adder. 14. Realize the Boolean function using appropriate multiplexer F(A,B,C)= Σ (0,1,3,7) 15. Compare the performance of binary serial and parallel adders. Serial Adder: Serial adder uses shift registers The serial adder requires only one full adder circuit The serial adder is a sequential circuit Time required for addition depends on the number of bits It is slower parallel adder: Parallel adder uses registers with parallel load capacity It is faster Time required for addition does not depend on number of bits Excluding the registers, the parallel adder is a purely combinational circuit

16. Construct a two-4-bit parallel adder/subtractor using Full Adders and XOR gates. 17. Convert a two-to-four line decoder with enable input to 1X4 Demultiplexer 18. Draw the logic diagram of serial adder.

UNIT- 3 SYNCHRONOUS SEQUENTIAL CIRCUITS 1. Mention any two differences between the edge triggering and level triggering. Level Triggering: 1) The input signal is sampled when the clock signal is either HIGH or LOW. 2) It is sensitive to Glitches. Example: Latch. Edge Triggering: 1) The input signal is sampled at the RISING EDGE or FALLING EDGE of the clock signal. 2) It is not-sensitive to Glitches. Example: Flipflop. 2. What is meant by programmable counter? Mention its application. A counter that divides an input frequency by a number which can be programmed into decades of synchronous down counters. Decades, with additional decoding and control logic, give the equivalent of a divide-by N counter system, where N can be made equal to any number. Application: Microprocessor. Traffic light controller. Street light controller. 3. Write the characteristic equation of a JK flip-flop. The characteristic equation of a JK flip-flop is given by Q(next) = JQ' + K'Q

4. State the differences between Moore and mealy state machine. 1) Mealy Machines tend to have less states a) Different outputs on arcs (n^2) rather than states (n). 2) Moore Machines are safer to use a) Outputs change at clock edge (always one cycle later). b) In Mealy machines, input change can cause output change as soon as logic is done - A big problem when two machines are interconnected asynchronous feedback. 3) Mealy Machines react faster to inputs b) React in same cycle don't need to wait for clock. c) In Moore machines, more logic may be necessary to decode state into outputs more gate delays after. 5. Realise T-FF from JK-FF. 6. Convert JK flip-flop to T flip-flop.

7. How many flip-flops are required to build a binary counter that counts from 0 to 1023? If the number of flip-flops required is n, then 2 n -1=1023 n=10 since 2 10 =1024 8. Compare the logics of synchronous counter and ripple counter. Asynchronous counter: 1. In this type of counter flipflop are connected in such a way that output of first flip-flop drives the clock for next flip-flop. 2. All the flip-flop are not clocked simultaneously. 3. Logic circuit is very simple even for more number of states. Synchronous counter: 1. In this type there is no connection between output of first flip-flop and clock input of the next flip-flop. 2. All the flip-flop are clocked simultaneously. 3. Design involves complex logic circuit as number of states increases. 9. Sketch the logic diagram of a clocked SR flip-flop. 10. How do you eliminate the race around condition in a JK flip-flop? When the input to the JK flip-flop is j=1 and k=1, the race around condition occurs, i.e it occurs when the time period of the clock pulse is greater than the propagation delay of the flip flop. the output changes or toggles in a single clock period. If it toggles even number of times the output is same but if it toggles odd number of times then the output is complimented. To avoid race around condition we cant make the clock pulse smaller than the propagation delay so we use 1. Master slave JK flip flop 2. Positive or negative edge triggering

11. Draw the state table and excitation table of T flip-flop. 12. A 4-bit binary ripple counter is operated with clock frequency of 1KHz. What is the output frequency of its third Flip flop? The output frequency of third flip-flop is: ½ 3 = 1/8KHz. 13. Realize JK flip-flop using D flip-flop. 14. Design a 3-bit ring counter and find the mod of the designed counter.

15. Define latches. Latch is a simple memory element, which consists of a pair of logic gates with their inputs and outputs inter connected in a feedback arrangement, which permits a single bit to be stored. 16. Draw the block diagram for Moore model. 17. What is synchronous sequential circuit? In synchronous circuits the input are pulses (or levels and pulses) with certain restrictions on pulse width and circuit propagation delay. Therefore synchronous circuits can be divided into clocked sequential circuits and uncklocked or pulsed sequential circuits. In a clocked sequential circuit which has flip-flops or, in some instances, gated latches, for its memory elements there is a (synchronizing) periodic clock connected to the clock inputs of all the memory elements of the circuit, to synchronize all internal changes of state

UNIT- 4 ASYNCHRONOUS SEQUENTIAL CIRCUITS 1. What are hazard free digital circuits? A circuit which has no hazard like static-0-hazard and static-1-hazard is called hazard free digital circuit. 2. What are the two types of asynchronous sequential circuits? Fundamental mode circuit Pulse mode circuit 3. What is state table? The state table representation of a sequential circuit consists of three sections labelled present state, next state and output. The present state designates the state of flip-flops before the occurrence of a clock pulse. The next state shows the states of flip-flops after the clock pulse, and the output section lists the value of the output variables during the present state. 4. What are Hazards? The unwanted switching transients (glitches) that may appear at the output of a circuit are called Hazards. 5. What is a state diagram? Give an example. A state diagram is a type of diagram used in computer science and related fields to describe the behaviour of systems. State diagrams require that the system described is composed of a finite number of states; sometimes, this is indeed the case, while at other times this is a reasonable abstraction. Many forms of state diagrams exist, which differ slightly and have different semantics. 6. Under what circumstances asynchronous circuits are prepared. (i) Fundamental mode asynchronous circuits (ii) Pulse mode asynchronous circuits

7. Differentiate fundamental mode and pulse mode asynchronous sequential circuits. Fundamental mode sequential circuits 1 (i) Memory elements are clocked flip-flops Pulse mode sequential circuits. (i) Memory elements are either unlocked flip - flops or time delay elements. 2 (ii) Easier to design (ii) More difficult to design 8. Write short notes on Hazards. The unwanted switching transients (glitches) that may appear at the output of a circuit are called Hazards. Static-0-Hazard Static-1-Hazard

UNIT - 5 MEMORY DEVICES AND DIGITAL INTEGRATED CIRCUITS 1. What is meant by memory Expansion? Mention its limit. The memory expansion can be achieved in two ways: by expanding word size and expanding memory capacity. Limitations: 1. Memory capacity upto 16Mbytes. 2. 24 address lines and 16 data lines. 2. What are the advantages of static RAM and Dynamic Ram? Static RAM: Access time is less. Fast operation. Dynamic Ram It consumes less power. Cost is low. 3. What is difference between PAL and PLA? PLA: Both AND and OR arrays are programmable and Complex Costlier than PAL PAL: AND arrays are programmable OR arrays are fixed Cheaper and Simpler 3. Implement the exclusive or function using ROM. Can implement multi-input/multi-output logic functions inside of ROM. Data outputs are the logic functions and the address lines are the logic function inputs. We create a ROM Table to store the logic functions. When an input (or address) is presented, the value stored in the specified memory location appears at the data outputs. Each data output represents the correct value for its logic function

4. Compare Dynamic RAM with Static RAM. Static Ram is very costly. Dynamic Ram is cheaper. Static Ram contains Transistors. Dynamic Ram contains Capacitors. Static Ram is used in L1 and L2 cache. Dynamic Ram is used in system RAM. 5. Mention few applications of PLA and PAL. Implement combinational circuits Implement sequential circuits Code converters Microprocessor based systems 6. What are the different types of programmable logic devices? PROM PLA PAL GAL 7. Draw the structure of a static RAM cell.

8. List the advantages of PLDs. low and fixed (two gate) propagation delays (typically down to 5 ns), simple, low-cost (free), Design tools. 9. What is PAL? PAL is programmable array logic, PAL consists of a programmable AND array and a fixed OR array with output logic. 10. What is access time and cycle time of a memory? Access time is the maximum specified time within which a valid new data is put on the data bus after an address is applied. Cycle time is the minimum time for which an address must be held stable on the address bus in read cycle. 11. Implement a 2-bit multiplier using ROM. [Nov/Dec-2010]

12. How the memories are classified? It is classified into two types: volatile non-volatile memory 13. Draw the logic diagram of a static RAM cell and Bipolar cell. 14. What is volatile and non-volatile memory? The memory which cannot hold the data when power is turned off is known as volatile memory. The memory which can hold the data when power is turned off is known as nonvolatile memory 15. Give the advantages of RAM. Read and write the data. Data is accessed by using address of the memory location. Higher speed.

16. Draw an active-high tri-state buffer and write its truth table. Enable Input Output 0 X Z 1 0 0 1 1 1 17. What is a totem pole output? Totem pole output is a standard output of a TTL gate. It is specifically designed to reduce the propagation delay in the circuit and to provide sufficient output power for high fan-out. 18. Draw the TTL Inverter (NOT) Circuit. 19. State the advantages of CMOS logic. Consumes less power. Can be operated at high voltages, resulting in improved noise immunity. Fan-out is more. Better noise margin.

20. Write a note on tri-state gates. It is a digital circuit that exhibits three states. Two of the states are signals equivalent to logic1 and logic 0. The third state is high impedance state. High impedance state behaves like a open circuit. 21. What is the significance of high impedance state in tri-state gates? a. High impedance state of a three-state gate provides a special feature not available in other gates. b. Because of this features a larger number of three state gate output can be connected with wires to form a common line without endangering loading effects. 22. Define the term Fan out. It is the maximum number of inputs which have same family that the gate can drive maintaining its output within the specified limits. 23. Draw the CMOS inverter circuit.

BIG QUESTIONS QUESTION BANK PART B UNIT I DIGITAL FUNDAMENTALS 1. Using K-map simplify the expression Y (A, B, C, D) = m 1 +m 3 +m 5 + m 7 +m 8 +m 9 + m 0 +m 2 +m 10 +m 12 +m 13. Indicate the prime implicants, essential and non-essential prime implicants. Realize the logic circuit using AND-OR-INVERT gates and also by using NAND gates. (16) 2. Obtain the simplified function for the Boolean function Y (A, B, C, D) = m 1 +m 3 +m 5 + m 7 +m 8 +m 9 + m 0 +m 2 +m 10 +m 12 +m 13 using Quine McClusky method. Obtain the NAND and NOR implementation of the simplified expression. (16) 3. Obtain the minimum SOP using Quine McClusky method and verify using K- map F= m0 + m2+m4+m8+m9+m10+m11+m12+m13. (16) 4. Determine the prime implicants of the following function and verify using K-map F(A,B,C,D) = Σ(3,4,5,7,9,13,14,15). (16) 5. Simplify using K-map to obtain a minimum POS expression for the function F = (A + B + C + D) (A + B + C + D) (A + B + C + D ) (A + B + C + D ) (A + B + C + D )(A + B + C + D). (8) 6. Write short notes on i) alphanumeric codes and ii) Error detection and correction methods (6) 7. i. Simplify F (A,B,C,D) = Σm ( 1,3,5,8,9,11,15) + Σd (2,13).If don t care conditions are not taken into care what will be the simplified Boolean function? Write your comments on it. Implement both circuits using logic gates. (12) ii. Add 26 and 39 using Excess-3 code. (4) 8. Simplify using five variable mapping F =(8,9,10,11,13,15,16,18,21,24,25,26,27,30,31) (16) 9. State and prove De - Morgan s theorems using two variables. (6) 10. Realize the functions of NOT, AND, OR and NAND gates only with NOR gates. (8) 11. i. Convert the decimal 65 to BCD, Excess-3 and Gray code (4) ii. Encode data bits 1001 into a seven bit even parity Hamming code. (4) 12. Simplify the following Boolean function in SOP and POS form using K-map F ( A,B,C,D) = Σm( 3,4,9,13,14,15) + Σd ( 2,5,10,12) (8) 13. Simplify the following function using K map and tabular methods. Compare the methods. F ( A,B,C,D) = Σm(4,5,6,7,8) + Σd (11,12,13,14,15).Implement the result using NAND gates. (16)

14. Obtain the minimum SOP using Quine Mc Clusky s method for the function Σm(0,1,2,8,9,15,17,21,24,25,27,31) (7) 15. What are codes? Explain the different codes with examples. (16) 16. Prove the following Boolean identities i) x + xyz + yzx + wx + w x + x y = x + y ii) (X1 + X 2 ) (X1 X 3 + X 3 ) (X 2 + X 1 X 3 ) = X 1 X 2 (6) 17. The state of 12 cell register is 010110010111.What is its contents if it represents a) Three decimal digits in BCD b) Three decimal digits in Excess- 3 code. c) Three decimal digits in 2421 code d) Three decimal digits in 84-2-1 code. (8) 18. Implement the following expression with 2 - input NAND NOT gates. Assume that only true values of the inputs are available = (AB + A B ) (CD + C D).Also use a multiple level implementations to reduce the number of gates. Hint Use a two level AND OR implementation plus NOT gates on the inputs as needed. Then convert to NAND NOT gates. (16) 19. Simplify the following switching function F(A,B,C,D,E) = Σm(1,3,6,10,11,12,14,15,17,19,20,22,24,29,30) (16) 20. i) Perform the following arithmetic using two s complement (+27) + (-61), (-27) + (+61) and (-27) + (-61). (6) ii) Generate the parity bits for 8421 BCD code in an odd parity system. (2) 21. Perform the following using 12 bit two s complement arithmetic i. 8-7 ii. -8-7 iii. - 8+7 (6) 22. Given F = A BE + BCDE + BC D E+ A B DE + B C DE, BE +B DE is the simplified version of the expression. Are there any don t care conditions, if so what are they? (8) 23. Simplify the function F(w,x,y,z) = Σm(2,3,12,13,14,15) using tabulation method. Implement the simplified function using gates. (8) 24. Obtain a four level NAND network for F (A, B, C, D) = (A B + C) D + EF (8) 25. Simplify the function F(w,x,y,z) = Σm(1,4,6,7,8,9,10,11,15) using tabulation method. Implement the simplified function using gates. (8) 26. Explain the term Prime Implicants. Write notes on computer aided minimization procedure. (10) 27. Simplify the five variable switching function F(E,D,C,B,A)=Σm(3,5,6,8,9,12,13,14,19,22,25,30) (16) 28. Determine the Prime Implicants and Essential Prime Implicants of the function F(w,x,y,z) = Σm(1,4,6,7,8,9,10,11,15) using tabulation method. (16)

29. Realise F(A,B,C,D) = Σm(0,3,4,5,8,9,10,14,15) using three input NOR gates. (16) 30. Find the MSP form of F (w, x, y, z) = Σm(1 3, 5-10,12 14) using the Quine Mc Clusky method. (16) 31. Perform the following: i) (-105) 10 + (-120) 10 using ones and twos complement. Comment on the result. ii) Divide 100000110.1 by 101 and perform 100000 0.11 using ones complement, iii) (34) 10 + (19) 10 using excess 3 code. iv) Determine whether single error has occurred and if so, corrects the error using Hamming code, for 1100010. (16) 32. Compare ones complement and twos complement representation of signed binary numbers. (16) 33. Obtain the minimum SOP using Quine MC Clusky s method and using K-map. F = m0+ m2 + m4 + m8 + m9 +m10 + m11 + m12 + m13 (16) 34. Reduce the following using tabulation method. F = m2 + m3 + m4 + m6 + m7 +m9 + m11 + m13. (16) 35. Using Quine Mc Clusky method find all the prime implicants and the minimum SOP for the function F ( a, b, c, d) = Σm(0,4,5,7,8,11,12,15) (16) 36. Convert the decimal number 342.75 to binary, octal and hexa decimal. (6)

UNIT 2 COMBINATIONAL CIRCUIT DESIGN 1. Draw and explain the working of 4 bit adder subtractor circuit. (8) 2. Design a two bit magnitude Comparator (8) 3. The inputs to a circuit are the four bits of the binary number D 3 D 2 D 1 D 0. The circuit produces a one if and only if all of the following conditions hold, i. MSB is 1 or any of the other bits are a 0. ii. D 2 is a 1 or any other bits are a 0. iii. Any of the 4 bits are 0 Obtain a minimal expression for the output. (8) 4. i) Design a Half subtractor using NAND- NAND logic (6) ii) Design a four bit gray to binary code converter. (10) 5. Explain the working of carry look ahead generator (10) 6. A majority gate is a digital circuit whose output is equal to 1 if majority of its inputs are 1 s.the output is 0 otherwise. Using a truth table, find the Boolean function implemented by a 3-input majority gate. Simplify the function and implement it with logic gates. (10) 7. i) Design and implement a full adder circuit using logic gates and also by using half adders. (8) ii. Design a logic circuit to simulate the function f (A, B, C) = A (B + C) by using only NAND gates. (4) iii. Explain with truth table and gate level circuits diagram for a full adder. (12) 8. i. What is a decoder? How is it different from encoder? (6) ii. Implement the following function with a Multiplexer f (a, b, c, d) = Σ ( 0, 1, 3, 4, 8, 9, 15) (10) 9. Using 8 to 1 multiplexer, realize the following Boolean function T = f (w,x,y,z) = Σ (1,1,2,4,5,7,8,9,12,13) (16) 10. i. Implement full adder circuit using, a) Decoder b) Multiplexer (12) ii. How can you convert a decoder into a de-multiplexer? (4) 11. i. Using 8 to 1 multiplexer, realize the Boolean function T = f (w, x, y, z) = Σm (0, 1, 2, 4, 5, 7, 8, 9, 12, 13) (8) ii. Realize the function given in (i) using Decoder and external gates. (8) 12. Implement the function Y (A, B, C, D) = Σm (1, 3, 5, 7, 8, 9, 0, 2, 10, 12, 13) using 4:1MUX. (16)

13. i. Implement the logic function Y(A,B,C) = Σm ( 1, 2, 7) using 74151A and 74153 (8) ii. Implement a 3 to 8 line decoder. (8) 14. Which of the following statements refer to a decoder, encoder, a MUX or a DEMUX? a) Has more inputs than outputs. b) Can be used in parallel to serial conversion. c) Produces a binary code at its output. d) Only one of its outputs can be active at one time. e) Can be used to route an input signal to one of several possible outputs. f) Can be used to generate arbitrary logic functions. (16) 15. Implement the following multiple output combinational logic circuit using a 4 16 line decoder. F 1 = Σm (1, 2, 4, 7, 8, 11, 12, 13) F 2 = Σm (2, 3, 9, 11) F 3 = Σm (10, 12, 13, 14) F 4 = Σm (2, 4, 8) (16) 16. Implement the function Y (A, B, C, D) = Σm (1, 4, 6, 7, 8, 9, 10, 11, 15) using 4:1 MUX (16) 17. Design and explain the working of a 4 x 1 MUX. (8) 18. Explain how a 4 to 16 line decoder can be built using 2 to 4 line decoder. (8) 19. Implement the switching function F (A, B, C) = Σm (1, 2, 4, 5) using the DEMUX 74156. (16) 20. Design the following function F = Σm (0, 1, 3, 5, 6, 8, 10, 13, 14) using a multiplexer and a decoder. (16)

UNIT 3 SYNCHRONOUS SEQUENTIAL CIRCUITS 1. Design a MOD 10 synchronous counter using JK flip-flops. Write the excitation table and state table. (16) 2. i. Compare Moore and Mealy circuits. (4) ii. Draw and explain the block diagram of Mealy circuit. (12) 3. Using SR flip-flops, design a synchronous counter which counts in the sequence 000, 111, 101, 110, 001, 010, 000 (16) 4. Design a mod 5 synchronous counter using JK flip flops with separate logic circuitry for each J and K input. Construct a timing diagram and determine the duty cycle of the output of the most significant stage. (16) 5. Design a synchronous counter using JK flip-flop to count the following sequence 7, 4, 3, 1, 5, 0, 7. (16) 6. Design a sequential circuit with four flip-flops ABCD. The next states of B, C, and D are equal to the present states of A, B, C respectively. The next state of A is equal to the EX- OR of present states of C and D. (16) 7. i. Show that the characteristic equation of Q ( t+1) of JK flip flop is Q (t+1) = J Q + KQ (4) ii. A sequential circuit has one flip-flop Q, two inputs x and y, and one output S. It consists of a full adder circuit connected to a D flip-flop, as shown below. Derive the state table and state diagram of the sequential circuit. (12) 8. i. Reduce the number of states in the following state table and tabulate the reduced state table. (8) Present Next State Output state x = 0 x = 1 x = 0 x = 1 a F b 0 0 b D c 0 0 c F e 0 0 d G a 1 0 e D c 0 0 f F b 1 1 g G h 0 1 h G a 1 0 ii. Starting from state a, and the input sequence 01110010011, determine the output sequence for the given and reduced state stable. (8)

9. Design a synchronous decade counter using D flip flop. (16) 10. i. Explain the working of a master slave JK flip flop. State its advantages. (6) ii. For a four bit even parity bit generator, inputs come serially. The four bits of the input sequence are to be examined by the circuit and circuit produces a parity bit which is to be added in the original sequence. The circuit should get ready for receiving another four bits after producing a parity bit for the last sequence. Draw the state diagram and write down the state transition table. (10) 11. A sequential circuit has four flip-flops ABCD and an input x is describe the following State equations. A (t + 1) = (CD + C D) x + (CD + C D ) x B (t + 1) = A C (t + 1) = B D (t + 1) = C a. Obtain the sequence of states when x = 1 starting from ABCD = 0001 b. Obtain the sequence of states when x = 0 starting from ABCD = 0000 (16) 12. A sequential circuit with 2 D flip-flops A and B and input X and output Y is specified by the following next state and output equations. A (t + 1) = AX + BX B (t + 1) = A X Y = (A + B) X i. Draw the logic diagram of the circuit ii. Derive the state table Iii. Derive the state diagram (16) 13. Design a Mod-14 up-down counter using T flip-flops. (16) 14. Design a mod- 7 counter using JK flip-flops. (16) 15. Design a BCD Up / Down counter using S R flip-flops. (10) 16. Design an asynchronous decade counter using JK flip-flops. (16) 17. Draw a four state switch tail ring counter. Show the count sequence. What is the modification to be used to prevent lock out? (16) 18. Design a synchronous counter with states 0, 1, 2, 3, 0, 1 using JK flip-flops. (16) 19. Write notes on state minimization. (8) 20. Design the clocked sequential circuit using JK flip-flops whose state diagram is given below. (16)

21. What is the use of State reduction? Reduce the state diagram. (10) 22. Design 4 bit synchronous counter using X-OR gate as well as JK Flip-flop to count from 0 to 15. (16) 23. Distinguish between synchronous and asynchronous sequential circuits. (6) 24. Consider the following synchronous sequential circuit. Determine its state table. What does the circuit do? (16) 25. Explain the meaning of Mealy and Moore machines. (6) 26. Show that if a sequential machine is strongly connected, then it is reversible but that the converse is not always true. (10) 27. Design a four state down counter using type T design procedures. (16) 28. Design a 4 bit synchronous 8421 decade counter with ripple carry. (16) 29. Explain the working of JK flip- flop. What is race around condition? How is it overcome? Explain these concepts with relevant timing diagrams. (16) 30. Design a 4 bit up / down counter using JK flip flops and Explain its working with timing diagrams. (16) 31. For the given Moore model sequential circuit, find the state table, state diagram, flips flop input and output equations. (16)

UNIT 4 ASYNCHRONOUS SEQUENTIAL CIRCUITS 1. Develop the state diagram and primitive flow table for a logic system that has two inputs S and R and a single output Q. The device is to be an edge triggered SR flipflop but without a clock. The device changes state on the rising edges of the two inputs. Static input values are not to have any effect in changing the Q output. (16) 2. Design an asynchronous sequential circuit that has two inputs X 2 and X 1 and one output Z. The output is to remain a 0 as long as X 1 is a 0. The first change in X 2 that occurs while X 1 is a 1 will cause a Z to be a 1. Z is to remain a 1 until X 1 returns to 0. Construct a state diagram and flow table. Determine the output equations. (16) 3. Construct the state diagram of a Mealey Pattern detector that can detect a serial string of 4 inputs, where each input is a four bit code. If the string of four bit codes is correctly received, then an output is generated. An incorrect input code pattern is to generate a second output. The second output is to be asserted only after receiving the sequence of four bit codes. (16) 4. An asynchronous sequential circuit has two internal states and one output. The excitation and output functions describing the circuit are Y 1 =x 1 +x 1 y 2 ' +x 2 y 1 Y 2 =x 2 +x 1 y 1 ' y 2 +x 1 y 1 Z= x 2 +y 1 (i) Draw the logic diagram of the circuit. (6) (ii) Derive the transition table and output map. (5) (ii) Obtain a flow table for the circuit. (5) 5. An asynchronous sequential circuit is described by the excitation and output functions Y = x 1 x 2 ' +(x 1 +x 2 ' ) y and Z =y (i) Draw the logic diagram of the circuit with a NOR SR latch. (6) (ii)derive the transition table and output map (5) (iii)obtain a two-state flow table. (5) 6. Define the following: i) asynchronous sequential circuits, ii) Cycles, iii) critical race, iv) non- critical race (8) 7. Draw the state diagram and obtain the primitive flow table for a circuit with two inputs x 1 and x 2 and two outputs z 1 and z 2 that satisfies the following conditions. When x 1 x 2 = 00 output z 1 z 2 = 00, when x 1 = 1 and x 2 changes from 0 to 1 the output z 1 z 2 = 01, when x 2 = 1 and x 1 changes from 0 to 1 the output z 1 z 2 = 10 otherwise output does not change. (16) 8. Design an asynchronous binary toggle circuit that changes state with each rising edge of clock input. Assume the initial output as zero. (16) 9. Write notes on the following giving one example for each. (8) Stable state, unstable state, Cycles, Race

10. Analyze the Boolean expression, K- Map, transition and state table and primitive flow table of the following asynchronous sequential circuits. (16) 11. How will you minimize the number of rows in the primitive state table of an incompletely specified sequential machine? (12) 12. State the restrictions on the pulse width in a pulse mode asynchronous sequential machine. (4)

UNIT 5 MEMORY DEVICES AND DIGITAL INTEGRATED CIRCUITS 1. Draw the circuit diagram and explain the working of TTL inverter with tristate output (8) 2. Explain the concept and implementation of ECL logic family. (8) 3. i) Explain the operation of TTL NAND gate with a neat circuit diagram. (8) ii) Draw the circuit of CMOS NOR gate and explain its operation. Mention any two points about the advantages of CMOS over the other digital logic families. (8) 4. i) Using ROM, design a combinational circuit which accepts 3 bit number and generates an output binary number equivalent to the square of input number. (8) ii) A combinational circuit is defined by the functions F 1 (A, B, C) = m (3, 5, 6, 7), F 2 (A, B, C) = m (0, 2, 4, 7). Implement the circuit using PLA. (8) 5. Discuss the working of the following programmable logic devices: (16) i. PROM ii. FPGA iii. PLD 6. Explain the working of 3 input totem pole TTL NAND gate. (10) 7. Draw a PLA circuit to implement the logic functions A BC + AB C + AC and A B C + BC (6) 8. Compare various digital logic families based on any five suitable parameters (10) 9. Write notes on ROM and its types. (16) 10. Write short notes on TTL, ECL and CMOS digital logic families. (16) 11. Explain EPROM and PLA. (8) 12. Define the terms Fan-out, tri-state gates, Fan-in. (6) 13. Draw the circuits of two input NAND and two input NOR gates using CMOS. (8) 14. Illustrate the ROM and PLA design for the following functions W(A,B,C,D) = Σm(3,7,8,9,11,15) X(A,B,C,D) = Σm(3,4,5,7,10,14,15) Y (A, B, C, D) = Σm (1, 5, 7, 11, 15) (16) 15. Draw and explain the circuit diagram of an ECL OR / NOR gate. (8) 16. Draw a neat sketch showing the implementation of Z1 = ab d e + a b c d e + bc + de Z2 = a c e Z3 = bc + de + c d e + bd and Z4 = a c e + ce using a 5 x 8 x 4 PLA. (12)

17. Generate the following Boolean functions with a PAL with 4 inputs and 4 outputs. Y 3 = A BC D + A BCD + A BCD + ABC D Y 2 = A BCD + A BCD + ABCD Y 1 = A BC + A BC + AB C + ABC Y 0 = ABCD (16) 18. Discuss about the TTL parameters. (10) 19. Draw the TTL inverter circuit. (6) 20. Name and explain the characteristics of TTL logic family. (8) 21. Draw the internal circuits of TTL inverter and AND gate. (8) 22. Discuss the concept of working and applications of the following memories: ROM, EPROM, PLA (16) 23. Explain the characteristics and implementation of the following digital logic families. i. CMOS, ii. ECL (16) 24. Write short notes on memory based design (8) 25. Show a BCD to Gray code converter can be designed using a 16 words X 4 bits ROM. (16)