equential Logic! equential Circuits " imple circuits with feedback " Latches " Edge-triggered flip-flops! Timing Methodologies " Cascading flip-flops for proper operation " Clock skew! Basic egisters " hift registers " Counters equential Circuits! Circuits with Feedback " Outputs = f(inputs, past inputs, past outputs) " Basis for building "memory" into logic circuits " oor combination lock is an example of a sequential circuit # tate is memory # tate is an "output" and an "input" to combinational logic # Combination storage elements are also memory value comparator C C2 C3 multiplexer mux control new equal comb. logic state reset C 5 - pring 27 Lec. #5 equential Logic - equal open/closed C 5 - pring 27 Lec. #5 equential Logic - 2 Circuits with Feedback! How to control feedback? " What stops values from cycling around lessly implest Circuits with Feedback! Two inverters form a static memory cell " Will hold value as long as it has power applied "" X X2 Xn switching network Z Z2 Zn "" "stored value"! How to get a new value into the memory cell? " electively break feedback path " Load new value into cell "remember" "data" "load" "stored value" C 5 - pring 27 Lec. #5 equential Logic - 3 C 5 - pring 27 Lec. #5 equential Logic - 4 Memory with Cross-coupled Gates! Cross-coupled NO gates " imilar to inverter pair, with capability to force output to (reset=) or (set=) '! Cross-coupled NAN gates " imilar to inverter pair, with capability to force output to (reset=) or (set=) Timing Behavior eset Hold et eset et ' ace ' ' ' ' ' \ C 5 - pring 27 Lec. #5 equential Logic - 5 C 5 - pring 27 Lec. #5 equential Logic - 6
tate Behavior of - latch Theoretical - Latch Behavior! Truth table of - latch behavior hold unstable ' ' ' = =! tate iagram " tates: possible values " Transitions: changes based on inputs ' = = = = = = = ' = = = = ' = = = ' possible oscillation between states and ' C 5 - pring 27 Lec. #5 equential Logic - 7 C 5 - pring 27 Lec. #5 equential Logic - 8 Observed - Latch Behavior! Very difficult to observe - latch in the - state " One of or usually changes first! Ambiguously returns to state - or - " A so-called "race condition" " Or non-deterministic transition = = = ' = = = = = ' = = ' = C 5 - pring 27 Lec. #5 equential Logic - 9 = = - Latch Analysis! Break feedback path ' (t) (t+!) hold reset set X not allowed X (t) (t) C 5 - pring 27 Lec. #5 equential Logic - X X characteristic equation (t+!) = + (t) (t+!) Gated - Latch Clocks! Control when and inputs matter " Otherwise, the slightest glitch on or while enable is low could cause change in value stored et ' enable' ' eset '! Used to keep time " Wait long enough for inputs (' and ') to settle " Then allow to have effect on value stored! Clocks are regular periodic signals " Period (time between ticks) " uty-cycle (time is high between ticks - expressed as % of period) duty cycle (in this case, 5%) ' ' enable' ' period C 5 - pring 27 Lec. #5 equential Logic - C 5 - pring 27 Lec. #5 equential Logic - 2
Clocks (cont d)! Controlling an - latch with a " Can't let and change while is active (allowing and to pass) " Only have half of period for signal changes to propagate " ignals must be stable for the other half of period ' Cascading Latches! Connect output of one latch to input of another! How to stop changes from racing through chain? " Need to control flow of data from one latch to the next " Advance from one latch per period " Worry about logic between latches (arrows) that is too fast ' ' ' stable changing stable changing stable ' and ' ' ' C 5 - pring 27 Lec. #5 equential Logic - 3 C 5 - pring 27 Lec. #5 equential Logic - 4 Master-lave tructure! Break flow by alternating s (like an air-lock) " Use positive to latch inputs into one - latch " Use negative to change outputs with another - latch! View pair as one basic unit " master-slave flip-flop " twice as much logic " output changes a few gate delays after the falling edge of but does not affect any cascaded flip-flops master stage P' ' P C 5 - pring 27 Lec. #5 equential Logic - 5 slave stage ' The s Catching Problem! In first - stage of master-slave FF " -- glitch on or while is high "caught" by master stage " Leads to constraints on logic to be hazard-free P P' ' et eset s catch Master Outputs lave Outputs master stage P' ' C 5 - pring 27 Lec. #5 equential Logic - 6 P slave stage ' Flip-Flop Edge-Triggered Flip-Flops! Make and complements of each other " Eliminates s catching problem " Can't just hold previous value (must have new value ready every period) " Value of just before goes low is what is stored in flipflop " Can make - flip-flop by adding logic to make = + ' master stage P' ' P C 5 - pring 27 Lec. #5 equential Logic - 7 slave stage ' ' gates Clk=! More efficient solution: only 6 gates " sensitive to inputs only near edge of signal (not while high) holds ' when goes low C 5 - pring 27 Lec. #5 equential Logic - 8 holds when goes low negative edge-triggered flip-flop (-FF) 4-5 gate delays must respect setup and hold time constraints to successfully capture input characteristic equation (t+) =
Edge-Triggered Flip-Flops (cont d) Edge-Triggered Flip-Flops (cont d)! tep-by-step analysis! =, Clk High Act as inverters Clk= Clk= Clk= Hold state new new # old when goes high-to-low when is low data is latched data is held C 5 - pring 27 Lec. #5 equential Logic - 9 C 5 - pring 27 Lec. #5 equential Logic - 2 Edge-Triggered Flip-Flops (cont d) Edge-Triggered Flip-Flops (cont d)! =, Clk High " "! =, Clk LOW Act as inverters Clk= " C 5 - pring 27 Lec. #5 equential Logic - 2 " Clk= " C 5 - pring 27 Lec. #5 equential Logic - 22 " " Edge-Triggered Flip-Flops (cont d)! Positive edge-triggered " Inputs sampled on rising edge; outputs change after rising edge! Negative edge-triggered flip-flops " Inputs sampled on falling edge; outputs change after falling edge Negative Edge Trigger FF in Verilog module d_ff (q, q_bar, data, clk); input data, clk; output q, q_bar; reg q; assign q_bar = ~q; pos pos' neg neg' positive edge-triggered FF negative edge-triggered FF always @(negedge clk) q <= data; C 5 - pring 27 Lec. #5 equential Logic - 23 C 5 - pring 27 Lec. #5 equential Logic - 24
Announcements! Cancel Lab ection Tu -2 PM starting next week " Young assigned to Th 5-8 PM lab " Allen assigned to W 5-8 PM lab (3 TAs!)! Homework #2 Bug " Problem 7(b) revised and posted to the web! tarting Thursday, lecture meets in 59 Mulford Timing Methodologies! ules for interconnecting components and s " Guarantee proper operation of system when strictly followed! Approach deps on building blocks used for memory elements " Focus on systems with edge-triggered flip-flops # Found in programmable logic devices " Many custom integrated circuits focus on level-sensitive latches! Basic rules for correct timing: " () Correct inputs, with respect to time, are provided to the flip-flops " (2) No flip-flop changes state more than once per ing event C 5 - pring 27 Lec. #5 equential Logic - 25 C 5 - pring 27 Lec. #5 equential Logic - 26 Timing Methodologies (cont d) Comparison of Latches and Flip-Flops! efinition of terms " : periodic event, causes state of memory element to change; can be rising or falling edge, or high or low level " setup time: minimum time before the ing event by which the input must be stable (Tsu) " hold time: minimum time after the ing event until which the input must remain stable (Th) positive edge-triggered flip-flop input T su T h data G edge latch there is a timing "window" stable changing around the ing event data during which the input must remain stable and unchanged in order to be recognized C 5 - pring 27 Lec. #5 equential Logic - 27 transparent (level-sensitive) latch behavior is the same unless input changes while the is high C 5 - pring 27 Lec. #5 equential Logic - 28 Comparison of Latches and Flip-Flops (cont d) Type When inputs are sampled When output is valid uned always propagation delay from input change latch level-sensitive high propagation delay from input change latch (Tsu/Th around falling or edge (whichever is later) edge of ) master-slave high propagation delay from falling edge flip-flop (Tsu/Th around falling of edge of ) negative hi-to-lo transition propagation delay from falling edge edge-triggered (Tsu/Th around falling of flip-flop edge of ) Typical Timing pecifications! Positive edge-triggered flip-flop " etup and hold times " Minimum width " Propagation delays (low to high, high to low, max and typical) Tsu 2ns Th 5ns Tw 25ns Tplh 25ns 3ns Tsu 2ns Th 5ns Tphl 4ns 25ns all measurements are made from the ing event that is, the rising edge of the C 5 - pring 27 Lec. #5 equential Logic - 29 C 5 - pring 27 Lec. #5 equential Logic - 3
Cascading Edge-triggered Flip-Flops! hift register " New value goes into first stage " While previous value of first stage goes into second stage " Consider setup/hold/propagation delays (prop must be > hold) Cascading Edge-triggered Flip-Flops! hift register " New value goes into first stage " While previous value of first stage goes into second stage " Consider setup/hold/propagation delays (prop must be > hold) OUT OUT elay Clk C 5 - pring 27 Lec. #5 equential Logic - 3 Clk C 5 - pring 27 Lec. #5 equential Logic - 32 Cascading Edge-triggered Flip-Flops (cont d)! Why this works " Propagation delays exceed hold times " Clock width constraint exceeds setup time " This guarantees following stage will latch current value before it changes to new value In T su 4ns T h 2ns T p 3ns T su 4ns T h 2ns T p 3ns C 5 - pring 27 Lec. #5 equential Logic - 33 timing constraints guarantee proper operation of cascaded components assumes infinitely fast distribution of the Clock kew! The problem " Correct behavior assumes next state of all storage elements determined by all storage elements at the same time " ifficult in high-performance systems because time for to arrive at flip-flop is comparable to delays through logic (and will soon become greater than logic delay) " Effect of skew on cascaded flip-flops: In original state: =, =, = due to skew, next state becomes: =, =, and not =, = C 5 - pring 27 Lec. #5 equential Logic - 34 is a delayed version of ummary of Latches and Flip-Flops! evelopment of -FF " Level-sensitive used in custom integrated circuits # can be made with 4 switches " Edge-triggered used in programmable logic devices " Good choice for data storage register! Historically J-K FF was popular but now never used " imilar to - but with - being used to toggle output (complement state) " Good in days of TTL/I (more complex input function: = J' + K' " Not a good choice for PLAs as it requires two inputs " Can always be implemented using -FF! Preset and clear inputs are highly desirable on flip-flops " Used at start-up or to reset system to a known state Flip-Flop Features! eset (set state to ): " ynchronous: new = ' old (when next edge arrives) " Asynchronous: doesn't wait for, quick but dangerous! Preset or set (set state to : (or sometimes P) " ynchronous: new = old + (when next edge arrives) " Asynchronous: doesn't wait for, quick but dangerous! Both reset and preset " new = ' old + (set-dominant) " new = ' old + ' (reset-dominant)! elective input capability (input enable/load): L or EN " Multiplexer at input: new = L' + L old " Load may/may not override reset/set (usually / have priority)! Complementary outputs:! and ' C 5 - pring 27 Lec. #5 equential Logic - 35 C 5 - pring 27 Lec. #5 equential Logic - 36
egisters! Collections of flip-flops with similar controls and logic " tored values somehow related (e.g., form binary value) " hare, reset, and set lines " imilar logic at each stage! Examples " hift registers " Counters "" OUT OUT2 OUT3 OUT4 hift egister! Holds samples of input " tore last 4 input values in sequence " 4-bit shift register: OUT OUT2 OUT3 OUT4 2 3 4 C 5 - pring 27 Lec. #5 equential Logic - 37 C 5 - pring 27 Lec. #5 equential Logic - 38 hift egister Verilog module shift_reg (out4, out3, out2, out, in, clk); output out4, out3, out2, out; input in, clk; reg out4, out3, out2, out; always @(posedge clk) out4 <= out3; out3 <= out2; out2 <= out; out <= in; hift egister Verilog module shift_reg (out, in, clk); output [4:] out; input in, clk; reg [4:] out; always @(posedge clk) out <= {out[3:], in}; C 5 - pring 27 Lec. #5 equential Logic - 39 C 5 - pring 27 Lec. #5 equential Logic - 4 Universal hift egister esign of Universal hift egister! Holds 4 values " erial or parallel inputs " erial or parallel outputs " Permits shift left or right " hift in new values from left or right left_in left_out clear s s output input right_out right_in clear sets the register contents and output to s and s determine the shift function s s function hold state shift right shift left load new input! Consider one of the four flip-flops " New value at next cycle: clear s s new value output output value of FF to left (shift right) output value of FF to right (shift left) input to N-th cell [N-] (left) Nth cell CLEA s and s 2 3 control mux Input[N] to N+th cell [N+] (right) C 5 - pring 27 Lec. #5 equential Logic - 4 C 5 - pring 27 Lec. #5 equential Logic - 42
Universal hift egister Verilog module univ_shift (out, lo, ro, in, li, ri, s, clr, clk); output [3:] out; output lo, ro; input [3:] in; input [:] s; input li, ri, clr, clk; reg [3:] out; hift egister Application! Parallel-to-serial conversion for serial transmission parallel outputs assign lo = out[3]; assign ro = out[]; always @(posedge clk or clr) if (clr) out <= ; else case (s) 3: out <= in; 2: out <= {out[2:], ri}; : out <= {li, out[3:]}; : out <= out; case parallel inputs serial transmission C 5 - pring 27 Lec. #5 equential Logic - 43 C 5 - pring 27 Lec. #5 equential Logic - 44 Pattern ecognizer! Combinational function of input samples " In this case, recognizing the pattern on the single input signal Counters! equences through a fixed set of patterns " In this case,,,, " If one of the patterns is its initial state (by loading or set/reset) OUT OUT2 OUT3 OUT4 OUT OUT2 OUT3 OUT4 OUT! Mobius (or Johnson) counter " In this case,,,,,,,, OUT OUT2 OUT3 OUT4 C 5 - pring 27 Lec. #5 equential Logic - 45 C 5 - pring 27 Lec. #5 equential Logic - 46 Binary Counter! Logic between registers (not just multiplexer) " XO decides when bit should be toggled " Always for low-order bit, only when first bit is true for second bit, and so on Binary Counter Verilog module shift_reg (out4, out3, out2, out, clk); output out4, out3, out2, out; input in, clk; reg out4, out3, out2, out; "" OUT OUT2 OUT3 OUT4 always @(posedge clk) out4 <= (out & out2 & out3) ^ out4; out3 <= (out & out2) ^ out3; out2 <= out ^ out2; out <= out ^ b ; C 5 - pring 27 Lec. #5 equential Logic - 47 C 5 - pring 27 Lec. #5 equential Logic - 48
Binary Counter Verilog module shift_reg (out4, out3, out2, out, clk); output [4:] out; input in, clk; reg [4:] out; always @(posedge clk) out <= out + ; Four-bit Binary ynchronous Up-Counter! tandard component with many applications " Positive edge-triggered FFs w/ sync load and clear inputs " Parallel load data from, C, B, A " Enable inputs: must be asserted to enable counting " CO: ripple-carry out used for cascading counters # high when counter is in its highest state # implemented using an AN gate (2) CO goes high (3) High order 4-bits are incremented () Low order 4-bits = EN C B A LOA CL CO C B A C 5 - pring 27 Lec. #5 equential Logic - 49 C 5 - pring 27 Lec. #5 equential Logic - 5 Offset Counters equential Logic ummary! tarting offset counters use of synchronous load " e.g.,,,,,,,,,,,...! Ending offset counter comparator for ing value " e.g.,,,,...,,,! Combinations of the above (start and stop value) C 5 - pring 27 Lec. #5 equential Logic - 5 "" "" "" "" "" "" "" "" "" "" "" EN C B A LOA CL EN C B A LOA CL CO C B A CO C B A! Fundamental building block of circuits with state " Latch and flip-flop " - latch, - master/slave, master/slave, edge-triggered FF! Timing methodologies " Use of s " Cascaded FFs work because prop delays exceed hold times " Beware of skew! Basic registers " hift registers " Pattern detectors " Counters C 5 - pring 27 Lec. #5 equential Logic - 52