Vivekananda College of Engineering and Technology Puttur (D.K)

Vivekananda College of Engineering and Technology Puttur (D.K) Analog and Digital Electronics Laboratory Manual 5CSL 37 Author Prof. Mahesh Prasanna K Assoc. Professor & Head, CSE kmpshastry@gmail.com

Directions to use PSPICE: Go to: Start Programs Cadence OrCAD Capture CIS Select: File New Project (Enter the Project name, and select Analog or Mixed A/D) Select: Place Part ( select the required components) Select: Place Wire ( connect the components using wire) Select: Place Ground (to ground the circuit) Select: PSPice New simulation ( create a new simulation profile) Set the 'Run to time' as t= / f (f= frequency of input waveform) Set the 'Maximum step size' as: 0.000m Check the 'Skip the Initial Transients bias point calculation' box Select: PSPice Run Introduction to Xilinx Xilinx is one of most popular software tool used to synthesize VHDL/Verilog code. This tool includes many steps. To make user feel comfortable with the tool the steps are given below: Double click on Project navigator. (Assumed icon is present on desktop). Select NEW PROJECT in FILE MENU. Enter following details in New Project Wizard Create New Project window Project name : PANNA Project location : C:\Xilinx\PANNA Top-Level source type : HDL Click Next. Enter following details in New Project Wizard Device Properties window Product Category : All Device family : Spartan3 Device : XC3S200 Package : FT256 Speed :-4 Top-Level Source Type : HDL Synthesis Tool : XST (VHDL/Verilog) Simulator : ISE Simulator (VHDL/Verilog) Preferred Language : Verilog Enable Enhanced Design Summary and Click Next for three times and finally Click Finish. In Sources window Right Click on xc3s200-4ft256, select New Source Enter the following details in New Source Wizard Select Source Type window File name : and_gate

Location : C:\Xilinx\PANNA Select Verilog Module Enable Add to project and Click Next. Enter the following details in New Source Wizard Define Module window a select as in b select as in c select as out Click Next. Check the Summary and Click Finish. Now, and_gate.vhd file is created. Enter the code as c <= a and b; Click on Save all. Go to Sources for > Synthesis/Implementation. Select and_gate in Sources window. Go to Processes window: Click on + against Synthesize XST. Double click on Check Syntax. Double click on View Technology Schematic to see Truth-Table & k-map; and close that window. Double click on View RTL Schematic to see the Gate; and close that window. In Sources window, Right Click on and_gate.vhd, select New Source Enter the following details in New Source Wizard Select Source Type window Select Test Bench Waveform File name : and_gate_bench Location: C :\Xilinx\PANNA Enable Add to project and Click Next. In New Source Wizard Associate Source window, - associate and_gate file and Click Next; and finally Click Finish. Enter the following in Initial Timing and Clock Wizard Initialize Time window Select Global Signal as (GSR) FPGA High for initial 00 ns. Clock Information: Select Combinational (or internal clock) Check outputs 50 ns After Inputs are Assigned. Assign Inputs 50 ns After Outputs are Checked. Initial Length of Test Bench: 000 ns Time Scale: ns Click Finish. Set input waveforms and Save all. Go to Sources for > Behavioral Simulation. Verify that and_gate_bench.tbw is selected in the Sources window. Go to Processes window: Click on + against Xilinx ISE Simulator and Double Click Simulator Behavioral Model. Check the output waveform.

7. CONTENTS: Expt Title of the Experiments No. a) Design and construct a Schmitt trigger using Op-Amp for given UTP and LTP values and demonstrate its working. b) Design and implement a Schmitt trigger using Op-Amp using a simulation package for two sets of UTP and LTP values and demonstrate its working. a) Design and construct a rectangular waveform generator (Op-Amp relaxation oscillator) for given frequency and demonstrate its working. 2 b) Design and implement a rectangular waveform generator (Op-Amp relaxation oscillator) using a simulation package and demonstrate the change in frequency when all resistor values are doubled. Design and implement an Astable multivibrator circuit using 555 timer for a given frequency 3 and duty cycle. Design and implement Half adder, Full Adder, Half Subtractor, Full Subtractor using basic 4 gates. a)given a 4-variable logic expression, simplify it using Entered Variable Map and realize the simplified logic expression using 8: multiplexer IC. 5 b) Design and develop the Verilog /VHDL code for an 8: multiplexer. Simulate and verify its working. Design and implement code converter I)Binary to Gray II) Gray to Binary Code using basic 6 gates. Design and verify the Truth Table of 3-bit Parity Generator and 4-bit Parity Checker using 7 basic Logic Gates with an even parity bit. a) Realize a J-K Master / Slave Flip-Flop using NAND gates and verify its truth table. 8 b) Design and develop the Verilog / VHDL code for D Flip-Flop with positive-edge triggering. Simulate and verify its working. a) Design and implement a mod-n (n<8) synchronous up counter using J-K Flip-Flop ICs and demonstrate its working. 9 b) Design and develop the Verilog / VHDL code for mod-8 up counter. Simulate and verify its working. Design and implement an asynchronous counter using decade counter IC to count up from 0 to 0 n (n<=9) and demonstrate on 7-segment display (using IC-7447). Generate a Ramp output waveform using DAC0800 (Inputs are given to DAC through IC74393 dual 4-bit binary counter). 2 Open ended experiment : To study 4-bit ALU using IC-748. EXPERIMENTS. EXPERIMENT NO: 0 2. TITLE: SCHMITT TRIGGER 3. LEARNING OBJECTIVES: To learn about the Op-Amp based Schmitt trigger circuit and understand its working. To learn simulation of Op-Amp based Schmitt trigger circuit. 4. AIM: To design and implement an inverting Schmitt trigger using Op-Amp for a given UTP and LTP values.. To implement a Schmitt trigger using Op-amp using a simulation package for two sets of UTP and LTP values. 5. MATERIAL / EQUIPMENT REQUIRED: S. No Components/Equipments Specification/No Quantity Op-Amp ua74 2 Resistor 0K

K 2 3 DC Regulated Power Supply - 4 Signal Generator - 5 CRO - 6. THEORY / HYPOTHESIS: Schmitt Trigger converts an irregular shaped waveform to a square wave or pulse. Here, the input voltage triggers the output voltage every time it exceeds certain voltage levels called the upper threshold voltage VUTP and lower threshold voltage VLTP. The input voltage is applied to the inverting input. Because the feedback voltage is aiding the input voltage, the feedback is positive. A comparator using positive feedback is usually called a Schmitt Trigger. Schmitt Trigger is used as a squaring circuit, in digital circuitry, amplitude comparator, etc. 7. PROCEDURE / PROGRAMME / ACTIVITY:. Test all the components. 2. Rig up the circuit according to the circuit diagram. 3. Apply VCC =2V, VEE = -2V. 4. Apply a sinusoidal signal of peak voltage say 5V, with a frequency of 500Hz. 5. Observe the rectangular output on the CRO, measure the UTP and LTP values, compare them with the design values. 6. Keep the CRO in X-Y mode (Vin to X-channel, Vout to Y-channel). Observe the transfer curve which is called the Hysteresis curve. 8. BLOCK / CIRCUIT / MODEL DIAGRAM / REACTION EQUATION: a) Hardware Implementation

b) Simulation Case : UTP = V, LTP = V Case 2: UTP = V, LTP = V 9. OBSERVATION TABLE / LOOKUP TABLE / TRUTH TABLE: a). Vin-p = V 2. Input period T = ms 3. UTP = V

4. LTP = V 5. +Vsat = V 6. Vsat = V b) Case : UTP= V, LTP= V Case 2: UTP = V, LTP = 0. FORMULA / CALCULATIONS: UTP(Upper Trip Point) is the point in the raising part of input waveform, at which the output voltage changes state. LTP (Lower Trip Point) is the point in the falling part of the input waveform, at which the output changes state. The above state change of output occurs when the input voltage crosses Vref UTP = BVsat LTP = -BVsat Where B is called the feedback fraction. It is the part of the output voltage fed back to the input (pin 3) B = R2/ (R+R2)(by potential divider principle) +Vsat : It is the output voltage. Ideally it is either +Vcc or VEE respectively. (Practically it will be a little less than this value) Let us design an inverting Schmitt trigger for a UTP =+V and LTP = -V Let VCC = +2V (= +Vsat) VEE= -2V (= -Vsat), R2 =K We know UTP = +BVsat, ie V= (R2 /(R + R2))2V ie = K/ (R + K )* 2 R + K =2K R=2K -K = K The above design will set an LTP = -V. GRAPHS / OUTPUTS: 2. RESULTS & CONCLUSIONS: a)the difference between UTP and LTP is defined as Hysteresis is: H=UTP LTP = V V = V 3. LEARNING OUTCOMES : Hence from this experiment we can conclude that Opamp Schmitt trigger circuit converts sine wave to square wave for a given threshold voltage. Simulation results of Op Amp Schmitt trigger circuit matches with practical values. 4. APPLICATION AREAS: Function Generator. Noise immunity and Oscillator.

5. REMARKS:. EXPERIMENT NO: 2 2. TITLE: RELAXATION OSCILLATOR 3. LEARNING OBJECTIVES: To learn about the rectangular waveform generator circuit and understand its working. To learn to implement a rectangular waveform generator using a simulation package. 4. AIM: To design and implement a rectangular waveform generator(op-amp relaxation oscillator) for a given frequency. To implement a rectangular waveform generator (Op-amp relaxation oscillator) using a simulation package, and observe the change in frequency when all the resistors values are doubled 5. MATERIAL / EQUIPMENT REQUIRED: S. No Components/Equipments Specification/No Quantity Op-Amp ua74 2 Resistor K,0K,.8K each 3 Capacitor 0.u 4 Regulated Power Supply - 2 5 CRO - 6. THEORY / HYPOTHESIS: As the name indicates, here there is no input signal, but circuit produces a square wave output that swings between +Vsat and Vsat. The capacitor charges through the feedback resistor R, exponentially towards +Vsat. But capacitor voltage never reaches +Vsat because the voltage crosses the UTP. When this happens the output wave switches to Vsat. With the output now in negative saturation, the capacitor discharges. When the capacitor voltage crosses through zero, the capacitor starts charging negatively toward Vsat.When the capacitor voltage crosses the LTP, output switches back to +Vsat. The above events repeat, resulting in rectangular output. 7. PROCEDURE / PROGRAMME / ACTIVITY:. Check all the components 2. Rig-up the circuit according to the circuit diagram. 3. Apply +Vcc of say 5V and VEE of -5V. 4. Connect the CRO channel- across the capacitor and channel-2 across the output. 5. Observe the output rectangular waveform and capacitor waveform. 6.Calculate the period of the waveform, T. 7. Note down the out put voltage (+Vsat and Vsat) and UTP and LTP voltages. (Observed Vsat will be < +Vcc and - Vsat < -VEE ) 8. Draw the graph of the output waveform and the capacitor voltage waveform.

8. BLOCK / CIRCUIT / MODEL DIAGRAM / REACTION EQUATION: a) Hardware Implementation b) Simulation Case : for the original circuit Case 2: Circuit with all resistors doubled

9. OBSERVATION TABLE / LOOKUP TABLE / TRUTH TABLE: a) i) Period, T = ms ii) +Vsat = V iii) -Vsat = V iv) UTP = + V v) LTP = V b) Case : Period of the output waveform = ms Frequency f = Hz Case 2: With all resistors doubled: Period of the output waveform = ms Frequency f = Hz 0. FORMULA / CALCULATIONS:

. The output is a rectangular wave with a duty cycle of 50 %. (i.e., high duration = low duration). The period of the output wave is given by, Let us choose R=.8KΩ. The maximum voltage across the capacitor is the UTP and minimum voltage across the capacitor is the LTP. UTP = +BVsat and LTP = -BVsat The output waveform swings between +Vsat and Vsat). GRAPHS / OUTPUTS: 2. RESULTS & CONCLUSIONS: Frequency of output waveform =/T = Hz Frequency of output waveform in simulation=/t = Hz 3. LEARNING OUTCOMES : From this experiment we can conclude that relaxation oscillator can be used to generate rectangular waveforms of desired frequency. Relaxation oscillator circuit can be simulated using PSPICE simulator and the results are matching with the practical values. 4. APPLICATION AREAS: Voltage controlled oscillators (VCOs)

Switching power supplies. Dual-slope analog to digital converters. function generators. 5. REMARKS:. EXPERIMENT NO: 03 2. TITLE: ASTABLE MULTIVIBRATOR 3. LEARNING OBJECTIVES: To learn about the astable multivibrator circuit using 555 timer for a given frequency and duty cycle. 4. AIM: To design and implement an Astable multivibrator using 555 timer, for a given frequency and duty cycle. 5. MATERIAL / EQUIPMENT REQUIRED: S. No Components/Equipments Specification/No Quantity Timer NE 555 2 Resistor 3.3K, 6.8K each 3 Capacitor 0.u, 0.0u each 4 DC Regulated Power Supply - 5 CRO - 6. THEORY / HYPOTHESIS: Multivibrator is a form of oscillator, which has a non-sinusoidal output. The output waveform is rectangular. When 555 timer is used as astable multivibrator, it has no stable states, which means it cannot remain indefinitely in either state. This results in rectangular output. The multivibrators are classified as: Astable or free running Multivibrator: It alternates automatically between two states (low and high for a rectangular output) and remains in each state for a time dependent upon the circuit constants. It is just an oscillator as it requires no external pulse for its operation. Monostable or one shot Multivibrator: It has one stable state and one quasi stable state. The application of an input pulse triggers the circuit time constants. After a period of time determined by the time constant, the circuit returns to its initial stable state. The process is repeated upon the application of each trigger pulse. Bistable Multivibrators on other hand have both stable states. It requires the application of an external triggering pulse to change the output from one state to other. After the output has changed its state, it remains in that state until the application of next trigger pulse. 7. PROCEDURE / PROGRAMME / ACTIVITY:. All the components are tested. 2. Circuit is rigged up according to the circuit diagram. 3. Connect CRO-CH to pin no.6 (or 2) and CH2 to pin no.3 (Vout) of the 555. 4. Apply a Vcc of +0V. 5. Observe the capacitor voltage waveform at pin no.6. Observe the output waveform at pin no.3. 6. Note down the period, pulse width, UTP, LTP and VH values.

8. 7. Plot the graph of output waveform and capacitor voltage waveform. (UTP= 2/3 Vcc, LTP = /3 Vcc, as per theory) BLOCK / CIRCUIT / MODEL DIAGRAM / REACTION EQUATION: 9. OBSERVATION TABLE / LOOKUP TABLE / TRUTH TABLE:. 2. 3. 3. 4. 5. 6. Period,T = ms Therefore frequency, f = Hz Pulse width, W = ms Duty cycle, D = W/T = % UTP = V LTP= V High level of output, VH = Volts. (Low level is zero volts). 0. FORMULA / CALCULATIONS: When 555 timer IC is connected to run as an Astable multivibrator, it gives rectangular output. Let T be the period of the output waveform. Then duration of T during which output is high,

. GRAPHS / OUTPUTS: 2. RESULTS & CONCLUSIONS: The various values are as expected. Frequency of output waveform = Hz. Duty cycle = % 3. LEARNING OUTCOMES : From this experiment we can conclude that square waveforms of desired frequency can be generated using 555 timer based astable multivibrator. 4. APPLICATION AREAS: Multivibrator. Embedded Applications. 5. REMARKS:. EXPERIMENT NO: 04 2. TITLE: ADDERS AND SUBTRACTORS 3. LEARNING OBJECTIVES: To realize the half adder circuits using basic gates. To realize the half substractor circuits using basic gates.

To realize the full adder circuits using basic gates. To realize the full substractor circuits using basic gates. 4. AIM: To realize Half Adder and Full Adder using Basic gates. To realize Half Substractor and Full Substractor using Basic gates. 5. MATERIAL / EQUIPMENT REQUIRED: IC7404,7408,7432. Patch Cords, IC Trainer Kit. 6. THEORY / HYPOTHESIS: Adder circuit is a combinational digital circuit that is used for adding two numbers. A typical adder circuit produces a sum bit (denoted by S) and a carry bit (denoted by C) as the output. Adder circuits are of two types: Half adder ad Full adder. Half-Adder: A combinational logic circuit that performs the addition of two data bits, A and B, is called a half-adder. Addition will result in two output bits; one of which is the sum bit, S, and the other is the carry bit, C. Full-Adder: The half-adder does not take the carry bit from its previous stage into account. This carry bit from its previous stage is called carry-in bit. A combinational logic circuit that adds two data bits, A and B, and a carry-in bit, Cin, is called a full-adder. Subtractor is the one which used to subtract two binary number(digit) and provides Difference and Borrow as a output.in digital electronics we have two types of subtractor. Half Subtractor and Full Subtractor. Half Subtractor :Half Subtractor is used for subtracting one single bit binary digit from another single bit binary digit. Full Subtractor : A logic Circuit Which is used for Subtracting Three Single bit Binary digit is known as Full Subtractor.Adder circuit is a combinational digital circuit that is used for adding two numbers. A typical adder circuit produces a sum bit (denoted by S) and a carry bit (denoted by C) as the output. Adder circuits are of two types: Half adder ad Full adder. Half-Adder: A combinational logic circuit that performs the addition of two data bits, A and B, is called a half-adder. Addition will result in two output bits; one of which is the sum bit, S, and the other is the carry bit, C. Full-Adder: The half-adder does not take the carry bit from its previous stage into account. This carry bit from its previous stage is called carry-in bit. A combinational logic circuit that adds two data bits, A and B, and a carry-in bit, Cin, is called a full-adder. Subtractor is the one which used to subtract two binary number(digit) and provides Difference and Borrow as a output.in digital electronics we have two types of subtractor. Half Subtractor and Full Subtractor. Half Subtractor :Half Subtractor is used for subtracting one single bit binary digit from another single bit binary digit. Full Subtractor : A logic Circuit Which is used for Subtracting Three Single bit Binary digit is known as Full Subtractor. 7. PROCEDURE / PROGRAMME / ACTIVITY: Make connections as shown in the circuit diagram. Verify the Truth Table and observe the outputs. 8. BLOCK / CIRCUIT / MODEL DIAGRAM / REACTION EQUATION: IC 7404 PIN DIAGRAM

IC 7408 PIN DIAGRAM IC 7432 PIN DIAGRAM IC 74 PIN DIAGRAM Half Adder Half subtractor Full Adder Full Subtractor

9. OBSERVATION TABLE / LOOKUP TABLE / TRUTH TABLE: Difference=a b+a b Borrow = a b Sum = a b c + a b c + a b c + a b c Carry = A B + A C + B C

Difference = a b c + a b c + a b c + a b c Borrow = a c + a b + b c 0. FORMULA / CALCULATIONS: N/A. GRAPHS / OUTPUTS: N/A 2. RESULTS & CONCLUSIONS: The truth table of half adder, half subtractor, full adder and full subtractor is verified. 3. LEARNING OUTCOMES : Students will be able to design half adder, half subtractor, full adder and full subtractor using basic gates. 4. APPLICATION AREAS: Used in the design of ripple counters. Half adders can be used to design full adders. 5. REMARKS:. EXPERIMENT NO: 05 2. TITLE: EVM & 8: MUX 3. LEARNING OBJECTIVES: To learn about various applications of multiplexer. To learn and understand the working of IC 745. To learn to realize any function using Multiplexer. To develop a Verilog code for an 8: Multiplexer using dataflow modeling in Xilinx simulator. 4. AIM: To simplify 4 variable logic expression, simplify it using Entered Variable Map and realize the simplified logic expression using 8: Multiplexer IC. To develop the Verilog / VHDL code for an 8: multiplexer, simulate and verify its working. 5. MATERIAL / EQUIPMENT REQUIRED: IC 745, IC 7404 Patch Cords & IC Trainer Kit PC with Windows XP, XILINX software. 6. THEORY / HYPOTHESIS:

Multiplexer means many into one. A multiplexer is a circuit with many inputs, but only one output. By using control signals, we can connect any input to the output. Hence, it is also known as Data Selector. Map Entered Variable Rules for entering values in a MEV K-map: 7. PROCEDURE / PROGRAMME / ACTIVITY: Rule No. 2 3 4 5 6 7 8. 9 MEV f Entry in MEV Map 0 0 0 0 0 0 0 MEV ------ 0 MEV 0 - - 0-0 0 0 0-0 - 0 - Comments If function equals 0 for both values of MEV, enter 0 0 0 in appropriate cell of MEV Map. If function equals for both values of MEV, enter. If function equals MEV enter MEV If the function is compliment of MEV, enter MEV. If function equals don't care for both values of MEV, enter. Iff = 0 for MEV= 0 and f=0 for MEV=, enter 0. Iff = 0 for MEV= 0 and f=- for MEV=l, enter 0. Iff = for MEV= 0 and f= for MEV=, enter. Iff = for MEV= 0 and f=- for MEV=, enter. Assume that the following 4-variable Boolean function is to be implemented using 8: multiplexer IC 745. Y = F(A,B,C,D) = (0,,2,4,5,6,8,9,2,3,4). Entered Variable Map Simplification and the simplified expression is shown below: The Entered Variable Map Truth-Table corresponding to the above expression is shown below:

IC 745 is an 8-channel digital multiplexer having 8- data inputs D0 D7, three select lines (MSB)ABC(LSB) and two complementary outputs designated as Y and Y. IC 7404 contains 6-inverters. IC 745 and IC 7404 are inserted into the separate sockets in the digital trainer. In IC 745 Pin 6 is Vcc and Pin 8 is Ground. In IC 7404 in 4 is Vcc and Pin 7 is Ground. Vcc pins of both the ICs are connected to +5V dc power source pin. Ground pins of both the ICs are connected the Ground points in the trainer. The circuit is rigged up as shown in the following diagram. Inputs D0 through D7 are connected as shown in the diagram and as required by the function to be implemented. Output Y (Pin 5) is connected to LED. To enable the IC 745, Pin 7 (Enable Pin) which is active low is connected to GND. Additional input D (LSB) derived from a switch is connected to Pin of IC 7404. Pin 2 (output) of IC 7404 is D and hence connected to Pin 3, Pin and Pin 2 of IC 745constituting D, D3, and D7 respectively. Pin 4 (D5) of IC 745 is grounded remaining D input pins to the Vcc. Inputs ABCD are varied by making the corresponding switches ON or OFF, according to the truth table below and the output observed in the LED (ON =; OFF = 0) is verified for correctness. 8. BLOCK / CIRCUIT / MODEL DIAGRAM / REACTION EQUATION: a) Hardware Implementation Pin Diagram: IC 745 (8: MUX) Circuit Diagram: IC 7404(NOT Gate)

b) Simulation module MUX8to(A,B,C,D0,D,D2,D3,D4,D5,D6,D7, Y); input A,B,C,D0,D,D2,D3,D4,D5,D6,D7; output Y; reg Y; always @ (A or B or C or D0 or D or D2 or D3 or D4 or D5 or D7) case ({A, B, C}) 0: Y = D0; : Y = D; 2: Y = D2; 3: Y = D3; 4: Y = D4; 5: Y = D5; 6: Y = D6; 7: Y = D7; endcase endmodule 9. OBSERVATION TABLE / LOOKUP TABLE / TRUTH TABLE: a)

0. FORMULA / CALCULATIONS: N/A. GRAPHS / OUTPUTS: 2. RESULTS & CONCLUSIONS: A four-variable logic expression is simplified using entered variable map and is verified using 8: multiplexer. 3. LEARNING OUTCOMES : We can conclude that using an Entered variable map a four variable logic expression can be simplified so that it can be implemented using an 8: Multiplexer. Thus it can also be concluded that a multiplexer sometimes works as an universal logic circuit because a 2n to multiplexer can be used as a design solution for any n variable truth table. 4. APPLICATION AREAS: Programmable Logic Devices. Multiplexing. Digital Subscriber Line Access Multiplexer. 5. REMARKS:. EXPERIMENT NO: 06 2. TITLE: Code Converters 3. LEARNING OBJECTIVES: To learn the importance of non-weighted code. To learn to generate gray code. 4. AIM: Design and implement code converter I)Binary to Gray II)Gray to Binary Code using basic gates. 5. MATERIAL / EQUIPMENT REQUIRED: IC 7404, IC 7432 2, IC 74 2 or IC 7486 2 Patch Cords & IC Trainer Kit 6. THEORY / HYPOTHESIS: Binary Codes: A symbolic representation of data/ information is called code. The base or radix of the binary number is 2. Hence, it has two independent symbols. The symbols used are 0 and. A binary digit is called as a bit. A binary number consists of sequence of bits, each of which is either a 0 or. Each bit carries a weight based on its position relative to the binary point. The weight of each bit position is one power of 2 greater than the weight of the position to its immediate right. e. g. of binary number is 000 which is equivalent to decimal number 35. Gray Codes: It is a non-weighted code; therefore, it is not a suitable for arithmetic operations. It is a cyclic code because successive code words in this code differ in one bit position only i.e. it is a unit distance code.

Applications of Gray Code: In instrumentation and data acquisition system where linear or angular displacement is measured. In shaft encoders, input-output devices, A/D converters and the other peripheral equipment. Code Converters: The availability of a large variety of codes for the same discrete elements of information results in the use of different codes by different digital systems. It is some time necessary to use the output of one system as the input to the other. The conversion circuit must be inserted between the two systems if each uses different codes for the same information. Thus a code converter is a circuit that makes the two systems compatible even though each uses the different code. 7. PROCEDURE / PROGRAMME / ACTIVITY: Check all the components for their working. Insert the appropriate IC into the IC base. Make connections as shown in the circuit diagram. Verify the Truth Table and observe the outputs 8. BLOCK / CIRCUIT / MODEL DIAGRAM / REACTION EQUATION: IC 74 Pin Diagram IC 7486 Pin Diagram Binary to Gray code converter BOOLEAN EXPRESSIONS: G3=B3 G2=B3 B2 = B3B2 + B3B2 G=B B2 = BB2 + BB2 G0=B B0 = BB0 + BB0 Gray to binary code converter

or BOOLEAN EXPRESSIONS: B3 = G3 B2 = G3 G2 = G3G2 + G3G2 B = G3 G2 G = G3 (G2G + G2G) = G3(G2G + G2G)' + G3(G2G + G2G) = G3(G2 G + G2G) + G3(G2G + G2G) = G3G2 G+ G3G2G+ G3G2G+G3 G2G B0=G3 G2 G G0 9. OBSERVATION TABLE / LOOKUP TABLE / TRUTH TABLE: 0. FORMULA / CALCULATIONS: N/A. GRAPHS / OUTPUTS: N/A 2. RESULTS & CONCLUSIONS: Binary to gray code conversion and vice versa is realized using basic gates. 3. LEARNING OUTCOMES : Binary to gray code conversion and vice versa is implemented using basic gates. 4. APPLICATION AREAS: Code conversion. Encoding and decoding. 5. REMARKS:

. EXPERIMENT NO: 07 2. TITLE: PARITY GENERATOR AND CHECKER 3. LEARNING OBJECTIVES: To implement parity generator and parity checker using basic gates. 4. AIM: Design and verify the Truth Table of 3-bit Parity Generator and 4-bit Parity Checker using basic Logic Gates with an even parity bit. 5. MATERIAL / EQUIPMENT REQUIRED: IC7404, IC74 2, IC7432 2 or IC7486 Trainer kit, patch cords. 6. THEORY / HYPOTHESIS: Parity Generator: It is combinational circuit that accepts an n- bit stream data and generates the additional bit that is to be transmitted with the bit stream. This additional or extra bit is termed as a parity bit. In even parity bit scheme, the parity bit is 0 if there are even number of s in the data stream and the parity bit is if there are odd number of s in the data stream. In odd parity bit scheme, the parity bit is if there are even number of s in the data stream and the parity bit is 0 if there are odd number of s in the data stream. Let us discuss both even and odd parity generators. Parity Check: It is a logic circuit that checks for possible errors in the transmission. This circuit can be an even parity checker or odd parity checker depending on the type of parity generated at the transmission end. When this circuit is used as even parity checker, the number of input bits must always be even. When a parity error occurs, the sum even output goes low and sum odd output goes high. If this logic circuit is used as an odd parity checker, the number of input bits should be odd, but if an error occurs the sum odd output goes low and sum even output goes high. 7. PROCEDURE / PROGRAMME / ACTIVITY: Make the connections according to the design and verify the truth table. 8. BLOCK / CIRCUIT / MODEL DIAGRAM / REACTION EQUATION: Parity Generator with even parity bit: Parity Checker with even parity bit: Parity Checker with even parity bit using XOR gates:

9. OBSERVATION TABLE / LOOKUP TABLE / TRUTH TABLE: 0. FORMULA / CALCULATIONS: N/A. GRAPHS / OUTPUTS: N/A 2. RESULTS & CONCLUSIONS: 3-bit Parity generater and 4-bit parity checker using even parity is implemented using basic gates. And truth table is verified. 3. LEARNING OUTCOMES : Able to implement parity generator and parity checker using basic gates. 4. APPLICATION AREAS: Error detection and correction. 5. REMARKS:. EXPERIMENT NO: 08 2. TITLE: MASTER-SLAVE JK FLIP-FLOP 3. LEARNING OBJECTIVES: To learn about various applications of flip flops. To learn and understand the working of IC 740. To learn and understand the working of J-K Master Slave Flip flop. To develop Verilog/VHDL code for positive edge triggered D Flip-Flop using behavioral modeling in Xlinx simulator. 4. AIM: To study the truth table of J-K Master Slave flip flop and verify the same. To develop Verilog/VHDL code for positive edge triggered D Flip-Flop and simulate its working. 5. MATERIAL / EQUIPMENT REQUIRED:

IC 740 2 IC 7400 2 Patch Cords & IC Trainer Kit PC with Windows XP, XILINX software. 6. THEORY / HYPOTHESIS: A flip-flop is a circuit that can maintain a binary state until directed by an input signal to switch states. JK flip-flop is the most generally used flip-flop, which is edge triggered and has got two data inputs J & K, and a clock input. Normal data inputs to a flip-flop are referred to as synchronous inputs, because they effect the output in steps synchronous with the clock signal. Preset and Clear are asynchronous inputs, because they can set / reset the flip-flop regardless of the status of clock. When Preset is activated, the flip-flop will be set and when Clear is activated, the flip-flop will be reset. Preset and Clear find use when multiple flipflops are ganged together to perform a function. In Master-Slave JK flip-flop, two flip-flops are arranged such that, when the clock pulse enables the first (the Master) latch, it disables the second (the Slave) latch. When the clock changes the state again (on its falling edge), the output of the Master latch is transferred to the Slave latch. The output of MS JK flip-flop is: Qnext = JQ + K Q NOTE: A group of flip-flops sensitive to pulse duration is a latch. E.g.: 7475, a 4-bit latch. A group of flip-flops sensitive to pulse transition is a register. E.g.: 7475, a 4-bit register. 7. PROCEDURE / PROGRAMME / ACTIVITY: Flip-flop is a sequential circuit used as memory element in other sequential circuits as it is capable of storing a single bit of information. Every flip-flop has two complementary outputs (Q and Q ). Numbers of inputs to a JK flip-flop is 2 and are usually designated as J and K. The circuit does not respond to the change in the inputs unless an additional input called the clock input is applied. NAND gates of both the 3-input and 2-input ICs are connected as shown below. It is ensured that the Vcc and GNDs of both the ICs are connected to +5V dc power source and Ground points respectively in the trainer. Outputs Q and Q are connected to the LEDs. Inputs J and K are connected to the switches and the CP input is connected to the monopulser slot in the trainer. Initially J=0 and K = 0. Observe the Q. If it is 0, apply the clock pulse. Otherwise make clear LOW (to make Q=0) and again HIGH (for normal operation) and then apply the clock pulse. Observe the output listed in the column captioned Q(t+). If Q= is to be established, make preset LOW (to make Q=) and again HIGH (for normal operation). Likewise obtain all the input combinations according the sequence in the table and verify corresponding outputs. 8. BLOCK / CIRCUIT / MODEL DIAGRAM / REACTION EQUATION: a) Hardware Implementation Pin Diagram: IC 7400(2-input NAND Gate) IC 740 (3-input NAND)

Circuit Diagram: b) Simulation module DFF(Clock, D, Q); input Clock, D; output Q; reg Q; always @ (posedge Clock) Q = D; endmodule 9. OBSERVATION TABLE / LOOKUP TABLE / TRUTH TABLE: a) 0. FORMULA / CALCULATIONS: N/A. GRAPHS / OUTPUTS:

2. RESULTS & CONCLUSIONS: The J-K Master / Slave Flip Flop is designed using NAND gates and its truth table is verified. 3. LEARNING OUTCOMES : The master slave flip flop is used as a solution to the race around problem in flip flops. 4. APPLICATION AREAS: Data Storage Data Transfer Counter, Registers Frequency Division. 5. REMARKS:. EXPERIMENT NO: 09 2. TITLE: SYNCHRONOUS UP-COUNTER 3. LEARNING OBJECTIVES: To learn about synchronous Counter and its application. To learn and understand the working of IC 7476. To learn the design and the working of synchronous counter. To develop Verilog/VHDL code for mod-8 up counter using behavioral modeling in Xilinx simulator. 4. AIM: To Design and implement mod n (n<8) synchronous up-counter using J-K Flip Flop. To develop Verilog/VHDL code for mod-8 up counter and simulate its working. 5. MATERIAL / EQUIPMENT REQUIRED: IC 7476 2 IC 7408 Patch Cords & IC Trainer Kit, PC with Windows XP, XILINX software. 6. THEORY / HYPOTHESIS: A Counter is a sequential circuit that goes through a prescribed sequence of states up on application of input pulse. Counter are in two categories Ripple Counter (Asynchronous Counter) consists of a series connection of complementing flip-flops (T / JK type), with the output of each flip-flop connected to the clock pulse input of the next higher order flip-flop. The flip-flop holding the LSB receives the clock pulses. Synchronous Counter the input pulses / clock pulses are applied to all clock pulse inputs of all the flip-flops simultaneously. The ripple counter requires a finite amount of time for each flip flop to change state. This problem can be solved by using a synchronous parallel counter where every flip flop is triggered in synchronism with the clock, and all the output which are scheduled to change do so simultaneously. The counter progresses counting upwards in a natural binary sequence from count 000 to count 00 advancing count with every negative clock transition and get back to 000 after

this cycle. 7. PROCEDURE / PROGRAMME / ACTIVITY: The counter with n flip-flops has maximum mod number 2n. For example, 3-bit binary counter is a mod 8 counter. This basic counter can be modified to produce MOD numbers less than 2n by allowing the counter to skip states those are not normally part of counting sequence. MOD-5 synchronous counter is designed below using JK flip-flops and the circuit is implemented as shown in the circuit diagram. A timing diagram is also constructed below. Number of Flip-flops required = 3 as 3 is the minimum number for which 5<8. Let the inputs of the three Flip-flops be JA, KA JB, KB, JC, KC. Let the normal outputs be QA, QB, QC and the complementary outputs be QA, QB, QC. Preset and Clear are the active low direct inputs (asynchronous inputs) to set or reset the counter (means to set or reset all the flip-flops contained in the counter) before to the application of the clock pulse to obtain the next state of the counter. The Characteristic table is useful for analysis and defining operation of flip-flops. The characteristic table of JK flip-flop is given below. But during design, we normally know the transition from the present state to the next state, called Transition table. The transition table is derived using the truth table. Truth table is constructed using the given counter. Here, given counter is mod-5. i.e., the given sequence is: 0,, 2, 3, 4, 0,... First draw the State Diagram: Then construct the expected Truth table: Expected Truth table From the truth table, construct Transition table.

Transition table of Mod-5 Counter Now, construct the Excitation table of JK flip-flop using the State diagram / Characteristic table of JK flip flop. A table that lists the required inputs for a given change of state is called Excitation table. Now by using the excitation table and the transition table, evaluate the flip-flop inputs as shown below. Go for K-Map simplification, and after K-Map simplification, expressions for the flip-flop inputs are as shown below:

Having obtained the combinational expressions for the flip-flop inputs to ensure the desired next state transitions at the corresponding outputs, the following circuit diagram is rigged up. Two 7476 JK Flip-flop ICs are required as one IC contains only two JK flip-flops. Vcc and GND of both the ICs are connected. Outputs QA(LSB), QB, and QC(MSB) are connected to LEDs. Preset and Clear are the direct inputs connected to the switches. All the flip-flops driven by the same clock pulse, establishes the concept of synchronous counter. Clock input may be supplied with monopulser or continuous clock generator. 8. BLOCK / CIRCUIT / MODEL DIAGRAM / REACTION EQUATION: a) Hardware Implementation Pin Diagram: IC 7476 (J K Flip Flop) Circuit Diagram: IC 7408(2-input AND Gate)

b) module Mod8UpCounter(Clock, Rst, Q); input Clock, Rst; output [2:0] Q; reg [2:0] Q; always @ (negedge Clock or negedge Rst) if (~Rst) Q = 3'b0; else Q = Q + ; endmodule 9. OBSERVATION TABLE / LOOKUP TABLE / TRUTH TABLE: N/A 0. FORMULA / CALCULATIONS: N/A. GRAPHS / OUTPUTS: a) b)

2. RESULTS & CONCLUSIONS: The mod-n synchronous counter is successfully implemented by using the JK Flip Flop. 3. LEARNING OUTCOMES : Using the JK Flipflops a mod-n synchronous counter can be implemented thereby allowing to generate a count sequence that is desired. 4. APPLICATION AREAS: Data Storage Data Transfer Frequency Division. 5. REMARKS:. EXPERIMENT NO: 0 2. TITLE: ASYNCHRONOUS COUNTER 3. LEARNING OBJECTIVES: To learn about asynchronous counter and decade counter. To learn and understand the working of IC 7490. To understand the working of mod-n asynchronous counter using decade counter. 4. AIM: Design and implement an asynchronous counter using decade counter IC to count up from 0 to n (n<=9) and demonstrate on 7-segment display (using IC-7447). 5. MATERIAL / EQUIPMENT REQUIRED: IC 7490 IC 74 IC 7447 Patch Cords & IC Trainer Kit 6. THEORY / HYPOTHESIS: A Counter is a sequential circuit that goes through a prescribed sequence of states up on application of input pulse. Counter are in two categories Ripple Counter (Asynchronous Counter) consists of a series connection of complementing flip-flops (T / JK type), with the output of each flip-flop connected to the clock pulse input of the next higher order flip-flop. The flip-flop holding the LSB receives the clock pulses. Synchronous Counter the input pulses / clock pulses are applied to all clock pulse inputs of all the flip-flops simultaneously. A counter is a device which stores (and sometimes displays) the number of times a particular event or process has occurred, often in relationship to a clock signal. In asynchronous counter a clock signal is provided for one flip-flop and its output is provided as clock source for next flip-flop. The output of asynchronous counter is not synchronized with clock signal. A decade counter follows a sequence of 0 states and returns to zero after the count of nine. Such a counter must have at least 4 flip flops to represent each decimal digit since a decimal digit is represented by a binary code with at least 4 bits.

7. PROCEDURE / PROGRAMME / ACTIVITY: Explained along with the circuit diagram. 8. BLOCK / CIRCUIT / MODEL DIAGRAM / REACTION EQUATION: Pin Diagram: IC 7490 (Decade counter) Internal Diagram of 7490 IC 7447 Function Table of 7490 IC 74 (3-input AND Gate)

Circuit Diagram: The examples of different MODs are self-explanatory with the corresponding circuit diagrams.

For mod-6 (divide-by-6) and onwards the clk input is INPUT-A, and not the INPUT-B. INPUT-B is connected to QA. Divide-by-8: QD to R and R2. Divide-by-9: QAQD to AND Gate, then ANG Gate output to R and R2 / QAQD to RR2.

9. OBSERVATION TABLE / LOOKUP TABLE / TRUTH TABLE: Given along with the circuit diagram. 0. FORMULA / CALCULATIONS: N/A. GRAPHS / OUTPUTS: N/A 2. RESULTS & CONCLUSIONS: An asynchronous counter using a decade counter is designed and the truth table is verified for the same. 3. LEARNING OUTCOMES : By using a decade counter we can obtain an appropriate decimal number 4. APPLICATION AREAS: Binary Coded Decimal. Finite State Machines. 5. REMARKS: