SOLUTIONS TO INTERNAL ASSESSMENT TEST 3 Date : 8/11/2016 Max Marks: 40 Subject & Code : Analog and Digital Electronics (15CS32) Section: III A and B Name of faculty: Deepti.C Time : 11:30 am-1:00 pm Note: Answer five complete questions each of 8 marks, one from each part PART 1. 1. a) Differentiate between ideal Op-Amp and practical Op-Amps. (4 Marks) Ideal OPAMP Practical OPAMP Infinite voltage gain Practical Voltage gain around 200,000 Infinite input impedance Practical input impedance about 10 12 Ω for FET input op-amps Zero output impedance Low output impedance independent of load Infinite bandwidth Practically limited to few MHz range(slew rate limited to 0.5 20 V/µs Linear irrespective of entire analog signal range Zero input offset voltage Mostly Linear with slight variation Practical very small value of input offset voltage b) Explain the working of Op-Amp as peak detector circuit. (4 Marks) PEAK DETECTOR measures the Positive peak values of the Square wave input. During the positive half-cycle of Vin, the output of the op amp drives D1 on, charging capacitor C to the positive peak value Vp of the input voltage Vin. Thus, when D1 is forward biased, the OP AMP operates as a voltage follower. On the other hand, during the negative half-cycle of Vin, diode D1 is reverse biased, and voltage across C is retained. The only discharge path for C is through R1 since the input bias current Ib is negligible For proper operation of the circuit, the charging time constant (CRdiode) and discharging time constant (CR1) must satisfy the following conditions: The capacitor C1 charges rapidly, via D1, to the peak positive value of an input signal, but discharges slowly via R1 when the signal falls below the peak value.
The second opamp is used as a voltage-following buffer stage; to ensure that R1 is not shunted by external loading effects.this circuit outputs the peak voltage of the input. The capacitor stores the current peak voltage. If the input voltage is larger, the op-amp output goes positive until the capacitor is charged up to the new peak value. If the input voltage is smaller, the diode keeps the capacitor from being discharged. 2. Explain with a neat connection diagram and waveforms how IC555 timer is used as an astable multivibrator (8 Marks) When Q is low or output V OUT is high, the discharging transistor is cut-off and the capacitor C begins charging toward V CC through resistances R A and R B. Because of this, the charging time constant is (R A + R B ) C. The charging of the capacitor will be done using two external resistors RA& RB. When the voltage of the capacitor goes above 2/3 Vcc, then the output of comparator1 will be High, which sets the flip-flop so that its Q is high and the timer output Q (output at pin no 3) is low. So the final o/p of the timer is LOW. High Q drives discharge transistor to saturation and the discharge transistor Q1 transistor switches ON. The capacitor starts discharging through resistor RB with a discharging time constant R B C. With the discharging of capacitor, trigger voltage at inverting input of comparator 2 decreases. When the capacitor voltage becomes less than 1/3 VCC, comparator 2 output goes high resetting the flip flop (Q=0, Q =1).This cycle repeats.
3. For the relaxation oscillator in Figure determine the peak to peak amplitude and frequency of the square wave output given that saturation output voltage of OPAMP is +/- 12.5V at power supply voltages of +/- 15V β = R1/(R1+R2) = 0.825 PART2 (8 Marks) T = 2 RC ln [(1 + β)/(1- β)] = 0.469 ms F=1/T=2.13 khz Peak to peak amplitude = 2Vsat = 25 V 4. The figure on the right shows as second order low pass filter built around a single operational amplifier. Calculate the values of R1,R2,C1,C2 and R3.The filter has a cutoff frequency of 10kHz,Q factor of 0.707 and input impedance not less than 10 kω (8Marks) Let R1=R2= R =10 kω Q = 0.5 * C1/C2 For Q=0.707 C1= 2C2 Given fc= 1/(2πR C1C2) =10 khz Hence C2 = 0.0011 µf C1 = 2C2 = 0.0022 µf R3= R1+R2= 20 kω
PART 3 5. a) Explain the working of Schmitt Trigger along with its Transfer characteristic. (5 Marks) A Schmitt trigger is an electronic circuit that is used to detect whether a voltage has crossed over a given reference level. It has two stable states (Bistable Multivibrator). It is useful as a signal-conditioning device. Slow varying inputs are converted to a rectangular output that has sharp leading and trailing edges. The Schmitt trigger is a comparator application which switches the output negative when the input passes upward through a positive reference voltage. It then uses positive feedback of a negative voltage to prevent switching back to the other state until the input passes through a lower threshold voltage, thus stabilizing the switching against rapid triggering by noise as it passes the trigger point. That is, it provides feedback which is not reversed in phase, but in this case the signal that is being fed back is a negative signal and keeps the output driven to the negative supply voltage until the input drops below the lower design threshold. Transfer Characteristic The value of the input voltage Vi that causes the output to jump from LOW to HIGH is called the positive going threshold VT+. The value of Vi that causes the output to switch from HIGH to LOW is called the negative-going threshold VT-. The transfer characteristic is as shown below: b) Derive characterstic equation of SR Flip Flop. (3 marks) A description of the next state of a flip-flop. Characterstic equation is an expression for Qt+1 in terms of the present state and input.it can be constructed from the Karnaugh Map
6. With a neat logic diagram and truth table, explain the working of master slave JK Flip - Flop along with its implementation using NAND gates. (8 Marks) The J and K data is processed by the flip-flop after a complete clock pulse. On the positive transition of the clock, the data from the J and K inputs is transferred to the master. On the negative transition of the clock, the data from the master is transferred to the slave. The flip-flop is referred to as pulse-triggered. When J = K = 1, the output can continue to toggle as long as the clock is high. This condition is called the racearound condition. Propagation delay prevents the JK flip-flop from racing. The JK flip-flop output changes after the PT of the clock. The new Q and Q values are too late to coincide with the PTs driving the AND gate. If PTs are narrower than the propagation delay of the flip-flop, the returning Q and Q arrive too late to cause false triggering. A better method to avoid race around condition is to use a master-slave circuit
7. a) Write the Verilog code for a positive edge triggered JK Flip Flop (5 Marks) module JK_FF (J,K,CLK,Q,Qnot); output Q,Qnot; input J,K,CLK; reg Q; assign Qnot = ~ Q ; always @(posedge CLK) case({j,k}) 2'b00: Q = Q; 2'b01: Q = 1'b0; 2'b10: Q = 1'b1; 2'b11: Q = ~ Q; endcase endmodule b) Explain the characteristics of an ideal clock. (3 Marks) 1. Clock levels must be absolutely stable (HIGH = + 5V,LOW= 0V,unchanging) 2. Ideal clock has zero transition time 3. The frequency of the clock should be steady and unchanging over a period of time
8. With a neat logic and timing diagram, explain the working of a 4 - bit SISO register using JK Flip Flops The serial in/serial out shift register accepts data serially--that is, one bit at a time on a single line. It produces the stored information on its output also in serial form. With four stages, this register can store up to four bits of data; its-storage capacity is four bits. (8 Marks) JK FFs cascaded Q to J, Q to K with clocks in parallel to yield an alternate form of the shift register above. A serial-in/serial-out shift register has a clock input, a data input, and a data output from the last stage. In general, the other stage outputs are not available Otherwise, it would be a serial-in, parallel-out shift register.. The waveforms below are applicable to either one of the preceding two versions of the serial-in, serial-out shift register. The three pairs of arrows show that a three stage shift register temporarily stores 3-bits of data and delays it by three clock periods from input to output. At clock time t1 a data in of 0 is clocked from D to Q of all three stages. In particular, D of stage A sees a logic 0, which is clocked to QA where it remains until time t2. At clock time t2 a data in of 1 is clocked from D to QA. At stages B and C, a 0, fed from preceding stages is clocked to QB and QC. At clock time t3 a data in of 0 is clocked from D to QA. QA goes low and stays low for the remaining clocks due to data in being 0. QB goes high at t3 due to a 1 from the previous stage. QC is still low after t3 due to a low from the previous stage. QC finally goes high at clock t4 due to the high fed to D from the previous stage QB. All earlier stages have 0s shifted into them. And, after the next clock pulse at t5, all logic 1s will have been shifted out, replaced by 0s
9. With neat diagram, explain a 4 bit universal shift register (8 Marks) Universal Shift Register is a register which can be configured to load and/or retrieve the data in any mode (either serial or parallel) by shifting it either towards right or towards left. In other words, a combined design of unidirectional (either right- or left-shift of data bits as in case of SISO, SIPO, PISO, PIPO) and bidirectional shift register along with parallel load provision is referred to as universal shift register. Such a shift register capable of storing n input bits. n 4 1 multiplexers to drive the input pins of n flip-flops in the register which are also connected to clock and clear inputs. All of the multiplexers in the circuit share the same select lines, S1 and S0 (pink lines in the figure), in order to select the mode in which the shift registers operates. First input (Pin Number 0) connected to the output pin of the same flip-flop i.e. zeroth pin of MUX1 is connected to Q1; zeroth pin of MUX2 is connected to Q2, Zeroth pin of MUX n is connected to Qn. Second input (Pin Number 1) connected to the output of the very-previous flip-flop (except the first flip-flop FF1 where it acts like an serial-input to the input data bits which are to be shifted towards right) i.e. first pin of MUX2 is connected to Q1, first pin of MUX3 is connected to Q2, first pin of MUXn is connected to Qn-1.Third input (Pin Number 2) connected to the output of the very-next flip-flop (except the first flip-flop FFn where it acts like an serial-input to the input data bits which are to be shifted towards left) i.e. second pin of MUX1 is connected to Q2, second pin of MUX2 is connected to Q3, second pin of MUXn-1 is connected to Qn. Fourth input (Pin Number 3) connected to the individual bits of the input data word which is to be stored into the register, thus providing the facility for parallel loading.
10. a) Explain briefly serial adder to add two 4 - bit numbers with a neat sketch. (5Marks) Shift control used to stop addition, Generally not a good idea to gate the clock Shift register can be arbitrary length, Full Adder can be built from combinational logic b) Write Verilog HDL code for 4-bit SIPO shift register where all the flip-flop outputs are available externally. module sipo (d,clk,q); input clk,d; output [3:0]q; wire [3:0]q; always@(negedge clk) begin q[0] <= d; q[1] <= q[0]; q[2] <= q[1]; q[3] <= q[2]; end endmodule // Nonblocking assignment *********** (3Marks)