EE-Fall 00 Digital tegrated Circuits Timing Lecture Timing Announcements Homework #8 due next Tuesday Synchronous Timing Project Phase plan due this Sat. Hanh-Phuc s extra office hours shifted next week Tues. -pm R R C in C out 5 5 Class Material Latch Parameters Last lecture Latches and flip-flops Today s lecture Timing Reading Chapter 7, 0 D PW m T tsetup t d-q Q Delays can be different for rising and falling data transitions 6 6
Register Parameters Clock Uncertainties T Power Supply terconnect Devices Variation 5 Temperature Clock Generation 6 Capacitive Load 7 Coupling to Adjacent Lines D Q t setup Delays can be different for rising and falling data transitions 7 7 Sources of clock uncertainty 0 0 Clock Skew and Jitter R t SK t t t JS t cclk-q q t cclk-q,min cd tt su, t setup, hold t logic logic t t logic, cd logic,min Both skew and jitter affect the effective cycle time Only skew affects the race margin (usually) Cycle time (max): T > + t logic + t setup Race margin (min): <,min + t logic,min 8 8 Clock Nonidealities Clock skew Spatial variation in temporally equivalent clock edges; deterministic + random, t SK Clock jitter Temporal variations in consecutive edges of the clock signal; modulation + random noise Cycle-to-cycle (short-term) t JS Long term t JL Variation of the pulse width Important for level sensitive clocking Clock Skew # of registers Earliest occurrence of edge Nominal / sertion Max skew Latest occurrence of edge Nominal + / 9 9
Positive and Negative Skew R R R t t t (a) Positive skew R t (b) Negative skew t R t t t c q t t c q, cd clk-q,min t su, t setup, t logic t t logic logic, t cd logic,min Minimum cycle time: T clk - = + t setup + t logic t Worst case is when receiving edge arrives early (positive ) 6 6 Positive Skew T + R + t h T Launching edge arrives before the receiving edge t c q,min c cd t su, t setup, t logic t logic t logic, t cd logic,min Hold time constraint: t (clk-q,min) + t (logic,min) > + Worst case is when receiving edge arrives late Race between data and clock t 7 7 Negative Skew Longest Path in Edge-Triggered Systems T - T t clk-q t logic t setup t JS + T Receiving edge arrives before the launching edge Latest point of launching Earliest arrival of next cycle 5 5 8 8
Clock Constraints in Edge-Triggered Systems Pipelining a a If launching edge is late and receiving edge is early, the data will not be too late if: log log + t logic + t setup < T t JS, t JS, - b b Minimum cycle time is determined by the maximum s through the logic Reference Pipelined + t logic + t setup + + t JS < T Skew can be either positive or negative 9 9 Shortest Path Latch-Based Clocking Earliest point of launching,min t logic,min F C C G C Nominal clock edge Data must not arrive before this time (Domino logic almost always uses latch-based clocking) Compute F compute G 0 0 Clock Constraints in Edge-Triggered Systems If launching edge is early and receiving edge is late:,min + t logic,min t JS, > + t JS, + Minimum logic,min + t logic,min > + t JS + (This assumes jitter at launching and receiving clocks are independent which usually is not true) Latch vs. Flip-flop a flip-flop based system: Data launches on one rising edge And must arrive before next rising edge If data arrives late, system fails If it arrives early, wasting time Flip-flops have hard edges a latch-based system: Data can pass through latch while it is transparent Long cycle of logic can borrow time into next cycle As long as each loop finished in one cycle
Time Borrowing Example 5 5 Latch vs. Flip-flop Summary Flip-flops generally easier to use Most digital ASICs designed with register-based timing But, latches (both pulsed and level-sensitive) allow more flexibility And hence can potentially achieve higher performance Latches can also be made more tolerant of clock un-certainty More in EE 6 6 Next Lecture Clock and power distribution 7 7