100 Gb/s per Lane for Electrical Interfaces and PHYs CFI Consensus Building. CFI Target: IEEE November 2017 Plenary

Transcription

1 100 Gb/s per Lane for lectrical Interfaces and PHYs CFI Consensus Building CFI Target: I November 2017 Plenary 1

2 Objective Build consensus of starting a study group investigating a 100 Gb/s per lane for electrical interfaces and PHYs project We do not need to: Fully explore the problem Debate strengths and weaknesses of solutions Choose a solution Create a PAR or 5 Criteria Create a standard Anyone in the room may vote or speak 2 2

3 Motivation for 100 Gb/s per Lane With next steps in thernet, comes the needed next step in interfaces. Faceplate density Chip breakout ystem throughput They are all tied together! *Web-scale data centers and cloud based service are presented as leading applications 3 3

4 lectrical interfaces come in many shapes and sizes. 4

5 Tonight s Meeting To present the market need, technical Feasibility, and Why Now?? of 100Gb/s per lane of electrical signaling. To gain consensus towards Thursday s Call-for-Interest. We are NOT discussing specific implementations or objectives these are just some of the reasons that we need a study group! 5

6 Market Drivers for 100 Gb/s per lane for lectrical Interfaces 6

7 What Are We Talking About? Fabric /witch R D BP C O N N LC C O N N R D Nx??G Fabric - witch Interface R D R D N P U M A C R D R D G L U TX O/O RX O/O Backplane Chip-2-Chip Chip-2-Module Consider how many instances of the interface can exist in the system KR C2C C2M LR, R, DR CR or hort R 7

8 Bandwidth (Gb/s) Historical Perspective hows What s Coming witch IO BW lectrical Lane peed Ratification Historical curve fit to highest rate switch products introduced to market (blue squares) ingle AIC IO capacity doubling every ~ 2 years

9 IO scape forcing transition to higher lane speeds xisting witch Devices ~ 70mm package is a current BGA practical maximum (due to coplanarity / warpage) This will force BGA devices with > 14Tb/s of aggregate bandwidth to transition to lane rates of higher greater than 50G (possibly 100G?) 9

10 Backplane is easily system bottleneck xisting ystems New ystems Defined backplane and pin count Can tune pitch and pin count No choice but to put more signal across the pin However, there is limited gain left in this mechanical density backplane speed needs to scale for bandwidth to grow 10

11 The Current thernet Family (100 Gb/s and Above) ignaling (Gb/s) lectrical Interface Backplane MMF 500m MF 2km MF 10 CAUI-10 CR10 R10 10X10 25 CAUI-4 / 100GAUI-4 10km MF 40km MF KR4 CR4 R4 PM4 CWDM4 CLR4 LR4 R GAUI-2 KR2 CR2 R2 100??? DR GAUI GAUI-4 KR4 CR4 R4 DR4 FR4 LR4 100??? GAUI-16 R16 Twinax 100GBA- 200GBA- 400GBA GAUI-8 FR8 LR8 100??? DR4 Includes thernet standards in development Underlined indicates industry MA or proprietary solutions Blue indicates the areas of interest for this CFI 11

12 Technical Feasibility for 100 Gb/s per lane for lectrical Interfaces 12

13 It s time to open the toolbox again From the 100Gb lectrical Backplane / Cu Cabling Call-For-Interest consensus building presentation, November

14 Data rate per lane, Gb/s olutions for each generation 100 erdes Backplane Cable 100 Gb/s/lane? +Decision feedback equalization assumed +Transmitter training + Lightweight FC + Improved FR4 (~25 db at 5.2 GHz) + Tighter crosstalk/impedance control +PAM4 +Additional transmitter tap +Configurable precoding + tronger reference receiver 10 PAM2/NRZ modulation 7 m cable + ~30 db at 13.3 GHz +Tighter crosstalk/impedance control 3 m cable FR4 (~8.8 db at 0.6 GHz) 25 m cable +Fixed transmitter de-emphasis FR4 (~16 db at 1.6 GHz) + tronger reference receiver + tronger Reed-olomon FC (PAM4 introduced) + Megtron 6 (~35 db at 12.9 GHz) +Tighter crosstalk/impedance control 15 m cable 5 m cable * Dates are approximate 14

15 Different constraints for different applications Chip-to-module Coexistence with defined PHYs, FC, PC? What is the minimum insertion loss that supports useful topologies? Consider improved PCB materials, PCB vs. cable, improvements in impedance/noise control? Chip-to-chip and backplane What is the minimum insertion loss that support useful topologies? Consider improved PCB materials, PCB vs. cable, improvements in impedance/noise control? Cable What is the minimum useful reach? Consider middle-of-rack topologies? Apply signal processing to meet the needs of each application 15

16 The discussion is already underway From the proceedings of the I New thernet Applications ad hoc ystem considerations Channel options Higher-speed erdes

17 Technical feasibility summary Rich signal integrity and signal processing toolbox that can be applied to the problem of 100 Gb/s per lane electrical signaling We must be mindful of the different needs for different applications We have done this many times before The discussion is already underway 17

18 Why Now??? 100 Gb/s per lane of lectrical Interfaces 18

19 The Road Map of Port Rates - next logical step Follow the RD 100G/lane is coming G/lane optics are here OIF/Inifinband are working on this We need study and frame it NOW so the Gb/s industry can plan 19

20 The Interest is Here March 2017** traw Polls Taken from NA Ad Hoc unapproved Minutes * ** May 2017* 20

21 ummary 100 Gb/s is the next step on Follow the erdes and continues existing market trends We ve moved to the unknown before and the industry survived. Technical details need to be rebalanced for the next speed. Impact of 100 Gb/s lectrical ignaling is wide across the thernet Family Let s form a tudy Group!! 21

22 Thank You! 22