T1 Electronic Design Review

Transcription

1 T1 Electronic Design Review Saverio Minutoli Talk overview: INFN Genova 7 March 2006 T1 detector structure CSC lab measures Radiation environment Anode FE system overview Anode vs VFAT measures Cathode FE overview Data and Trigger optical links Slow Control Ring H.V. and L.V. power distribution Saverio Minutoli INFN Genova 1

2 Overview of T1 detector T1 is composed by 2 arms Each arm contain 5 planes, each with 6 CSC trapezoidal chambers Each chamber is realized by 1 anode and 2 cathode planes For mechanical reasons, each arm is divided into two halves : each half is considered independent to the other also from electrical/logical point of view In total, each halve include 15 chambers Saverio Minutoli INFN Genova 2

3 Handling signals In each chamber there are (maximum numbers): 220 anode wires 192 x 2 = 384 cathode strips In total for the 2 arms there are 220 x 30 x 2 = wires 384 x 30 x 2 = strips Each wire (anode) and strip (cathode) generate a digital information: 1 bit for each wire and 2 bits for each strip, assuming the half strip resolution for the cathode signals. In total, the maximum number of bits managed by the electronic readout system is approximately (~1000 per chamber). Data taking and triggering are indipendent for each T1 halve: trigger can be combined together at higher hierarchical level. Saverio Minutoli INFN Genova 3

4 Anode/Cathode static measurements Impedance measured with TDR method. Capacitance measured with 4 wires LCR instrument. Anode wires: Z = Ω cap pf (others to gnd) Anode wires length cm Cathode Strips: Z = Ω cap pf (others to gnd) Cathode Strips length 6 80 cm Saverio Minutoli INFN Genova 4

5 T1 Radiation Environment Mika s data 80 Assuming: s/year L=10 32 cm -2 s -1 T T1 CSCs are placed between 7.5m and 9.5m Anode worst position R = 25 cm 10 7 *10-3 *10 2 /10 2 = 10krad/year Cathode position R = cm 10 7 *10-4 *10 2 /10 2 = 1krad/year Saverio Minutoli INFN Genova 5

6 CSC FE Electronics The T1 chambers have been tested on beam, Due to the compatibility with the CMS-EMU CSC chambers, the same FE electronics have been used. Anode FE based on AFEB 16 (validated by EMU people up to krad; hep.phys.cmu.edu/cms/rad_hard/2000/rad_test_p_63_1.html) Cathode FE based on: BUCKEYE - ( tested by EMU people up to 300 krad; no meaningful variation up to 60 krad ) LCT-COMP - ( validated by UCLA people up to 50 krad; Concerning the Anodes FE electronic, due to the different environment, power consumption and mechanical constraints, an alternative solution have been evaluated: We are investigating an testing the compatibility of the analog section of the VFAT2 with the anodes CSC wires. Saverio Minutoli INFN Genova 6

7 CSC Anode FE Electronics VFAT2 VFAT2 was already planned to use for digital buffer, data storage and serializer. Now, for the anode FE, we will try to use also its analog section. Possible problems: Anode capacitance Signal Polarity Shaping time, the CSC signals are not faster VFAT analog, don t have any baseline restoring and tail cancellation Signal amplitude, a CSC can produce hundred of fc Jitter, our CSC have ~100ns Saverio Minutoli INFN Genova 7

8 Anode FE channel adapter network scheme ANODE WIRE MODEL 4M7 ANODE WIRE H.V. = I pf 3k3-3k6 Vdc CSC ANODES CONNECTIONS 0 0 1n 6kV 0 4M7 ANODE WIRE 1n 6kV 0 10k ANODE WIRE HV DECOUPLER CSC to VFAT ADAPTATION NETWORK Av = 53mV/fC VFAT PREAMP 3k3-3k6 Vdc 0 1M 4M7 ANODE WIRE 1n 6kV 0 10k I pF 1n 6kV 10k 330 1p x3 VFAT COMP MISSING IN OUR TESTS 4M7 ANODE WIRE 1n 1n 6kV 0 6kV 0 10k IN OUT DIGITAL OSCILLOSCOPE Saverio Minutoli INFN Genova 8

9 VFAT analog on the test bench The VFAT preamplifier tested isn t the final version. The DUT, FEDC1 V1.0, is DC coupled, the preamp and the shaper stages are identical to the final version, the comparator stage and amplifier (gain x 3) are missing, as the digital parts and spikes protection networks. The test board in the pictures have been produced by the MIC group with the only intent to measure the noise due to the detector capacitance. The Genoa group has bonded few analog channels (6), coupling the passive network as near as possible to the die, but only once is possible to select in output. Saverio Minutoli INFN Genova 9

10 VFAT analog on the test bench VFAT preamp. test board Gain and BW test bench Saverio Minutoli INFN Genova 10

11 VFAT analog channel on the test bench External pulser, no chamber connected Pulse 100µs 1kHz Pulse Gain expected value 53/3=17.65mV/fC The anode signal could be much large, we risk to work in the bent region, where the stage saturate. VFAT output (mv) VFAT-DC preamplifier prototype GAIN -16fC, 236mV 14.75mV/fC fC,-276mV 17.25mV/fC VFAT input (fc) Saverio Minutoli INFN Genova 11

12 VFAT analog on the test bench External pulser, no chamber connected Sinus Input signal Constant Vin=~10fC Considering the CSC peaking time 40-50ns, our working position on the graph is around 4MHz VFAT output (mv) VFAT Bandwidth with CSC anode passive network MHz 19MHz Vin(f) (MHz) Saverio Minutoli INFN Genova 12

13 VFAT analog on the test bench VFAT output width with 10fC Input 84ns 1.4µs VFAT output tail with 30fC Input 800ns VFAT output tail with 10fC Input VFAT output saturation with 100fC Input Saverio Minutoli INFN Genova 13

14 CSC Anode vs analog VFAT tests CSC test conditions: HV CSC chamber, Vdc Gas mixture 55% CO 2 45% Ar Can be triggered with Cosmic rays Saverio Minutoli INFN Genova 14

15 CSC Anode vs analog VFAT tests CSC anode CSC anode VFAT output CSC anode VFAT output VFAT output Anode with Z L =10kΩ, tail too long, with Z L =330Ω seems ok. Saverio Minutoli INFN Genova 15

16 Anodes Considerations The VFAT2 analog section, can be adopted for the CSC anode wires, using the adapter passive network shown. Due to the shorter shaping time, we loose some signal, but we can accept it. With big signals we have a long recovery time due to missing tail cancellation circuits. CSC jitter has been solved with the digital programmable (up to 150ns) stretcher already included in the VFAT2 design. Saverio Minutoli INFN Genova 16

17 Anode FE Card block diagram C12 1n C13 1p CH_1 6kV R12 10k R TRIGGER[8:1] TRIGGER LOGIC [16:1] 0 0 T1 INPUTS ANODES[256:1] ANODES[128:1] VFAT_1 MEZZANINE DACo_I_A1 DACo_V_A1 TRIGGER[16:9] DAV_A1 DOUT_A1 CK40 I2C_VFAT (MAX 8) ANODES[256:129] VFAT_2 MEZZANINE DAV_A2 DOUT_A2 DACo_I_A2 DACo_V_A2 2V5 POWER_SUPPLY CH_256 C14 1n C15 1p DCU I2C_DCU (MAX 16) 6kV R14 10k R R PT100 0 Saverio Minutoli INFN Genova 17

18 Anode FE Card integration Sketch of the new Anode FE Card (AFEC). Old HV network board (digital part not shown) The Anode FE Cards are 10 types, one for each kind of CSC chamber The VFAT mezzanine could be the same used for T2-GEM Saverio Minutoli INFN Genova 18

19 Cathodes FE electronics The cathodes FE electronic components implemented in our design, are the same as used in the CMS-EMU detector. These devices can be well integrated in our CSC chambers system. Buckeye and LCT-COMP are available from CMS. Due to the LCT-COMP device, the cathodes spatial resolution will be increased of a factor two (half strip resolution) and a unique peak identification is also possible. This is usefull in the events where the charge distribution on the cathodes involve more than 3 strips. The structure foreseen is realized with 6 eurocard boards (bigger chamber) per chamber, managing 64 channels each. Each board allocate a VFAT mezzanine (2 bit/channel). Saverio Minutoli INFN Genova 19

20 Anode Cathodes Cathodes CSC Anode and Cathodes Event with 3 cathodes hit underneath an anode. Cosmic triggering Anode Wire length 90cm Z L =330Ω (impedance line matching) Cathode strips length 80cm Z L =150Ω (impedance line matching) Saverio Minutoli INFN Genova 20

21 Cathode FE Card block diagram BUCKEYE LCT_COMP CH_[1:16] BUCKEYE LCT_COMP CK40 +2V5 +5V -5V -10V V25 V5 V5M V10M CH_[17:32] 16 BUCKEYE 16 LCT_COMP 16 DESERIALIZER 128 VFAT_1 MEZZANINE DACo_I_A1 DACo_V_A1 T1 DAV_A1 DOUT_A1 CK40 I2C_VFAT (MAX 8) CH_[33:48] BUCKEYE LCT_COMP I2C CH_[49:64] TEST PULSE IN THRESHOLD 16 3 PEAK_TIME TSIN TSOUT R21 PT100 0 DCU I2C_DCU (MAX 16) CK40 Saverio Minutoli INFN Genova 21

22 FE sub-system overview DOHM-CCU SLOW CONTROL RING 6xCFEC = 2x192chs CSC Plane_n+1 AFEC 220chs CSC Plane_n 50cm Saverio Minutoli INFN Genova 22

23 FE Read-Out Card block diagram C S C n C S C n+1 Saverio Minutoli INFN Genova 23

24 T1 Data architecture ~6k wires CSC (8xVFAT2) x2 16 (GOL) 1 CAVERN (GOL) 1 16 x2 CSC (8xVFAT2) ~6k wires ~12k strips ROC T1 ARM x2x x2x9 ROC T1 ARM ~12k strips T1 DATA_TOTFED (Needs 0 supp.) DAQ 4xSLINK T1 DATA_TOTFED COUNTING ROOM Saverio Minutoli INFN Genova 24

25 T1 Trigger segmentation Only the anodes wires are used to generate trigger informations. T1 chambers will use the basic functions included in VFAT2. VFAT2 provide fast regional hit information to be included within the CMS First Level Trigger (LV1). Anode wires channels are grouped together to form sectors. A hit channel in a given sector will set an LVDS output assigned to that sector to a logic 1". The assigment of channels to sectors is programmable. There are 8 LVDS sector outputs available. T1 trigger set-up use all of them, conseguently, the 128 channels are divided into eight equal regions. Sector 1 (S1) will contain channels 1 to 16, sector 2 (S2) will contain channels 17 to 32 etc. Saverio Minutoli INFN Genova 25

26 T1 Trigger architecture Trigger Bits 2 x 480 = 960 ~6k wires 16:1 S.L. VFAT2 CSC 1 8 x8 (16) (16) CAVERN x2 1 1 x2x x2x15 x2 8 x8 1 VFAT2 CSC 16:1 S.L. ~6k wires T1 ARM T1 ARM T1 TRG_TOTFED (Needs TRG algo.) MASTER TRG_TOTFED LV1 T1 TRG_TOTFED COUNTING ROOM Saverio Minutoli INFN Genova 26

27 Data rates Assuming the highest LV1 rate of 100 KHz. A single FRL can sustain up to 1.6 Gb/s with event size 2 kb. 8 ROC for each half (half T1 arm): 9 data GOL, but only 7.5 are full Need a zero suppression on DATA_TOTFED 15 trigger GOL FRL data size= 128(chs)*16(VFAT)*7.5/8=1920B < 2kB Boards needed: 2 data TOTFED with 2 mezzanines each 2 trigger TOTFED with 3 mezzanines each Saverio Minutoli INFN Genova 27

28 Slow Control Ring architecture O E Conversion Fault repair configuration example. T1 will use the same CMS control ring components (DOHM- CCUM_TOB_TEC) and configuration. The modules shall be connected to guaranty the system redundancy T1 need a DOHM and a loop of 6 CCUM for each arm. Limitations due to the short ring length: Max distance between CCUM modules 50-60cm Total max ring length 2-3m I 2 C line max length??? Saverio Minutoli INFN Genova 28

29 H.V. architecture 2 2 Patch -Panel 3 x R.M. SCADA OPC Server DCS R.M. Patch -Panel 15 SHV 15 SHV Patch -Panel R.M. R.M. 15 SHV Patch -Panel R.M.= 52 Radiall Multipin 15 SHV Patch -Panel R.M. A1733B 28 Channels 3 kv/3 ma or 4 kv/2 ma Saverio Minutoli INFN Genova 29

30 Low Voltages Voltages: -10V, -5V, +5V, +2.5V Current (1/4 T1): CFEC: AFEC: Power Supply: Need to have a local solution. WIENER Saverio Minutoli INFN Genova 30

31 Summary The CSC parameters are well known We are ready to start with the FE electronic prototypes design. VFAT2 can be adopted how complete FE for the CSC anodes wires (only one channel tested): Need an external passive circuit to reduce and adapt the detector signal amplitude. Tests will continue in Genoa, now we are ready to use a new gas mix Ar/CO 2 /CF 4 40/50/10. The AFEC are rad. hard., CFEC can operate up to L=10 33 cm -2 s -1 The VFAT digital is of course used in the cathodes FE electronic chain. The anodes will be used to generate the trigger bits pattern, the VFAT trigger sector logic function is involved. Possible to use the same VFAT mezzanine as T2: We have to check the connectors and the dimensions. Needs to check the Control Ring configuration, in particular the maximum electrical cable connections length. We agree to use the same low voltages power supplies as CMS. Saverio Minutoli INFN Genova 31

32 Extra slides Saverio Minutoli INFN Genova 32

33 CSC transmission line impedance measure Pulse ns Z_anode= W [ R = 115 W/m] Z_cathode= W Saverio Minutoli INFN Genova 33

34 CSC capacitance test-bench Two and four terminals LCR methods Stray and various parasite cap. Use of a guard plate and shielding, to minimize test leads stray cap. and noise pick-up Saverio Minutoli INFN Genova 34

35 Half strip accuracy SERIAL CODE 100 SERIAL CODE 101 N-1 N N+1 N-1 N N+1 SERIAL CODE 110 SERIAL CODE 111 N N+1 N+2 N N+1 N+2 The LCT-COMP allows to identify the charge distribution on CSC to a half strip accuracy. It permits to give the right or left position of an event within a strip. The LCT-COMP logic digitize the position of an event within 2 consecutive strips with a 3 serial bits word. Peaking time adjustable within ns. The serial data stream are unusable in our system, we need a deserializer. The choise could be the ACTEL antifuse programmable devices A54SX32A, tested and qualified up to ~50krad by the INFN-BO group. Saverio Minutoli INFN Genova 35

36 CSC Anode and Cathodes Asymmetric and large distribution charge on cathodes Saverio Minutoli INFN Genova 36

37 Side view Side of a T1 view quarter of a T1 halve Saverio Minutoli INFN Genova 37