Timing Error Detection and Correction using EDC Flip-Flop for SOC Applications

Transcription

1 Timing Error Detection and Correction using EDC Flip-Flop for SOC Applications Mahesh 1, Dr. Baswaraj Gadgay 2 and Zameer Ahamad B 3 1 PG Student Dept. of VLSI Design & Embedded Systems, VTU PG Centre, Kalaburagi. 2 Research Guide and Professor VTU PG Centre, Kalaburagi 3 Assistant Professor Dept. of VLSI Design & Embedded Systems VTU PG Centre, Kalaburagi. Abstract Timing mistakes are an expanding unwavering quality worry in nanometer innovation, increased unpredictability and multi voltage or recurrence ICs. A neighborhood rectification approach and error discovery is presented in this work that is dependent on another piece flipping flip-flop. Whenever, a timing mistake is encountered, it is adjusted by supplementing the yield of the related flip-flop. The hypothesized scheme is portrayed by power necessities and a minimal silicon area contrasted with past outline plans in the open writing. To approve its effectiveness, it has been connected in the outline of a SoC application, while a show adaptation of the same core in a FPGA stage is displayed. Keywords Timing Errors, Error Detection and Correction, System on Chip (SoC), EDAC unit, UART, FPGA. I. INTRODUCTION The timing error is a type of error which causes because of unnecessary delays in the execution of the program. The timing error causes because of many reasons it cause because of scaling in CMOS technology, increase of process variations, due to power supply minimization and due to increasing complexity of modern ICs, these all alter the consistency and fix the errors in the circuit [1][2]. The timing error furthermore causes from different modules like power supply dissemination, coupling noise, jitter and the temperature variations are held responsible for timing mistake era. Transistor maturing modules are likewise influenced on the execution of nanometer circuits that are subsequent in the presence of timing mistakes in the circuit. Timing disappointments in a combinational logic block causes due to the delayed responses. This delayed responses causes due to the wake of activating edge of the clock, the output of combinational block is not obtained because of delayed response of previous block; this causes the timing error in the combinational block. There are many number of error detection techniques used for an error detection and correction. Various error detection techniques have been proposed. The error discovery and correction procedures are separated into 2 sections those in view of flip-flop and the latch based methods. An understood error detection plan depends on utilization of a comparator that is implemented by a basic XOR gate. The hardware comprises of extra memory component in addition to a XOR gate for each memory component (flip-flop or fundamental latch) in the configuration. The auxiliary memory module is timed by an overdue form of the system clock that inputs the primary memory module. The proposed arrangement maintains a strategic distance from additional clock skew impacts and significantly decreases the silicon cost, area and utilization of power giving the identical timing mistake recognition adjustment productivity as in the prior methodologies. Another point of interest of the EDC flip - flop is that the 2 nd XOR gate is not fixed by the info part of the main flip- flop, with the goal that doesn't automatically acquaint an extra postpone with the time basic way under observing, as it is the situation for the extra multiplexer in the Razor flip- All rights Reserved 165

2 In this study, the proposed approach is scrutinized exhaustively and the metastability concept that influences its working is viewed as and an appropriate schema is presented. Furthermore, to corroborate its ability, it has been linked in the context of SoC applications, while presenting the adaptation of the same core in a FPGA stage is demonstrated. II. LITERATURE ANALYSIS Timing mistake recognition and redress procedures is basically partitioned into 2broad classes, they are flip-flop dependent techniques and latch based approaches focusing on the based outlines. In the principal classification, the Razor procedure is the most noticeable one [3]. A. Razor Technique The razor strategy is flip-flop based outline, stage registers are implemented by utilizing the Razor flip- flops. A razor flip- flop comprises of the main scheme flip- flop in conjunction to a MUX, right hand shadow latch along with an XOR gate. The shadow latch catches, with a delay as the fundamental flip- flop, the reactions of the combinational logic. The XOR gate functions like a comparator governs the yields of shadow latch and the primary flip- flop after this time period. If there should arise an occurrence of error discovery, the mistake correction tool is actuated, that diverts the contribution of the main flip- flop to get right info of the shadow latch and provide the following logic phase during the succeeding recovery, clock cycle. B. Time Borrowing and Error Relaying(TIMBER) The TIMBER procedure is likewise a flip-flop based outline. TIMBER [4] is basically a timing error flexibility strategy which masks timing mistakes through acquisition of time from progressive pipeline phases. It deploys an additional latch for each principle framework flip-flop to retest the information with appropriate delay. In this TIMBER proposes a method for web timing mistake resilience that covers timing mistakes by acquiring time from progressive pipeline stages. TIMBER can likewise handle timing mistakes because of moderate changing worldwide varieties that may bring about multi-stage timing mistakes. C. Double Sampling Scheme Alternative double sampling scheme for soft-error versatility is presented in [5] that could be effectively changed to handle timing mistake resistance. It utilizes an additional flip-flop for each framework flip-flop for mistake rectification so that its silicon range cost is restrictive in like manner scenarios. D. Global Reliability Architecture Approach for Logic (GRAAL) In the 2 nd class of latch oriented timing mistake recognition and revision systems, the Graal [6][7] design, which is dependent on XOR comparator for error identification and extra flip-flop per latch is utilized in case of error remedy. E. Razor- II Topology Recently the Razor-II protocol is proposed as in [8] that utilize move identifier for error discovery during the process of mistake correction is carried out via architectural reiteration. Rather than performing both mistake location and amendment in flip-flop, Razor-II implements just recognition in flip-flop, during the revision is carried out via architectural reiteration. This basically permits remarkable lessening among the unpredictability and magnitude of Razor flip-flop, despite the fact that at expense of the expanded IPC punishment while recovery. System replay is a traditional system that frequently as of now exists in high performance microprocessors to support approximate operation, for example, out-of-request execution and branch prediction. III. THE PROPOSED METHOD The proposed EDC flip-flop is depicted in Fig. 1(a) and Fig. 1(b) demonstrates the pulse generator used to produce the clock pulse. This proposed mistake location and redress depends All rights Reserved 166

3 the bit-flipping idea. In the event of mistake discovery in the yield of the flip flop, comparing logical value is asynchronously complemented for error correction. Fig.1 a) Proposed-EDC-FF b) Pulse-generator The Fig. 1(a) demonstrates the new Error Detection and Correction flip- flop (EDC FF) which is reasonable to timing errors. The EDC FF comprises of main flip-flop, aside from the main flip flop, it comprises of 2 XOR gate and latch. The 1 st XOR gate relates the D with F o/p of fundamental flip-flop and result gives to the latch. The latch catches yield of 1 st XOR gate and holds it. The latch bolsters the 2 nd XOR gate at the yield of fundamental flip-flop. Dependent upon the comparative result of the principal XOR gate inside a predefined time interim, either F sign of principle flip-flop or the complement is basically spread to yield Q of EDC flip-flop. The Q signal feed to following resulting logical phase. At first, the yield of the latch Error_F is made 0, since, the course of o/p of the major flip-flop F passed to the o/p of the 2 nd XOR gate and then transforms to the succeeding consequent logical phase. In the errorless scenario, the comparative results are low at the o/p of the main XOR gate on activating the clock-signal (CLK). Theo/p of the primary XOR gate is caught by the latch, in this manner the Q o/p signal gets indistinguishable to the signal F of the fundamental flip flop that conveys exact information. This signal passes the data to the succeeding logical phases S j+1. Nevertheless, during the timing fault in the logical phase S j, a signal arrived lately with the aid of the fundamental flip-flop in the activating side of the clock signal. For this situation timing mistake occurring on the o/p of principle flip-flop and incorrect information is given to succeeding resulting logic phase, S j+1. Furthermore, yield of the principle flip-flop is differs from the information signal worth D, so that first XOR gate identifies the distinction and raises its o/p. Then a latch catches this quality and takes the response and after that 2 nd XOR gate is compared with the latch o/p and the o/p of the fundamental flip-flop along with its o/p is Q, which is basically the complement the signal F, and this Q is passed to the succeeding resulting logic stage S j+1, along these lines EDC FF conveys the right esteem. Importantly, the mistake is privately rectified. A. EDC FLIP-FLOP WITH METASTABILITY DETECTOR Fig. 2 a) EDC-flip- flop with Meta - stability detector b) Meta - stability All rights Reserved 167

4 In nearness of timing faults there is a conceivable that the right however postponed information at D of the primary flip-flop and the signal clock makes the so called "simultaneous moves". This thus may prompt the hold or the set up time infringements in the primary flip-flop. Accordingly the flip-flop would go into a Meta - stable state, wherein the o/p stays amidst the voltage level, nearing to VDD/2. Therefore, voltage levels could be treated as logic low or high with gates which are fed with the flip-flop's o/p or the gates additionally goes into a Meta - stable phase. During this scenario, the primary XOR entryway cannot be effective in rendering the comparative results during the information and o/p of principle flip-flop with a specific end goal to distinguish the relating timing mistake. To overcome from this issue, a Meta - stability sensor is utilized at o/p of the principle flip flop depicted in Fig. 2 (a). At whatever point a Meta - stable phase is watched and then o/p of primary flip-flop gets compelled with corresponding estimation of data at D. Thus primary XOR door identifies a mistake and enacts the error adjustment instrument keeping in mind the end goal to give to the consequent logic stage. At the point when flip-flop functions in Meta - stable phase, a little noise inherent in the available circuit, fits to drive its yield either too low or high based on the polarity associated with the noise. Hence, for such scenarios, the yield of the Meta - stability finder gets initiated and empowers an inverter bearing tri-state configuration that gets compelled with the information signal (D). Tristate inverter basically derives the o/p of the fundamental flip-flop by the quality which correlates this at information D. In this manner mistake is recognized by 1st XOR entryway and error rectification instrument gets initiated. Despite the fact that it is anything but difficult to revise the information at the yield of the primary flip-flop utilizing a tri-state cradle rather than tri-state inverter, this is kept away from in light since it isn t feasible to predict whether the accompanying logical phase has the necessary interval for a right estimation. A straightforward Meta - stability finder is depicted in Fig. 2(b) that is basically dependent on the couple of inverters that gets described with alternate voltage degrees. The main inverter is basically n-dominant and consists of voltage lesser than VDD/2 move voltage category; the2 nd inverter is p-dominant comprises of voltage bigger than VDD/2 move voltage. During the metastable condition of flip-flop where in the o/p near VDD/2, previous inverter gives logically lower reactions. Therefore, the input of NAND gates is increased and the o/p empowers swings too low in order to empower the tri-state inverter. During ordinary conditions, o/p of NAND is constantly in an increased state and the tri-state inverter gets basically inactive. B. DESIGN OF SOC WITH EDAC Fig 3 Block diagram of SoC A typical block diagram of the SoC is depicted in Fig. 3.5, the SoC intended for recognizing and remedying the error that could occur in memory unit because of radiation in lower earth circle (LEO) and owing to the stuck-at shortcomings in the memory units of space stations [9]. The errorless information is passed to the foreordained processor utilizing serial correspondence convention. The amalgamation of error detection and correction (EDAC Unit), encoder, router and the universal asynchronous receiver and transmitter (UART) carries out the mistake recognition and remedy All rights Reserved 168

5 A block diagram of the SoC with EDAC square is depicted in Fig.3.5; the processors are set outside of the SoC. The data is sent from beginning of space station is considered as the contribution to the encoder. Among the space related applications, the computerized information put away in the low earth circle it experiences SEU's in memory chips, these are actually prompted by radiation. Bitflips brought about by SEU s are an understood issue in memory chips and due to this the mistake is presented in framework, consequently we can utilize an error detection and correction block in the SoC for error identifying and remedying. In case of secure transmission of data amongst the router, CPU and its neighborhood RAM, EDC flip- flop is connected during the error discovery and correction unit, hence, errors could be distinguished and revised and resultant yield will be devoid of error. In this way, the resultant errorfree data is passed to the processor, with the goal that it will handle the error less data and is furthermore gather every one of the information flags and deliver the resultant information yield. C. COMPARISION ANALYSISES In this proposed strategy, the flip-flop is supplanted with a new EDC flip-flop contrasted with Razor [3] and time dilation procedures [4], toward the end of the time basic way in a logic state. In Razor and Time Dilation each flip-flop is supplanted with relating error discovery and rectification flip-flop till the nearby clock gating procedures are utilized. Neighborhood clock gating is required to keep away from information irregularity as for error rectification, the information at registers i/p is assessed again in following cycles of the clock. The gating of clock strategies is not ideal because of related clock skew issues. Also, a rapid signal should be appropriated inside entire configuration for mistake recognition, which expands the outline unpredictability and expense. The proposed EDC flip-flop maintains a strategic distance from the additional clock skew impacts and significantly decreases the silicon area power and cost utilization rendering similar timing error identification redress effective like the ones in prior methodologies. An alternate benefit of EDC flip- flop is the 2 nd XOR gate is basically not set on information edge of main flip- flop, with the goal of not unwillingly acquainting an added delay with time basic way under-checking, since, it s situation in case of extra MUX in Razor flip- flop. Our proposed strategy needs extra clock signal for the functioning. As mentioned before, this signal could be privately produced, among every register wherein the timing error security is needed, by clock signal subsequent to the two signals contain similar period. The time dilation and razor methods additionally need additional CLK signal which gets deferred adaptation of clock signal, perhaps with changes in the duty cycles. Despite the fact that in these strategies the supplement of the clock signal can be utilized rather, this will extensively expand issues identified with the hold time issue (extra zone and power utilization prerequisites). Fig 4 The Comparison All rights Reserved 169

6 A.Simulation Results of EDC Flip-Flop International Journal of Modern Trends in Engineering and Research (IJMTER) IV. EXPERIMENTAL RESULTS Fig 5 Simulation Results of EDC flip-flop B.Simulation results of EDC flip- flop using meta - stability detector C. Simulation Results of SOC with EDAC Fig 6 Simulation Results of EDC flip-flop with MD Fig 7 Simulation Results of SOC with EDAC V. CONCLUSION A timing mistake resistance strategy is introduced for enhancing the unwavering quality in flip-flop based nano-meter innovation centers. This misuses another piece flipping flip- flop that gives capacity for the identification purpose, and adjusts numerous timing errors in a circuit, with a period discipline of a solitary clock cycle. Here, the proposed methodology is described with minimal silicon area prerequisites that come with decreased complexity in design and this reduced design complexity also reduces power consumption compared to that of earlier All rights Reserved 170

7 REFERANCES [1] J.W. McPherson, Reliability Challenges for 45nm and Beyond, ACM/IEEE Design Automation Conference, pp , [2] S. Mitra, N. Seifert, M. Zhang, Q. Shi and K. S. Kim, Robust System Design with Built-In Soft-Error Resilience, IEEE Computer, Volume 38, Number 2, pp , [3] T. Austin, D. Blaauw, T. Mudge and K. Flautner, Making Typical Silicon Matter with Razor, IEEE Computer, vol. 37, no. 3, pp , [4] M. Choudhury, V. Chandra, K. Mohanram and R. Aitken, TIMBER: Time Borrowing and Error Relaying for Online Timing Error Resilience, ACM/IEEE Design Automation and Test in Europe Conference, pp , [5] S. Mitra, N. Seifert, M. Zhang, Q. Shi and K. S. Kim, Robust System Design with Built-In Soft-Error Resilience, IEEE Computer, Volume 38, Number 2, pp , [6] M. Nicolaidis, GRAAL: A New Fault Tolerant Design Paradigm for Mitigating the Flaws of Deep Nanometric Technologies, IEEE International Test Conference, p. 4.3, [7] H. Yu, M. Nicolaidis, L. Anghel and N-E. Zergainoh, Efficient Fault Detection Architecture Design of Latch-based Low Power DSP/MCU Processor, IEEE European Test Symposium, pp , [8] S. Das, C. Tokunaga, S. Pant, W-H. Ma, S. Kalaiselvan, K. Lai, D.M. Bull and D.T. Blaauw, Razor II: In Situ Error Detection and Correction for PVT and SER Tolerance, IEEE Journal of Solid-State Circuits, vol. 44, no. 1, pp , [9] journal/fpga implementation of architecture of SoC For space craft All rights Reserved 171