EFFICIENT POWER REDUCTION OF TOPOLOGICALLY COMPRESSED FLIP-FLOP AND GDI BASED FLIP FLOP

Transcription

1 EFFICIENT POWER REDUCTION OF TOPOLOGICALLY COMPRESSED FLIP-FLOP AND GDI BASED FLIP FLOP S.BANUPRIYA 1, R.GOWSALYA 2, M.KALEESWARI 3, B.DHANAM 4 1, 2, 3 UG Scholar, 4 Asst.Professor/ECE 1, 2, 3, 4 P.S.R.RENGASAMY COLLEGE OF ENGINEERING FOR WOMEN ABSTRACT Power consumption is a major problem in modern circuit design, for low power applications. Optimization of power is the important task at the logic level to minimize the power consumption. So the components are designedcarefully in such a way that, they consume less power with high speed. Flip flops are the important elements in all digital design but, consume much power due to the dynamic and static power dissipation. This paper presents a low power Topologically Compressed Flip Flop with comparison of FF using GDI. In the existing method static Topologically Compressed 21-transistor flip flop is proposed. This FF reduces the power consumption by 75% at 0% data activity. The reduction is achieved by merging the logically equivalent transistors. In order to reduce power consumption new method GDI technique is introduced. The performance of TCFF and FF using GDI is designed and the simulation has been performed on the Tanner EDA Tool. An Experimental chip design with 40 nm CMOS technology shows that almost all conventional FF s are replaced by the proposed FF with the same performance and layout area. Key words: low power, Flip Flop, Transistor count. I.INTRODUCTION Power dissipation and consumption is a serious problem in an IC. The four important components involving the power dissipation in integrated circuits. P Total =α C L V DD 2 f clk +V DD (I sc + I st +I leakage ). 2 P Total is the total power dissipation. α C L V DD f clk refers to the power dissipation due to switching activities. WhereC L is the load capacitance, f clk is the clock frequency andα denotes the node transition factor. V DD *I sc Refers to the short circuit power and V DD *I st refers to the Static power dissipation. So while designing an IC, delay, area and transistor count has comes under the primary design goal. In LSI most of the power is dissipated by Flip Flops (FF s). Flip Flops are used as the memory elements which are the basic building blocks of an IC. They are used in many applications such as data storage, counters, frequency division and shift registers etc. The purpose of this paper is to reduce the transistor count, power consumption and cell area. In section II we review existing low power FF s. In section III we show the topologically compressed flip flop with reduction steps. In section IV the power and performance characteristics are shown compared to other FF s. II.EXISTING WORK In this section we analyze the problems of previously described Flip Flops. Fig.1 shows a typical circuit of differential sense amplifier type FF (DiffFF). This FF is very ISSN : Page 87

2 useful to amplify small swing signals. So it is generally used in the output of memory circuit. In this FF still the power reduction is goes down at lower data activity, because these types of circuit have the pre charge operation in every clock low state. Likewise, if we use reduced clock swing, a clock generator and an extra bias circuitry are needed. fig2: XCFF Fig.3 shows adaptive -coupling flip flop (ACFF). In this circuit, commonly used doublechannel transmission gate is replaced by the single-channel transmission gate with dynamic circuit for the data line. It is used to reduce clock related transistor count. Still in this circuit, delay is easily affected by input clock slew variation because different types of singlechannel transmission gates are used in the same data line and connected to the same clock signal. fig1: DiffFF Fig.2 shows a circuitry of cross charge control flip flop (CCFF). This circuit drives output transistor separately in order to reduce the charged and discharged gate capacitance. In actual operation, some of the internal nodes are pre-set with clock signal for the high input data and this operation dissipates extra power to charge and discharge internal nodes. fig3:acff Let us prices the analysis on previously stated low-power FF s. For DiffFF and XCFF, precharge operation is difficult in lower data activity. And for ACFF patience for input clock variation becomes issue to resolve. III.TOPOLOGICALLY FLIP-FLOP COMPRESSED A.TRANSISTOR LEVEL COMPRESSION ISSN : Page 88

3 The FF shown in fig.4 consists of different type of latches in the master and the slave parts.the slave-latch is the reset-set type, but the masterlatch is an asymmetrical single input data type. The feature of this circuit is, it operates in single phase clock signal. Fig.5 shows the transistor level schematic of fig. 4.In this schematic logically equivalent transistors are merged. Fig4: Schematic diagram of proposed FF. Fig6: Transistor merging in PMOS side. Fig5: Transistor level schematic of Fig. 4. For the PMOS side, two transistor pairs in the m1 and s1 blocks in fig5. Can be shared as shown in fig6. When either CP or N3 is low, the shared common node becomes VDD voltage level, and N2 and N5 nodes are controlled by the PMOS transistors N1 and N4 individually. When both CP and N3 is high, both N2 and N5 nodes are pulled down to the VSS by the NMOS transistors. As well as M1 and S1 blocks, two PMOS transistor pairs in M2 and S2 blocks are shared. Fig7: Transistor merging in NMOS side. ISSN : Page 89

4 When CP is low, both nodes in VDD voltage level and either N2 or N3 is ON. When CP is high, each nodeis in independent voltage level shown in fig.9. This process leads to the circuits shown in fig.5. This circuit only contains the 21 transistors. The number of clock related transistors in only three. This reduction method is called as the Topological compression method. The FF in which TC-method is applied is known as the topologically compressed flip-flop. Fig8: Further transistor merging in PMOS side. Fig10: Transistor level schematic of topologically-compressed flip-flop (TCFF). B.OPERATION Fig9: The state of internal nodes. For the NMOS side configuration, transistors of logically equivalent operation can be shared. Two transistors in M1and M2 blocks in fig7 is shared. Transistor in S1 and S2 are shared. Further in the PMOS side, CP-input transistor in S1 and S2 in fig.8can be merged, because N2 and N3 are logically inverted to each other. In fig.10when CP is low; the PMOS transistor connected to CP turns ON and the master latch becomes the data input mode. Both VD1 and VD2 are pulled up to power supply voltage level, and the input data from D is stored in the master latch. When CP is high, the PMOS transistor is connected to CP turns OFF and the NMOS transistor connected to CP turns ON, and the slave latch becomes data output mode. At the condition the data in the master latch is transferred to the slave latch, and then outputted to Q. IV.PERFORMANCE COMPARISION The performance of TCFF is explained by SPICE simulation with 40nm CMOS technology. Table.1 shows the power consumption of various flip-flops. TCFF consumes least power among the other conventional FF. It is possible to operate down ISSN : Page 90

5 to 0.6V supply voltage. TCFF operates with single phase clock signal TCFF does not requires clock buffer. Flip Flop Transistor count Power in mw DiffFF XCFF M. Mahesh Kumar, N. Chandra Sekhar., Design and Analysis of Low Power Pulse Triggered Flip flop Based on Single Feed-Through Scheme., International Journal of Engineering Research Volume No.3 Issue No: Special 2, 22 March 2014 N. Karthika, S. Jayanthy., Design of Hybrid Pulsed Flip Flop Featuring Embedded logic. IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 4, Issue 2, Ver. I (Mar-Apr. 2014) ACFF FF without TC Table.1 Power analysis of various FF V.CONCLUSION An extremely low power FFusing topological compression and GDI technique is proposed. The TCFF has the lowest power dissipation compared to the other low-power FF`s. The very small no of transistors are connected to the clock signal reduces the power hugely. The power dissipation of the TCFF is 75% lower than the other flip flops. VI.REFERENCE TCFF Kawai, Takayama, Masumi, Kikuchi, Itoh, Ogawa, Tanaka, Suzuki and Ugawa, A fully static topologically compressed 21-transistor flip-flop, IEEE journal of solid-state circuits, vol. 49, no. 11, november CH.Vijayalakshmi, S. M.Vijayalakshmi Low Power Pass Transistor Logic Flip Flop International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering,Vol. 3, Issue 5, May 2014 Meghana Pelleti, T. Krishna Murthy and K. Neelima., Low-Power and Low- Area Dual Dynamic Node Hybrid Flip- Flop Featuring Efficient Embedded Logic for Low Power CMOS VLSI 120nm Technology., International Journal of Emerging Technology and Advanced Engineering,Volume 4, Issue 8, August 2014 B.Kavitha devi and P.V.K.Chaitanya., Power Efficient Enhanced Dual Dynamic Hybrid Flip-flop.,International Journal of VLSI and Embedded Systems-IJVES Vol 05, Article 09442, September 2014 A.Lakshminarayanan, N.Jayapal, R.Shankar, D.Karthikeyan4, T.Yuvaraja5., Conditional Clocking Flip-flop For Low Power High-speed Mobile Application Soc., International Journal of Advanced Research in ISSN : Page 91

6 Computer and Communication Engineering Vol. 3, Issue 11, November 2014 Kalarikkal Absel, Lijo Manuel,and R. K. Kavitha., Low-Power Dual Dynamic Node Pulsed Hybrid Flip-Flop Featuring Efficient Embedded Logic IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 21, No. 9, September 2013 K.G.Sharma Tripti Sharma B.P.Singh Manisha Sharma Modified SET D-Flip Flop Design for Low-Power VLSI Applications in IEEE Transaction On Low Power VLSI 2011 N. Nedovic and V.-G. Oklobdzija, Hybrid latch flip-flop with improved power efficiency, in Proc. Symp. Integr. Circuits Syst. Design, 2000, pp ISSN : Page 92

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