AN1141 PI3USB30532 and PI3USB31532 Application Note for Type-C Applications Paul Li, PTC, Diodes Incorporated

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1 AN4 PI3USB3053 and PI3USB353 for Type-C Applications Paul Li, PTC, Diodes Incorporated Table of Contents.0 Introduction.0 Why passive MUX (PI3USB3X53) is better than active MUX in notebook design? 3.0 PI3USB3X53 in source-host: notebook, tablet, AIO and desktop PC 4.0 What are the recommended maximum traces for PI3USB3X53 in Intel notebook design? 5.0 PI3USB3X53 in sink-device: Monitor and HDTV 6.0 PI3USB3X53 in sink-device: Docking station 7.0 The IC control of PI3USB3X Power and power de-coupling 9.0 Layout guideline 0.0 Appendix: application reference schematics AN4 Rev of 7 April 08

2 .0 Introduction AN4 The PI3USB3053 and PI3USB353 Type-C cross switch family is developed using cutting-edge technology to achieve high performance of DP., DP.3, USB 3.0, USB 3. signals in type-c applications. PI3USB3X53 is fully compliant to Type-C specifications. PI3USB3X53 was first to the market and successfully designed in many varying applications, such as notebooks, tablets, AIO, PCs, monitors, HDTVs, docking stations, etc. The PI3USB3X53 was also designed in Intel reference schematic and designed in Intel customer reference demonstration tablet..0 Why passive MUX (PI3USB3X53) is better than active MUX in notebook design? The market needs for notebooks are: 6-8 hours in battery running time ability to boot-up 6-8 days after power-off Intel mobile CPU/chipset can now achieve 6W power consumption, thus: The ~0.4W to ~0.6W power consumption from an active MUX is too high and not acceptable Especially when compared to the <0.003W power consumption from PI3USB3X53, which is a 99% power saving compared to an active MUX 3.0 PI3USB3X53 in Source-Host: Notebook, Tablet, AIO and Desktop PC Figure. PI3USB3053, PI3USB353 in Notebook, Tablet, All-in-One and Desktop PC Intel is a trademark of Intel Corporation in the U.S. and/or other countries AN4 Rev of 7 April 08

3 N/A is for not applicable AN4 Rev 3 of 7 AN4 4.0 What are the recommended maximum traces for PI3USB3X53 in Intel notebook design? 4. DP., DP.3 In Intel Kaby Lake design guideline, Intel recommends a maximum 8 DP. trace without passive MUX and 4. with passive MUX as to pass a DP. compliance test. Intel deducted 3.9 trace from the 8 DP. trace for the passive MUX, which is conservative for a high performance passive MUX such as PI3USB3X53, as explained in figure, figure 3a, figure 3b and in table below. Based on the PI3USB3053 DP. eye compliance test results in figure 3a and figure 3b, as well the trace data in figure and table, it s recommended as below. Maximum 6. trace for DP. (5.4Gbps) path, as: Intel DP. source PI3USB3X53 Type-C connector Maximum 4.0 trace for DP.3 (8Gbps) path, as: Intel DP.3 source PI3USB353 Type-C connector (Assuming the layout and schematics are as recommended as using 90Ω traces without chokes, etc., and in reasonable system conditions) 4. USB3.0, USB3. Based on the PI3USB3053 USB 3.0 eye compliance test results in figure 4a and figure 4b, as well the trace data in figure and table, we recommend the following guidelines: Maximum 8.5 trace for USB3.0 (5Gbps) path, as: USB3.0 host PI3USB3X53 Type-C connector Maximum 4.5 trace for USB3. (0Gbps) path, as: USB3. host PI3USB353 Type-C connector (Assuming the layout and schematics are as recommended below and in reasonable system conditions) Table - The insertion loss of PI3USB3X53 versus Intel trace board Insertion Per inch PI3USB3053 PI3USB353 loss of : 353: trace on Insertion Insertion Intel loss loss trace board Insertion loss at 5Gbps (USB3.0) Insertion loss at 5.4Gbps (DP.) Insertion loss at 8Gbps (DP.3) Insertion loss at 0Gbps 3053: equivalent trace length (loss of 3053/ trace) -.db -0.70db -.db.7 (.db/0.70 db) -.3db -0.77db -.3db.69 (.3db/0.77 db) 3053: good-max DP. trace in Intel 8 trace topology 353: equivalent trace length (loss of 353/ trace) N/A -.06db.5 (.06db/0.7 0db) 6.3 ( ) -.3db.60 (.3db/0.7 7db) -3.db -.07db N/A N/A N/A -.63db.5 (.63db/.0 7db) -3.96db -.3db N/A N/A N/A -.68db.7 (.68db/.3 db) 353: goodmax DP. trace in Intel 8 trace topology N/A 6.40 ( ) (USB3.) Table the insertion loss of the 3 FR4 differential trace was measured using Intel trace board and Agilent N530A 0GHz Network Analyzer, as setup in Figure. Note: The data above is not linear, because the performances vary with different switch-routings and signaltypes between PI3USB3053 and PI3USB353, while PI3USB353 has better performance than PI3USB3053 mostly at higher speed N/A N/A April 08

4 AN4 4.3 The insertion loss of 3 differential trace on Intel trace board Figure. The insertion loss of 3 FR4 differential trace on Intel trace board is measured using Agilent N530A 0GHz Network Analyzer (chart by James Liu) AN4 Rev 4 of 7 April 08

5 AN4 4.4 The PI3USB3053 Intel Haswell MB DP. eye compliance test result Figure 3a. The eye of DP. (5.4Gbps) compliance test using PI3USB3053 setup (figure 3b) with Asus H97i-plus MB (Intel Haswell) and 7 trace passed the DP. HBR compliance test 3. using Tektronix scope at 400mV, 3.5db pre-emphasis. The upper waveform is at T3 with emulation cable in scope. The lower waveform is at T without emulation cable (waveform by Jerry Chou). ASUS Trademark is either a US registered trademark or trademark of Asustek Computer Inc. in the United States and/or other countries AN4 Rev 5 of 7 April 08

6 AN4 4.5 Test Setup Figure 3b. The test setup of PI3USB3053 with 7 trace ( ) using Intel Haswell DP. source passed DP. (5.4Gbps) eye compliance test 3. as in figure 3a AN4 Rev 6 of 7 April 08

7 AN4 Figure 4a. The Tx and Rx eyes passed the USB 3.0 (5Gbps) compliance test at the USB 3.0 connector of notebook (Intel Haswell) without PI3USB3053 EV board. To be compared to figure 4b with PI3USB3053 EVB (waveform by Jerry Chou) AN4 Rev 7 of 7 April 08

8 AN4 Figure 4b. The Tx and Rx eyes passed USB 3.0 (5Gbps) compliance test with 0. trace ( ) using notebook (Intel Haswell) and PI3USB3053 EV board. To be compared to figure 4a without PI3USB3053 EV board (waveform by Jerry Chou). AN4 Rev 8 of 7 April 08

9 AN4 5.0 PI3USB3X53 in Sink-device: Monitor and HDTV Figure 5. PI3USB3053, PI3USB353 in monitor and HDTV No active DP re-driver and USB3.0 re-driver needed in type-c MUX (PI3USB3053) or between the switches in cascading (PI3USB3053, PI3WVR4, PI3PCIE34). o Because there are sufficient total source and sink equalization, as: Up to 9db output pre-emphasis (equalization) in DP source and USB3.0 Tx Up to 9db input equalization in DP scalar and USB3.0 Rx receiver. o The total 8db equalization in source and sink is sufficient to compensate the estimated total insertion loss from the topology in figure 5: Max 7.7db from total 0 traces Max 4db from m type-cable Max.5db from PI3USEB3053 Max.5db from PI3WVR4 or PI3PCIE34 AN4 Rev 9 of 7 April 08

10 AN4 6.0 PI3USB3X53 in Sink-device: Docking Station 7.0 The IC Control of PI3USB3X53 PI3USB3X53 has total three IC registers: Conf [:0], which is mapped between the IC control signals and the configuration tables (source, sink) as in figure-7. When using IC interface to control PI3USB3X53, the IC controller (in PD or MCU) will need sending total three bytes to PI3USB3053 in sequence as: Start # byte for address as (assuming A_A0 set to 00, while last 0 for write) # byte for chip-id as fixed #3 byte for Conf [:0] control as (assuming Conf [:0]= as for USB3+DPx swapped) Stop (must have stop, otherwise uncertainty may occur) AN4 Rev 0 of 7 April 08

11 AN4 Figure 7. The IC-control of the configuration table for source-sink (source-sink tables are the same) IC-controls PI3USB3053 in real application For both source and sink applications, when a type-c plug is plugging into the source or sink type-c connectors with PI3USB3053 and PD, the IC controller (in PD or MCU) shall IC-control PI3USB3053 as: DPx4 only, non-swap: Start (last 0 for write) stop DPx4 only, swapped: Start stop USB3.0 only, non-swap: Start stop USB3.0 only, swapped: Start stop USB3+DPx, non-swap: Start stop USB3+DPx, swapped: Start stop AN4 Rev of 7 April 08

12 AN4 8.0 Power and Power De-coupling Use 0.µf in size of 040 for all the V DD (any power pins) pins of the IC device, as close to the V DD pins as possible, within -3mm if feasible. Use dedicated V DD and planes for to minimize the jitters coupled between channel trough power sources. 9.0 Layout Guideline 9. Recommend 90Ω differential impedance trace for differential DP and USB 3.0 signals Figure 8. The trace width and clearance Use mils for trace-space-trace for the micro-strip lines (the traces on top and bottom layers) for 90Ω differential impedance. Use mils for trace-space-trace for the strip-lines (the traces inside layers) for 90Ω differential impedance. Use FR4. Using standard 4 to 8 layers stack-up with 0.06 inch thick PCB. For micro-strip lines, using ½ OZ Cu plated is ok. For strip-lines in 6 plus players, using OZ Cu is better. The trace length miss-matching shall be less than 5 mils for the + and traces in the same pairs More pair-to-pair spacing for minimal crosstalk Target differential Zo of 90Ω ±5% AN4 Rev of 7 April 08

13 AN4 9. The PCB Layers Stackup No new PCB technology required. Use FR4 is fine. Using standard 4 to 8 layers stack-up with 0.06 inch thick PCB. For micro strip lines, using ½ OZ Cu plated is ok. For strip line in 6 plus players, using OZ Cu is better. Figure 9. The Stackup Stackup Plane Material Thickness (mil) Solder mask Mask paint. Signal Copper.9 Prepreg Vcc Copper.4 Core 47 Vss Copper.4 Prepreg Signal Copper.9 Solder mask Mask paint. Total 6.4 AN4 Rev 3 of 7 April 08

14 AN4 9.3 The Layout Guidance for the Trace Routings Figure 0. The layout guidance for the trace routings Don t use EMI chokes, because PI3USB3053 and PI3USB353 are passive switches not having EMI issues. The differential traces shall be away from the strong EMI source and devices, such as TTL, switchingpower traces and devices, with at least 30mil to 50mil space. No other components shall piggy ride on the differential traces. AN4 Rev 4 of 7 April 08

15 RX- RX RX+ RX+ RX+/TX+ RX-/TX- AUX+ AUX- P DP0- DP0+ CONF/SDA CONF/SCL CONF0/A RX RX+ RX- RX- RX+/TX+ RX-/TX- AUX+ AUX- P DP0- DP0+ CONF/SDA CONF/SCL CONF0/A AN4 0.0 Appendix: Application Reference Schematics C7 6-C8 3 ar e " must hav e" to p reve nt non- DP c omp lian t 3. 3V s igna ls from plu g-i n as rea l-s een- case. C 0u 0.u C3 0.u C4 0.u C5 C6 0.u 0.u C7 0.u C8 0.u R3 C9 NC R6 4.7K CONF/SDA CONF/SCL CONF0/A NC (for IC) R4 R5 NC (for IC) Vbus control Source charging circuit No -cho kes bet ween and type -C conn ecto r, beca use is a pa ssiv e sw itc h wi thou t E MI i ssue. Use 0.uf if output swing >.V or using re-drivers DP source D0+ D0- AUX- R7 0 R9 0 R0 0 D3+ D3- AUX+ R8 0 R 0 R 0 R3 0 R4 0 C39 0.u C40 0.u MODE DP+ DP- DP+ DP- DP3+ DP3- TX+/RX+ TX-/RX- A0 U 34 RX+/TX+ 33 RX-/TX- 3 3 TX+/RX+ 30 TX-/RX- 9 8 TX+/RX+ 7 TX-/RX- 6 5 RX+/TX+ 4 RX-/TX- 3 SBU/SBU SBU/SBU ADDR0 PI3USB3053 C3 0.33u RX+ C3 0.33u RX- C33 0.u TX+ C34 0.u TX- C35 0.u TX+ C36 0.u TX- C u RX+ C u RX- 00uf C30 J B A B A TX+ B3 RX+ A0 TX- B4 RX- A9 B5 A8 CC B6 SBU A7 B7 A6 B8 A5 SBU B9 CC A4 B0 A3 RX- B TX- A RX+ B TX+ A USB3 controller TX+ TX- RX+ RX- C4 0.u C4 0.u R7 00K R8 00K R5 M R6 M R9 R3 R30 00K 00K 00K R3 00K Layout Type-C Recep. KUSB-8-A-P ST, USB /- RX+ RX- TX+ TX- TVS CONF/ CONF/ CONF0/ SDA SCL A See source truth table for the control of CONF[:0] PD controller Vbus control CC CC TX+ TX- RX+ RX- TVS PI3USB3053 reference schematic for source application Contact Diodes local sales for TVS PI3USB3053 DFP-source reference schematic for type-c PD/DP/ALT application C5 5-C6, C 63 are "mu st h ave" to pre vent no n-dp co mpli ant 3.3 V si gnal s fr om plug -in as real -se en-c ase. C 0u 0.u C C3 0.u 0.u C4 C5 C6 0.u 0.u 0.u R C7 C8 NC 0.u R4 4.7K CONF/SDA CONF/SCL CONF0/A NC (for IC) R R3 NC (for IC) Vbus control Sink charging circuit No -cho kes bet ween and typ e-c conn ect or, bec ause is a pa ssiv e s witc h wi tho ut E MI i ssu e. DP receiver D0+ D0- D3+ D3- AUX+ C7 0.u AUX- C9 0.u ADDR0 MODE DP+ DP- DP+ DP- DP3+ DP3- TX+/RX+ TX-/RX- A0 U 34 RX+/TX+ 33 RX-/TX- 3 3 TX+/RX+ 30 TX-/RX- 9 8 TX+/RX+ 7 TX-/RX- 6 5 RX+/TX+ 4 RX-/TX- 3 SBU/SBU SBU/SBU PI3USB3053 J B A B A TX+ B3 RX+ A0 TX- B4 RX- A9 B5 A8 CC B6 SBU A7 B7 A6 B8 A5 SBU B9 CC A4 B0 A3 RX- B TX- A RX+ B TX+ A C0 0.u TX+ C 0.u TX- C 0.33uRX+ C3 0.33uRX- C4 0.33uRX+ C5 0.33uRX- C6 0.u TX+ C8 0.u TX- 00uf C9 USB3 controller TX+ TX- RX+ RX- C0 0.u C 0.u R7 M R8 M R5 M R6 M R9 R R0 R 00K 00K 00K 00K Layout Type-C Recep. USB /- TX+ TX- RX+ RX- TVS CONF/ CONF/ CONF0/ Vbus SDA SCL A control See sink truth table for the control of CONF[:0] PD controller PI3USB3053 reference schematic for sink application CC CC RX+ RX- TVS TX+ TX- Contact Diodes local sales for TVS PI3USB3053 UFP-sink reference schematic for type-c PD/DP/ALT application AN4 Rev 5 of 7 April 08

16 RX+ RX+ RX- RX RX+/TX+ RX-/TX- AUX+ AUX- P DP0- DP0+ CONF/SDA CONF/SCL CONF0/A RX+ RX- RX+ RX RX+/TX+ RX-/TX- AUX+ AUX- P DP0- DP0+ CONF/SDA CONF/SCL CONF0/A AN4 C 8-C 5 are "m ust hav e" t o p reve nt non- DP comp lia nt 3.3V si gnal s f rom plu g-in as rea l-s een- cas e. C64 0u 0.u C65 0.u C66 0.u C67 C68 0.u 0.u C69 0.u C70 0.u R47 C7 NC R50 4.7K CONF/SDA CONF/SCL CONF0/A NC (for IC) R48 R49 NC (for IC) Vbus control Source charging circuit No -cho kes bet wee n 3 53 and ty pe-c co nnec tor, be cau se 3 53 is a pa ssi ve s wit ch w ith out EMI iss ue. Use 0.uf if output swing >.V or using re-drivers DP source USB3 controller D0+ D0- AUX- D3+ J4 B A B A TX+ B3 RX+ A0 TX- B4 RX- A9 B5 A8 CC B6 SBU A7 B7 A6 B8 A5 SBU B9 CC A4 B0 A3 RX- B TX- A RX+ B TX+ A Type-C Recep. KUSB-8-A-P ST, D3- R5 0 R5 0 R53 0 R56 0 R57 0 R58 0 AUX+ C8 0.u TX+ R54 0 R55 0 C8 0.u R59 NC C83 0.u C84 0.u R60 70K ADDR MODE DP+ DP- DP+ DP- DP3+ DP3- TX+/RX+ TX-/RX- MODE A0 U4 RX+/TX+ RX-/TX- TX+/RX+ TX-/RX- TX+/RX+ TX-/RX- RX+/TX+ RX-/TX- SBU/SBU SBU/SBU PI3USB353 R63 00K R64 00K TX- RX+ RX- C u RX+ C u RX- C75 0.u TX+ C76 0.u TX- C77 0.u TX+ C78 0.u TX- C u RX+ C u RX- R6 R6 M M R65 R67 R66 R68 00K 00K 00K 00K Layout 00uf C7 USB /- RX+ RX- TX+ TX- TVS CONF/ CONF/ CONF0/ SDA SCL A See source truth table for the control of CONF[:0] PD controller Vbus control CC CC TX+ TX- RX+ RX- TVS PI3USB353 reference schematic for source application Contact Diodes local sales for TVS PI3USB353 DFP-source reference schematic for type-c PD/DP/ALT application C43 C44 0u 0.u 0.u C45 C46 C47 0.u 0.u 0.u C48 C49 C50 R33 NC 0.u 0.u R36 CONF/SDA CONF/SCL 4.7K CONF0/A NC (for IC) R34 R35 NC (for IC) C9 7-C 03, C0 5 ar e "m ust hav e" t o p reve nt n on- DP c ompl ian t 3. 3V si gnal s fr om plug -in as real -see n-c ase. Vbus control Sink charging circuit No -cho kes bet ween 35 3 and type -C conn ecto r, beca use 3 53 is a pa ssiv e sw itc h wi thou t E MI i ssue. DP receiver D0+ D0- D3+ D3- AUX+ C59 0.u AUX- C6 0.u R37 NC ADDR0 C5 0.u TX+ C53 0.u TX- C u RX+ C u RX- C u RX+ C u RX- C58 0.u TX+ C60 0.u TX- MODE DP+ DP- DP+ DP- DP3+ DP3- TX+/RX+ TX-/RX- MODE A0 U3 34 RX+/TX+ 33 RX-/TX- 3 3 TX+/RX+ 30 TX-/RX- 9 8 TX+/RX+ 7 TX-/RX- 6 5 RX+/TX+ 4 RX-/TX- 3 SBU/SBU SBU/SBU PI3USB353 00uf C5 J3 B A B A TX+ B3 RX+ A0 TX- B4 RX- A9 B5 A8 CC B6 SBU A7 B7 A6 B8 A5 SBU B9 CC A4 B0 A3 RX- B TX- A RX+ B TX+ A USB3 controller TX+ TX- RX+ RX- C6 0.u C63 0.u R4 70K R40 M R4 M R38 M R39 M R43 R45 R44 R46 00K 00K 00K 00K Layout Type-C Recep. USB /- TX+ TX- RX+ RX- TVS CONF/ CONF/ CONF0/ SDA SCL A See sink truth table for the control of CONF[:0] PD controller Vbus control CC CC RX+ RX- TX+ TX- TVS PI3USB353 reference schematic for sink application Contact Diodes local sales for TVS PI3USB353 UFP-sink reference schematic for type-c PD/DP/ALT application AN4 Rev 6 of 7 April 08

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