with Internal Decoding and Quiet Series I O Buffers

Transcription

1 MCM28F064ACH 64-Mbit (8-Mbit x 8) Flash Memory Module with Internal Decoding and Quiet Series I O Buffers General Description The MCM28F064ACH is a bit flash memory module organized as 8 pages with bytes per page Utilizing Intel s FlashFileTM Memory the MCM28F064ACH is a high density nonvolatile memory solution for military aerospace storage applications The fast access time low power consumption small size and unique architecture provide a smaller lighter more reliable lower power and higher performance alternative to traditional rotating disk and magnetic tape technologies The module includes eight 28F008SA flash memories along with National Semiconductor s FACT Quiet SeriesTM I O buffers and decoding logic The MCM28F064ACH is offered in a 44-lead hermetic package Both through-hole and surface mount lead configurations are available Connection Diagram Features PRELIMINARY July 1995 Y Read access time of 200 ns over the military temperature range (b55 C toa125 C) Y Utilizes Intel s FlashFile architecture with kbytes block (8 pages with 16 blocks per page) Y Automated byte write block erase capability can be executed simultaneously in all 8 pages greatly improving average write erase cycle times Y Utilizes National s FACT Quiet Series technology for ultra low switching noise and superior dynamic threshold performance Y TTL compatible inputs Y TRI-STATE outputs with g24 ma static drive g50 ma dynamic drive Y Hermetically sealed integral substrate package Y DIP package standard (surface mount packages also available) Pin Names A 0 A 22 D 0 A 7 CE WE RE DE V PP V CC GND NC Description Address Inputs Data Inputs Outputs Chip Enable Input (Active LOW) Write Enable Input (Active LOW) Read Enable Input (Active LOW) Data Enable Input (Active LOW) Erase Write Power Supply Device Power Supply Ground No Connection MCM28F064ACH 64-Mbit (8-Mbit x 8) Flash Memory Module with Internal Decoding and Quiet Series I O Buffers TL Z TRI-STATE is a registered trademark of National Semiconductor Corporation FACTTM and FACT Quiet SeriesTM are trademarks of National Semiconductor Corporation FlashFileTM is a trademark of Intel Corporation C1995 National Semiconductor Corporation TL Z RRD-B30M115 Printed in U S A

2 Functional Description The MCM28F064ACH is a bit (64-Mbit) flash memory module organized as 8 pages with bytes per page The module is segmented into 128 blocks Each 64 kbyte block is individually erasable A memory map is included in this document A Command User Interface (CUI) serves as the interface between the system controller and the MCM28F064ACH Automation of the byte write and block erase functions allow these commands to be executed using a two-write command sequence to the CUI An internal Write State Machine (WSM) automatically executes the algorithms timings and verifications necessary for the byte write and block erase operations thereby relieving the system controller of these tasks A Status Register indicates the status of the WSM and flags the successful completion of the byte write block erase operations Writing of memory data is performed in byte increments typically within 9 ms A block erase operation erases one of the 128 blocks of memory typically within 1 6 seconds without affecting the contents of the remaining blocks Byte write and block erase operations can be executed simultaneously in all 8 pages greatly improving average write erase cycle times An erase suspend mode allows the system software to suspend the block erase operation in order to read data or execute code from any other block of the module For detailed information regarding the operation of the 28F008SA Flash Memory refer to the Intel datasheet (order number ) Bus Operations Mode CE RE WE DE D n Standby HIGH Immaterial Immaterial HIGH High Impedance Output Disable Immaterial Immaterial Immaterial HIGH High Impedance Read LOW LOW HIGH LOW D OUT Write LOW HIGH LOW LOW D IN Command Definitions Command Bus Cycles Notes First Bus Cycle Read Array Reset 1 Write X FFH Second Bus Cycle Operation Address Data Operation Address Data Intelligent Identifier Write X 90H Read IA IID Read Status Register 2 2 Write X 70H Read X SRD Clear Status Register 1 Write X 50H Erase Setup Erase Confirm 2 1 Write BA 20H Write BA D0H Erase Suspend Erase Resume 2 Write X B0H Write X D0H Byte Write Setup Write Write WA 40H Write WA WD Alternative Byte Write Setup Write Write WA 10H Write WA WD Note 1 IA e Identifier Address 00H for flash memory manufacturer code 01H for device code BA e Address within the block being erased WA e Address of memory location to be written Note 2 SRD e Data read from Status Register WD e Data to be written at location WA Data is latched on the rising edge of WE IID e Data read from Intelligent Identifiers Note 3 Following the Intelligent Identifier command two read operations access the flash memory manufacturer and device codes The flash memory manufacturer code (89H) is read when A 0 e L and the device code (A2H) is read when A 0 e H Note 4 Either 40H or 10H are recognized by the WSM as the Byte Write Setup command 2

3 Status Register Definitions Status Register Bit 7 e Write State Machine Status 1 e Ready 0 e Busy Status Register Bit 6 e Erase Suspend Status 1 e Erase Suspended 0 e Erase in Progress Completed Status Register Bit 5 e Erase Status 1 e Error in Block Erasure 0 e Successful Block Erasure Status Register Bit 4 e Byte Write Status 1 e Error in Byte Write 0 e Successful Byte Write Status Register Bit 3 e V PP Status 1 e V PP Low Detect Operation Abort 0 e V PP OK Status Register Bits 2 0 e Reserved for Future Use These bits are reserved for future use and should be masked out when polling the Status Register Block Diagram TL Z

4 Memory Map 4FFFFF 4F0000 4EFFFF 4E0000 4DFFFF 4D0000 4CFFFF 4C0000 4BFFFF 4B0000 4AFFFF 4A FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFFF 5F0000 5EFFFF 5E0000 5DFFFF 5D0000 5CFFFF 5C0000 5BFFFF 5B0000 5AFFFF 5A FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFFF 6F0000 6EFFFF 6E0000 6DFFFF 6D0000 6CFFFF 6C0000 6BFFFF 6B0000 6AFFFF 6A FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFFF 7F0000 7EFFFF 7E0000 7DFFFF 7D0000 7CFFFF 7C0000 7BFFFF 7B0000 7AFFFF 7A FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF Page 4 Page 5 Page 6 Page 7 4

5 Memory Map (Continued) 0FFFFF 0F0000 0EFFFF 0E0000 0DFFFF 0D0000 0CFFFF 0C0000 0BFFFF 0B0000 0AFFFF 0A FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFFF 1F0000 1EFFFF 1E0000 1DFFFF 1D0000 1CFFFF 1C0000 1BFFFF 1B0000 1AFFFF 1A FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFFF 2F0000 2EFFFF 2E0000 2DFFFF 2D0000 2CFFFF 2C0000 2BFFFF 2B0000 2AFFFF 2A FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFFF 3F0000 3EFFFF 3E0000 3DFFFF 3D0000 3CFFFF 3C0000 3BFFFF 3B0000 3AFFFF 3A FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF Page 0 Page 1 Page 2 Page 3 5

6 Absolute Maximum Ratings (Note 1) Device Power Supply Voltage (V CC ) b0 5V to a7 0V Erase Write Power Supply Voltage (V PP ) b0 5V to a7 0V DC Input Diode Current (I IK ) V I eb0 5V b20 ma V I e V CC a 0 5V a20 ma DC Output Diode Current (I OK ) V O eb0 5V b20 ma V O e V CC a 0 5V a20 ma DC Output Voltage (V O ) b0 5V to V CC a 0 5V DC Output Source Sink Current (I O ) g50 ma DC V CC or Ground Current Per Output Pin (I CC or I GND ) g50 ma Thermal Resistance Junction to Case (i JC ) 3 8 C W Junction Temperature (T J ) a150 C Storage Temperature (T STG ) b65 Ctoa150 C DC Electrical Characteristics Symbol Parameter Conditions Recommended Operating Conditions Device Power Supply Voltage (V CC ) 4 5V to 5 5V Erase Write Power Supply Voltage (V PP ) (Note 2) Read-Only Operations (V PPL ) 0 0V to 6 5V Erase Write Operations (V PPH ) 11 4V to 12 6V Input Voltage (V I ) 0VtoV CC Output Voltage (V O ) 0VtoV CC Case Operating Temperature (T C ) b55 Ctoa125 C Minimum Input Edge Rate (dv dt) 125 mv ns V IN from 0 8V to 2 0V V CC 4 5V 5 5V Maximum Static Output Current High Level (I OH ) b24 ma Low Level (I OL ) a24 ma Note 1 Absolute maximum ratings are those values beyond which damage to the device may occur The databook specifications should be met without exception to ensure that the system design is reliable over its power supply temperature and output input loading variables National does not recommend operation of this module outside the datasheet specifications Note 2 Block erases byte writes are inhibited when V PP e V PPL and not guaranteed in the range between V PPL and V PPH V CC (V) Guaranteed Limits T C eb55 Ctoa125 C V IH Minimum High Input Voltage V IL Maximum Low Input Voltage V OH Minimum High Output I OUT eb50 ma Voltage V IN e V IL or V OH I OUT eb24 ma V OL Maximum Low Output I OUT eb50 ma Voltage V IN e V IL or V OH I OUT e 24 ma I IN Maximum Input Current V IN e V CC or GND 5 5 g15 0 ma I OLD Minimum Dynamic V OLD e 1 65V Max ma I OHD Output Current V OHD e 3 85V Min 5 5 b50 ma I OZT Maximum I O Current V I O e V CC or GND 5 5 g10 0 ma I CCT Maximum V CC Current per V IN e V CC b 2 1V Input at TTL HIGH Units ma I CCS Maximum V CC Standby CE e DE e V CC ma Current V V V V V V I CCR Maximum V CC Read f e 5 MHz Current I CCW Maximum V CC Byte Write Single Byte Write Operation Current 8 Simultaneous Byte Write Operations Maximum test duration 2 0 ms one output loaded at a time ma ma ma 6

7 DC Electrical Characteristics (Continued) Symbol Parameter Conditions I CCE Maximum V CC Block Single Block Erase Operation Erase Current 8 Simultaneous Block Erase Operations I CCES Maximum V CC Erase Single Block Erase Operation Suspend Current Suspended 8 Block Erase Operations Simultaneously Suspended V CC Guaranteed Limits (V) T C eb55 Ctoa125 C Units ma ma ma ma I PPS Maximum V PP Standby V PP e V CC ma Current I PPW Maximum V PP Byte Write Single Byte Write Operation Current V PP e 12 6V ma 8 Simultaneous Byte Write Operations I PPE Maximum V PP Block Single Block Erase Operation Erase Current 8 Simultaneous Block Erase Operations I PPES Maximum V PP Erase Single Block Erase Operation Suspend Current Suspended Capacitance 8 Block Erase Operations Simultaneously Suspended ma ma ma ma ma ma Symbol Parameter Conditions Typ Units C IN Input Pin Capacitance (All Inputs Except CE) V CC e 5 0V 20 pf Input Pin Capacitance (CE Input) V CC e 5 0V 40 pf C I O Input Output Pin Capacitance V CC e 5 0V 25 pf AC Electrical Characteristics Read Operations Symbol Parameter V CC (V) Guaranteed Limits T C eb55 Ctoa125 C t AVAV Read Cycle Time 5 0 g 10% 200 ns t AVQV Address to Output Delay 5 0 g 10% 200 ns t ELQV CE to Output Delay 5 0 g 10% 200 ns t GLQX DE to Output Low Z 5 0 g 10% 20 ns t RLQV RE to Output Delay 5 0 g 10% 100 ns t GHQZ DE to Output High Z 5 0 g 10% 20 ns t OH Output Hold from Addresses CE 5 0 g 10% 0 ns or RE Change Whichever is First Min Max Units 7

8 AC Electrical Characteristics WE Controlled Write Operations Guaranteed Limits Symbol Parameter V CC (V) T C eb55 Ctoa125 C Units Min Max t AVAV Write Cycle Time 5 0 g 10% 200 ns t ELWL CE Setup to WE Going Low 5 0 g 10% 45 ns t AVWL A 20 A 22 Setup to WE Going Low 5 0 g 10% 25 ns t AVWH A 0 A 19 Setup to WE Going High 5 0 g 10% 60 ns t GLWH DE Setup to WE Going High 5 0 g 10% 70 ns t DVWH Data Setup to WE Going High 5 0 g 10% 60 ns t VPWH V PP Setup to WE Going High 5 0 g 10% 150 ns t WHEH CE Hold from WE High 5 0 g 10% 15 ns t WHAX Address Hold from WE High 5 0 g 10% 25 ns t WHGH DE Hold from WE High 5 0 g 10% 20 ns t WHDX Data Hold from WE High 5 0 g 10% 20 ns t WLWH WE Pulse Width Low 5 0 g 10% 50 ns t WHWL WE Pulse Width High 5 0 g 10% 40 ns t WHQV1 Duration of Byte Write Operation 5 0 g 10% ms t WHQV2 Duration of Block Erase Operation 5 0 g 10% s t WHGL Write Recovery before Read 5 0 g 10% 0 ms t QVVL V PP Hold from Valid Status Register Data 5 0 g 10% 0 ms Excludes system-level overhead (completion of operation determined by polling status register) AC Electrical Characteristics CE Controlled Write Operations Guaranteed Limits Symbol Parameter V CC (V) T C eb55 Ctoa125 C Units Min Max t AVAV Write Cycle Time 5 0 g 10% 200 ns t WLEL WE Setup to CE Going Low 5 0 g 10% 0 ns t AVEL A 20 A 22 Setup to CE Going Low 5 0 g 10% 0 ns t AVEH A 0 A 19 Setup to CE Going High 5 0 g 10% 40 ns t GLEH DE Setup to CE Going High 5 0 g 10% 50 ns t DVEH Data Setup to CE Going High 5 0 g 10% 40 ns t VPEH V PP Setup to CE Going High 5 0 g 10% 150 ns t EHWH WE Hold from CE High 5 0 g 10% 40 ns t EHAX Address Hold from CE High 5 0 g 10% 40 ns t EHGH DE Hold from CE High 5 0 g 10% 40 ns t EHDX Data Hold from CE High 5 0 g 10% 40 ns t ELEH CE Pulse Width Low 5 0 g 10% 65 ns t EHEL CE Pulse Width High 5 0 g 10% 35 ns t EHQV1 Duration of Byte Write Operation 5 0 g 10% ms t EHQV2 Duration of Block Erase Operation 5 0 g 10% s t EHGL Write Recovery before Read 5 0 g 10% 0 ms t QVVL V PP Hold from Valid Status Register Data 5 0 g 10% 0 ms Excludes system-level overhead (completion of operation determined by polling status register) 8

9 AC Testing Load Circuit TL Z When measuring OFF-to-LOW and LOW-to-OFF parameters V L e 2 c V CC When measuring all other parameters V L e open C L Includes jig and probe capacitance AC Reference Waveforms TL Z Input rise and fall times (10% 90%) e 3ns Timing Diagram Read Operations TL Z

10 Timing Diagram WE Controlled Write Operations TL Z Timing Diagram CE Controlled Write Operations TL Z

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12 MCM28F064ACH 64-Mbit (8-Mbit x 8) Flash Memory Module with Internal Decoding and Quiet Series I O Buffers Physical Dimensions (inches) 44-Lead Hermetic Dual-In-Line Custom ISPMCM-DC Package NS Package Number IS44A LIFE SUPPORT POLICY NATIONAL S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or 2 A critical component is any component of a life systems which (a) are intended for surgical implant support device or system whose failure to perform can into the body or (b) support or sustain life and whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system or to affect its safety or with instructions for use provided in the labeling can effectiveness be reasonably expected to result in a significant injury to the user National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd Japan Ltd 1111 West Bardin Road Fax (a49) th Floor Straight Block Tel Arlington TX cnjwge tevm2 nsc com Ocean Centre 5 Canton Rd Fax Tel 1(800) Deutsch Tel (a49) Tsimshatsui Kowloon Fax 1(800) English Tel (a49) Hong Kong Fran ais Tel (a49) Tel (852) Italiano Tel (a49) Fax (852) National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications