CSE140L: Components and Design Techniques for Digital Systems Lab. CPU design and PLDs. Tajana Simunic Rosing. Source: Vahid, Katz
|
|
- Dorthy Wilkinson
- 5 years ago
- Views:
Transcription
1 CSE140L: Components and Design Techniques for Digital Systems Lab CPU design and PLDs Tajana Simunic Rosing Source: Vahid, Katz 1
2 Lab #3 due Lab #4 CPU design Today: CPU design - lab overview PLDs Updates & Outline 2
3 CSE140L: Components and Design Techniques for Digital Systems Lab Lab #4 CPU design Tajana Simunic Rosing Source: Vahid, Katz 3
4 Simple in-order processor Objectives: Implementing a real processor on FPGA (challenging but fun!) Challenges: Design and implement the processor data path Design and implement the processor control units Make the whole thing work
5 Processor overview Control unit PC Address Instruction Memory Register File ALU 7-bit instruction
6 Instruction format Each Instruction has a size of 7 bits Instruction format 3-bit OP code 4-bit data Determines the instruction (i.e 100 = add)
7 Instruction set R3 = R1 + R2
8 Holds the whole program instructions Implemented as a ROM Can hold up to 16 instructions Instruction memory module instruction_rom(addr, inst); input [3:0] addr; output [6:0] inst; wire [6:0] memory [15:0]; assign memory[0] = 7'b ; assign memory[1] = 7'b ; assign memory[2] = 7'b ; assign memory[3] = 7'b ; assign memory[4] = 7'b ; assign memory[5] = 7'b ; assign memory[6] = 7'b ; assign memory[7] = 7'b ; assign memory[8] = 7'b ; assign memory[9] = 7'b ; assign memory[10] = 7'b ; assign memory[11] = 7'b ; assign memory[12] = 7'b ; assign memory[13] = 7'b ; assign memory[14] = 7'b ; assign memory[15] = 7'b ; assign inst = memory[addr]; endmodule Address Instruction Memory 7-bit instruction
9 Program counter Generate the next instruction address For non-control flow instructions PC = PC + 1 (Enable signal = 1) clk enable reset load For control flow instructions Branch address PC = Branch address (load signal = 1) PC Address to memory Think about how to implement this unit
10 Instruction decoder Decodes the instruction by reading the 3-bit OP code bits from the memory Generate the control signals to the rest of the processor (i.e. tells the ALU to add when there is an ADD instruction) Instruction 3bit OP Control unit Data path control signals Think about how to implement this unit
11 Register file Contains THREE 4-bit registers and the Flag bit Each register is made up of D-FF Control signals Challenge: Determine the appropriate interfacing with the rest of you processor Instruction (bit0-bit3) Register File ALU Compare flag ALU output
12 ALU Control Performs Addition, Multiplication and comparison Two input 4-bit operands Outputs: 4-bit results and 1-bit Compare Implement it! Input operands ALU Results Interfacing
13 Sample code
14 Test your design Testing phase is essential to ensure that your design is a bug free Here are some tips Generate test cases for all the instructions Generate test cases with various input conditions Generate test cases for some interesting combinations of instructions (e.g. control flow with non-control flow instructions) Good luck and have FUN!
15 CSE140L: Components and Design Techniques for Digital Systems Lab PLDs (cont.) Tajana Simunic Rosing Source: Xilinx 15
16 Programmable Logic Devices (PLD) PLDs combine PLA/PAL with memory and other advanced structures Similar to PLA/PAL, hence Field-Programmable Gate Arrays Types: Antifuse PLDs EPLD & EEPLD FPGAs with RAMs FPGA with processing Digital Signal Processing General purpose CPU 16
17 Field-Programmable Gate Arrays Logic blocks To implement combinational and sequential logic Interconnect Wires to connect inputs and outputs to logic blocks I/O blocks Special logic blocks at periphery of device for external connections Key questions: How to make logic blocks programmable? How to connect the wires? After the chip has been manufactured
18 Actel s Axcelerator Family Antifuse PLDs Antifuse: open when not programmed Low resistance when programmed 18
19 Actel s Axcelerator C-Cell C-Cell Basic multiplexer logic plus more inputs and support for fast carry calculation Carry connections are direct and do not require propagation through the programmable interconnect
20 Actel s Accelerator R-Cell R-Cell Core is D flip-flop Muxes for altering the clock and selecting an input Feed back path for current value of the flip-flop for simple hold Direct connection from one C-cell output of logic module to an R-cell input; Eliminates need to use the programmable interconnect Interconnection Fabric Partitioned wires Special long wires
21 Altera s EEPLD Altera s MAX 7k Block Diagram Global Routing: Programmable Interconnect Array Logic Array Blocks 21
22 EEPLD Altera s MAX 7k Logic Block 22
23 SRAM based PLD Altera s Flex 10k Block Diagram 23
24 SRAM based PLD Altera s Flex 10k Logic Array Block (LAB) 24
25 SRAM based PLD Altera s Flex 10k Logic Element (LE) 25
26 Slew Rate Control Passive Pull-Up, Pull-Down Vcc CLB CLB Switch Matrix D Q Output Buffer Pad CLB CLB Q D Delay Input Buffer Programmable Interconnect I/O Blocks (IOBs) C1 C2 C3 C4 H1 DIN S/R EC S/R Control G4 G3 G2 G1 F4 F3 F2 F1 G Func. Gen. F Func. Gen. H Func. Gen. DIN F' G' H' G' H' DIN F' G' H' 1 S/R Control SD D Q EC RD SD D Q Y Configurable Logic Blocks (CLBs) EC K H' F' 1 RD X
27 FPGA with DSP Altera s Stratix II: Block Diagram 28
28 FPGA with DSP Altera s Stratix II: DSP Detail 29
29 FPGA with General Purpose CPU & Analog Actel s Fusion Family Diagram FPGA with ARM 7 CPU and Analog Components 30
30 Discrete Gates Packaged Logic PLAs Programmable Logic Summary Ever more general architectures of programmable combinational + sequential logic and interconnect Altera Actel Xilinx
CSE140L: Components and Design Techniques for Digital Systems Lab. FSMs. Tajana Simunic Rosing. Source: Vahid, Katz
CSE140L: Components and Design Techniques for Digital Systems Lab FSMs Tajana Simunic Rosing Source: Vahid, Katz 1 Flip-flops Hardware Description Languages and Sequential Logic representation of clocks
More informationL11/12: Reconfigurable Logic Architectures
L11/12: Reconfigurable Logic Architectures Acknowledgements: Materials in this lecture are courtesy of the following people and used with permission. - Randy H. Katz (University of California, Berkeley,
More informationL12: Reconfigurable Logic Architectures
L12: Reconfigurable Logic Architectures Acknowledgements: Materials in this lecture are courtesy of the following sources and are used with permission. Frank Honore Prof. Randy Katz (Unified Microelectronics
More informationIntroduction Actel Logic Modules Xilinx LCA Altera FLEX, Altera MAX Power Dissipation
Outline CPE 528: Session #12 Department of Electrical and Computer Engineering University of Alabama in Huntsville Introduction Actel Logic Modules Xilinx LCA Altera FLEX, Altera MAX Power Dissipation
More informationExamples of FPLD Families: Actel ACT, Xilinx LCA, Altera MAX 5000 & 7000
Examples of FPL Families: Actel ACT, Xilinx LCA, Altera AX 5 & 7 Actel ACT Family ffl The Actel ACT family employs multiplexer-based logic cells. ffl A row-based architecture is used in which the logic
More informationWhy FPGAs? FPGA Overview. Why FPGAs?
Transistor-level Logic Circuits Positive Level-sensitive EECS150 - Digital Design Lecture 3 - Field Programmable Gate Arrays (FPGAs) January 28, 2003 John Wawrzynek Transistor Level clk clk clk Positive
More informationField Programmable Gate Arrays (FPGAs)
Field Programmable Gate Arrays (FPGAs) Introduction Simulations and prototyping have been a very important part of the electronics industry since a very long time now. Before heading in for the actual
More informationMarch 13, :36 vra80334_appe Sheet number 1 Page number 893 black. appendix. Commercial Devices
March 13, 2007 14:36 vra80334_appe Sheet number 1 Page number 893 black appendix E Commercial Devices In Chapter 3 we described the three main types of programmable logic devices (PLDs): simple PLDs, complex
More informationRELATED WORK Integrated circuits and programmable devices
Chapter 2 RELATED WORK 2.1. Integrated circuits and programmable devices 2.1.1. Introduction By the late 1940s the first transistor was created as a point-contact device formed from germanium. Such an
More informationRead-only memory (ROM) Digital logic: ALUs Sequential logic circuits. Don't cares. Bus
Digital logic: ALUs Sequential logic circuits CS207, Fall 2004 October 11, 13, and 15, 2004 1 Read-only memory (ROM) A form of memory Contents fixed when circuit is created n input lines for 2 n addressable
More informationDIGITAL CIRCUIT LOGIC UNIT 9: MULTIPLEXERS, DECODERS, AND PROGRAMMABLE LOGIC DEVICES
DIGITAL CIRCUIT LOGIC UNIT 9: MULTIPLEXERS, DECODERS, AND PROGRAMMABLE LOGIC DEVICES 1 Learning Objectives 1. Explain the function of a multiplexer. Implement a multiplexer using gates. 2. Explain the
More informationCAD for VLSI Design - I Lecture 38. V. Kamakoti and Shankar Balachandran
1 CAD for VLSI Design - I Lecture 38 V. Kamakoti and Shankar Balachandran 2 Overview Commercial FPGAs Architecture LookUp Table based Architectures Routing Architectures FPGA CAD flow revisited 3 Xilinx
More information9 Programmable Logic Devices
Introduction to Programmable Logic Devices A programmable logic device is an IC that is user configurable and is capable of implementing logic functions. It is an LSI chip that contains a 'regular' structure
More informationLecture 2: Basic FPGA Fabric. James C. Hoe Department of ECE Carnegie Mellon University
18 643 Lecture 2: Basic FPGA Fabric James. Hoe Department of EE arnegie Mellon University 18 643 F17 L02 S1, James. Hoe, MU/EE/ALM, 2017 Housekeeping Your goal today: know enough to build a basic FPGA
More informationFPGA Design. Part I - Hardware Components. Thomas Lenzi
FPGA Design Part I - Hardware Components Thomas Lenzi Approach We believe that having knowledge of the hardware components that compose an FPGA allow for better firmware design. Being able to visualise
More informationReconfigurable Architectures. Greg Stitt ECE Department University of Florida
Reconfigurable Architectures Greg Stitt ECE Department University of Florida How can hardware be reconfigurable? Problem: Can t change fabricated chip ASICs are fixed Solution: Create components that can
More informationCSE140: Components and Design Techniques for Digital Systems. More D-Flip-Flops. Tajana Simunic Rosing. Sources: TSR, Katz, Boriello & Vahid
CSE140: Components and esign Techniques for igital Systems More -Flip-Flops Tajana Simunic Rosing Where we are now. What we covered last time: SRAM cell, SR latch, latch, -FF What we ll do next: -FF review,
More informationChapter 7 Memory and Programmable Logic
EEA091 - Digital Logic 數位邏輯 Chapter 7 Memory and Programmable Logic 吳俊興國立高雄大學資訊工程學系 2006 Chapter 7 Memory and Programmable Logic 7-1 Introduction 7-2 Random-Access Memory 7-3 Memory Decoding 7-4 Error
More informationLecture 6: Simple and Complex Programmable Logic Devices. EE 3610 Digital Systems
EE 3610: Digital Systems 1 Lecture 6: Simple and Complex Programmable Logic Devices MEMORY 2 Volatile: need electrical power Nonvolatile: magnetic disk, retains its stored information after the removal
More informationMicroprocessor Design
Microprocessor Design Principles and Practices With VHDL Enoch O. Hwang Brooks / Cole 2004 To my wife and children Windy, Jonathan and Michelle Contents 1. Designing a Microprocessor... 2 1.1 Overview
More informationEN2911X: Reconfigurable Computing Topic 01: Programmable Logic. Prof. Sherief Reda School of Engineering, Brown University Fall 2014
EN2911X: Reconfigurable Computing Topic 01: Programmable Logic Prof. Sherief Reda School of Engineering, Brown University Fall 2014 1 Contents 1. Architecture of modern FPGAs Programmable interconnect
More informationFPGA Design with VHDL
FPGA Design with VHDL Justus-Liebig-Universität Gießen, II. Physikalisches Institut Ming Liu Dr. Sören Lange Prof. Dr. Wolfgang Kühn ming.liu@physik.uni-giessen.de Lecture Digital design basics Basic logic
More informationIE1204 Digital Design F11: Programmable Logic, VHDL for Sequential Circuits
IE1204 Digital Design F11: Programmable Logic, VHDL for Sequential Circuits Elena Dubrova KTH/ICT/ES dubrova@kth.se This lecture BV pp. 98-118, 418-426, 507-519 IE1204 Digital Design, HT14 2 Programmable
More informationComputer Systems Architecture
Computer Systems Architecture Fundamentals Of Digital Logic 1 Our Goal Understand Fundamentals and basics Concepts How computers work at the lowest level Avoid whenever possible Complexity Implementation
More informationSequential Logic. Introduction to Computer Yung-Yu Chuang
Sequential Logic Introduction to Computer Yung-Yu Chuang with slides by Sedgewick & Wayne (introcs.cs.princeton.edu), Nisan & Schocken (www.nand2tetris.org) and Harris & Harris (DDCA) Review of Combinational
More informationCombinational vs Sequential
Combinational vs Sequential inputs X Combinational Circuits outputs Z A combinational circuit: At any time, outputs depends only on inputs Changing inputs changes outputs No regard for previous inputs
More informationRegister Transfer Level (RTL) Design Cont.
CSE4: Components and Design Techniques for Digital Systems Register Transfer Level (RTL) Design Cont. Tajana Simunic Rosing Where we are now What we are covering today: RTL design examples, RTL critical
More informationCSE 140 Exam #3 Tajana Simunic Rosing
CSE 140 Exam #3 Tajana Simunic Rosing Winter 2010 Do not start the exam until you are told to. Turn off any cell phones or pagers. Write your name and PID at the top of every page. Do not separate the
More informationIE1204 Digital Design. F11: Programmable Logic, VHDL for Sequential Circuits. Masoumeh (Azin) Ebrahimi
IE1204 Digital Design F11: Programmable Logic, VHDL for Sequential Circuits Masoumeh (Azin) Ebrahimi (masebr@kth.se) Elena Dubrova (dubrova@kth.se) KTH / ICT / ES This lecture BV pp. 98-118, 418-426, 507-519
More informationCDA 4253 FPGA System Design FPGA Architectures. Hao Zheng Dept of Comp Sci & Eng U of South Florida
CDA 4253 FPGA System Design FPGA Architectures Hao Zheng Dept of Comp Sci & Eng U of South Florida FPGAs Generic Architecture Also include common fixed logic blocks for higher performance: On-chip mem.
More informationDesigning for High Speed-Performance in CPLDs and FPGAs
Designing for High Speed-Performance in CPLDs and FPGAs Zeljko Zilic, Guy Lemieux, Kelvin Loveless, Stephen Brown, and Zvonko Vranesic Department of Electrical and Computer Engineering University of Toronto,
More informationCOE328 Course Outline. Fall 2007
COE28 Course Outline Fall 2007 1 Objectives This course covers the basics of digital logic circuits and design. Through the basic understanding of Boolean algebra and number systems it introduces the student
More informationLogic Design II (17.342) Spring Lecture Outline
Logic Design II (17.342) Spring 2012 Lecture Outline Class # 03 February 09, 2012 Dohn Bowden 1 Today s Lecture Registers and Counters Chapter 12 2 Course Admin 3 Administrative Admin for tonight Syllabus
More informationSlide Set 6. for ENCM 369 Winter 2018 Section 01. Steve Norman, PhD, PEng
Slide Set 6 for ENCM 369 Winter 2018 Section 01 Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary February 2018 ENCM 369 Winter 2018 Section
More informationRegister Files and Memories
Register Files and Memories ECE 554 Digital Engineering Laboratory C. R. Kime 2/18/2002 Register Files and Memories Register Files Issues and Objectives Register File Concepts Implementation of Register
More informationCSE 140 Exam #3 Solution Tajana Simunic Rosing
CSE 140 Exam #3 Solution Tajana Simunic Rosing Winter 2010 Do not start the exam until you are told to. Turn off any cell phones or pagers. Write your name and PID at the top of every page. Do not separate
More informationChapter Contents. Appendix A: Digital Logic. Some Definitions
A- Appendix A - Digital Logic A-2 Appendix A - Digital Logic Chapter Contents Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic A. Introduction A.2 Combinational
More informationPROGRAMMABLE ASIC LOGIC CELLS
ASICs...THE COURSE ( WEEK) PROGRAABLE ASIC LOGIC CELLS 5 Key concepts: basic logic cell multiplexer-based cell look-up table (LUT) programmable array logic (PAL) influence of programming technology timing
More informationSequential Logic Design CS 64: Computer Organization and Design Logic Lecture #14
Sequential Logic Design CS 64: Computer Organization and Design Logic Lecture #14 Ziad Matni Dept. of Computer Science, UCSB Administrative Only 2.5 weeks left!!!!!!!! OMG!!!!! Th. 5/24 Sequential Logic
More informationL14: Quiz Information and Final Project Kickoff. L14: Spring 2004 Introductory Digital Systems Laboratory
L14: Quiz Information and Final Project Kickoff 1 Quiz Quiz Review on Monday, March 29 by TAs 7:30 P.M. to 9:30 P.M. Room 34-101 Quiz will be Closed Book on March 31 st (during class time, Location, Walker
More informationCSE115: Digital Design Lecture 23: Latches & Flip-Flops
Faculty of Engineering CSE115: Digital Design Lecture 23: Latches & Flip-Flops Sections 7.1-7.2 Suggested Reading A Generic Digital Processor Building Blocks for Digital Architectures INPUT - OUTPUT Interconnect:
More informationLogic Devices for Interfacing, The 8085 MPU Lecture 4
Logic Devices for Interfacing, The 8085 MPU Lecture 4 1 Logic Devices for Interfacing Tri-State devices Buffer Bidirectional Buffer Decoder Encoder D Flip Flop :Latch and Clocked 2 Tri-state Logic Outputs
More informationModeling Digital Systems with Verilog
Modeling Digital Systems with Verilog Prof. Chien-Nan Liu TEL: 03-4227151 ext:34534 Email: jimmy@ee.ncu.edu.tw 6-1 Composition of Digital Systems Most digital systems can be partitioned into two types
More information6.3 Sequential Circuits (plus a few Combinational)
6.3 Sequential Circuits (plus a few Combinational) Logic Gates: Fundamental Building Blocks Introduction to Computer Science Robert Sedgewick and Kevin Wayne Copyright 2005 http://www.cs.princeton.edu/introcs
More informationPrinciples of Computer Architecture. Appendix A: Digital Logic
A-1 Appendix A - Digital Logic Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic A-2 Appendix A - Digital Logic Chapter Contents A.1 Introduction A.2 Combinational
More informationDIGITAL SYSTEM FUNDAMENTALS (ECE421) DIGITAL ELECTRONICS FUNDAMENTAL (ECE422) LATCHES and FLIP-FLOPS
COURSE / CODE DIGITAL SYSTEM FUNDAMENTALS (ECE421) DIGITAL ELECTRONICS FUNDAMENTAL (ECE422) LATCHES and FLIP-FLOPS In the same way that logic gates are the building blocks of combinatorial circuits, latches
More informationLecture 10: Programmable Logic
Lecture 10: Programmable Logic We ve spent the past couple of lectures going over some of the applications of digital logic And we can easily think of more useful things to do like having a 7-segment LED
More informationECE 250 / CPS 250 Computer Architecture. Basics of Logic Design ALU and Storage Elements
ECE 25 / CPS 25 Computer Architecture Basics of Logic esign ALU and Storage Elements Benjamin Lee Slides based on those from Andrew Hilton (uke), Alvy Lebeck (uke) Benjamin Lee (uke), and Amir Roth (Penn)
More informationHigh Performance Carry Chains for FPGAs
High Performance Carry Chains for FPGAs Matthew M. Hosler Department of Electrical and Computer Engineering Northwestern University Abstract Carry chains are an important consideration for most computations,
More informationEE 447/547 VLSI Design. Lecture 9: Sequential Circuits. VLSI Design EE 447/547 Sequential circuits 1
EE 447/547 VLSI esign Lecture 9: Sequential Circuits Sequential circuits 1 Outline Floorplanning Sequencing Sequencing Element esign Max and Min-elay Clock Skew Time Borrowing Two-Phase Clocking Sequential
More informationDesign for Testability
TDTS 01 Lecture 9 Design for Testability Zebo Peng Embedded Systems Laboratory IDA, Linköping University Lecture 9 The test problems Fault modeling Design for testability techniques Zebo Peng, IDA, LiTH
More informationChapter. Sequential Circuits
Chapter Sequential Circuits Circuits Combinational circuit The output depends only on the input Sequential circuit Has a state The output depends not only on the input but also on the state the circuit
More informationCS/ECE 250: Computer Architecture. Basics of Logic Design: ALU, Storage, Tristate. Benjamin Lee
CS/ECE 25: Computer Architecture Basics of Logic esign: ALU, Storage, Tristate Benjamin Lee Slides based on those from Alvin Lebeck, aniel, Andrew Hilton, Amir Roth, Gershon Kedem Homework #3 ue Mar 7,
More informationIntroduction to Digital Logic Missouri S&T University CPE 2210 Exam 3 Logistics
Introduction to Digital Logic Missouri S&T University CPE 2210 Exam 3 Logistics Egemen K. Çetinkaya Egemen K. Çetinkaya Department of Electrical & Computer Engineering Missouri University of Science and
More informationAdvanced Devices. Registers Counters Multiplexers Decoders Adders. CSC258 Lecture Slides Steve Engels, 2006 Slide 1 of 20
Advanced Devices Using a combination of gates and flip-flops, we can construct more sophisticated logical devices. These devices, while more complex, are still considered fundamental to basic logic design.
More informationEE178 Spring 2018 Lecture Module 5. Eric Crabill
EE178 Spring 2018 Lecture Module 5 Eric Crabill Goals Considerations for synchronizing signals Clocks Resets Considerations for asynchronous inputs Methods for crossing clock domains Clocks The academic
More informationTestability: Lecture 23 Design for Testability (DFT) Slide 1 of 43
Testability: Lecture 23 Design for Testability (DFT) Shaahin hi Hessabi Department of Computer Engineering Sharif University of Technology Adapted, with modifications, from lecture notes prepared p by
More information3/5/2017. A Register Stores a Set of Bits. ECE 120: Introduction to Computing. Add an Input to Control Changing a Register s Bits
University of Illinois at Urbana-Champaign Dept. of Electrical and Computer Engineering ECE 120: Introduction to Computing Registers A Register Stores a Set of Bits Most of our representations use sets
More informationSequencing. Lan-Da Van ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall,
Sequencing ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2013 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Outlines Introduction Sequencing
More informationLecture 10: Sequential Circuits
Introduction to CMOS VLSI esign Lecture 10: Sequential Circuits avid Harris Harvey Mudd College Spring 2004 1 Outline Floorplanning Sequencing Sequencing Element esign Max and Min-elay Clock Skew Time
More informationLab #12: 4-Bit Arithmetic Logic Unit (ALU)
Lab #12: 4-Bit Arithmetic Logic Unit (ALU) ECE/COE 0501 Date of Experiment: 4/3/2017 Report Written: 4/5/2017 Submission Date: 4/10/2017 Nicholas Haver nicholas.haver@pitt.edu 1 H a v e r PURPOSE The purpose
More information11. Sequential Elements
11. Sequential Elements Jacob Abraham Department of Electrical and Computer Engineering The University of Texas at Austin VLSI Design Fall 2017 October 11, 2017 ECE Department, University of Texas at Austin
More informationObjectives. Combinational logics Sequential logics Finite state machine Arithmetic circuits Datapath
Objectives Combinational logics Sequential logics Finite state machine Arithmetic circuits Datapath In the previous chapters we have studied how to develop a specification from a given application, and
More informationIntegrated circuits/5 ASIC circuits
Integrated circuits/5 ASIC circuits Microelectronics and Technology Márta Rencz Department of Electron Devices 2002 1 Subjects Classification of Integrated Circuits ASIC cathegories 2 Classification of
More informationEECS150 - Digital Design Lecture 3 Synchronous Digital Systems Review. Announcements
EECS150 - Digital Design Lecture 3 Synchronous Digital Systems Review September 1, 2011 Elad Alon Electrical Engineering and Computer Sciences University of California, Berkeley http://www-inst.eecs.berkeley.edu/~cs150
More informationEECS150 - Digital Design Lecture 18 - Circuit Timing (2) In General...
EECS150 - Digital Design Lecture 18 - Circuit Timing (2) March 17, 2010 John Wawrzynek Spring 2010 EECS150 - Lec18-timing(2) Page 1 In General... For correct operation: T τ clk Q + τ CL + τ setup for all
More informationEECS150 - Digital Design Lecture 2 - CMOS
EECS150 - Digital Design Lecture 2 - CMOS January 23, 2003 John Wawrzynek Spring 2003 EECS150 - Lec02-CMOS Page 1 Outline Overview of Physical Implementations CMOS devices Announcements/Break CMOS transistor
More informationCSE 352 Laboratory Assignment 3
CSE 352 Laboratory Assignment 3 Introduction to Registers The objective of this lab is to introduce you to edge-trigged D-type flip-flops as well as linear feedback shift registers. Chapter 3 of the Harris&Harris
More informationCHAPTER1: Digital Logic Circuits
CS224: Computer Organization S.KHABET CHAPTER1: Digital Logic Circuits 1 Sequential Circuits Introduction Composed of a combinational circuit to which the memory elements are connected to form a feedback
More informationCS 261 Fall Mike Lam, Professor. Sequential Circuits
CS 261 Fall 2018 Mike Lam, Professor Sequential Circuits Circuits Circuits are formed by linking gates (or other circuits) together Inputs and outputs Link output of one gate to input of another Some circuits
More informationECE 263 Digital Systems, Fall 2015
ECE 263 Digital Systems, Fall 2015 REVIEW: FINALS MEMORY ROM, PROM, EPROM, EEPROM, FLASH RAM, DRAM, SRAM Design of a memory cell 1. Draw circuits and write 2 differences and 2 similarities between DRAM
More informationXC4000E and XC4000X Series. Field Programmable Gate Arrays. Low-Voltage Versions Available. XC4000E and XC4000X Series. Features
book 1 XC000E and XC000X Series Field Programmable Gate Arrays November 10, 1997 (Version 1.) 1 * Product Specification XC000E and XC000X Series Features Note: XC000 Series devices described in this data
More informationContents Slide Set 6. Introduction to Chapter 7 of the textbook. Outline of Slide Set 6. An outline of the first part of Chapter 7
CM 69 W4 Section Slide Set 6 slide 2/9 Contents Slide Set 6 for CM 69 Winter 24 Lecture Section Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary
More informationEE178 Lecture Module 4. Eric Crabill SJSU / Xilinx Fall 2005
EE178 Lecture Module 4 Eric Crabill SJSU / Xilinx Fall 2005 Lecture #9 Agenda Considerations for synchronizing signals. Clocks. Resets. Considerations for asynchronous inputs. Methods for crossing clock
More informationComputer Architecture and Organization
A-1 Appendix A - Digital Logic Computer Architecture and Organization Miles Murdocca and Vincent Heuring Appendix A Digital Logic A-2 Appendix A - Digital Logic Chapter Contents A.1 Introduction A.2 Combinational
More informationUnit 11. Latches and Flip-Flops
Unit 11 Latches and Flip-Flops 1 Combinational Circuits A combinational circuit consists of logic gates whose outputs, at any time, are determined by combining the values of the inputs. For n input variables,
More informationFPGA Implementation of Sequential Logic
ECE 428 Programmable ASIC Design FPGA Implementation of Sequential Logic Haibo Wang ECE Department Southern Illinois University Carbondale, IL 62901 8-1 Sequential Circuit Model Combinational Circuit:
More informationReconfigurable FPGA Implementation of FIR Filter using Modified DA Method
Reconfigurable FPGA Implementation of FIR Filter using Modified DA Method M. Backia Lakshmi 1, D. Sellathambi 2 1 PG Student, Department of Electronics and Communication Engineering, Parisutham Institute
More informationL14: Final Project Kickoff. L14: Spring 2006 Introductory Digital Systems Laboratory
L14: Final Project Kickoff 1 Schedule - I Form project teams this week (nothing to turn in) Project Abstract (Due April 10 th in 38-107 by 1PM) Start discussing project ideas with the 6.111 staff Each
More informationL13: Final Project Kickoff. L13: Spring 2005 Introductory Digital Systems Laboratory
L13: Final Project Kickoff 1 Schedule Project Abstract (Due April 4 th in class) Start discussing project ideas with the 6.111 staff Abstract should be about 1 page (clearly state the work partition) a
More informationLecture 23 Design for Testability (DFT): Full-Scan
Lecture 23 Design for Testability (DFT): Full-Scan (Lecture 19alt in the Alternative Sequence) Definition Ad-hoc methods Scan design Design rules Scan register Scan flip-flops Scan test sequences Overheads
More informationBUSES IN COMPUTER ARCHITECTURE
BUSES IN COMPUTER ARCHITECTURE The processor, main memory, and I/O devices can be interconnected by means of a common bus whose primary function is to provide a communication path for the transfer of data.
More informationInvestigation of Look-Up Table Based FPGAs Using Various IDCT Architectures
Investigation of Look-Up Table Based FPGAs Using Various IDCT Architectures Jörn Gause Abstract This paper presents an investigation of Look-Up Table (LUT) based Field Programmable Gate Arrays (FPGAs)
More informationLogic Design. Flip Flops, Registers and Counters
Logic Design Flip Flops, Registers and Counters Introduction Combinational circuits: value of each output depends only on the values of inputs Sequential Circuits: values of outputs depend on inputs and
More informationEE 459/500 HDL Based Digital Design with Programmable Logic. Lecture 9 Field Programmable Gate Arrays (FPGAs)
EE 459/5 HDL Based Digital Design with Programmable Logic Lecture 9 Field Programmable Gate Arrays (FPGAs) Read before class: Chapter 3 from textbook Overview FPGA Devices ASIC vs. FPGA FPGA architecture
More informationElectrical and Telecommunications Engineering Technology_TCET3122/TC520. NEW YORK CITY COLLEGE OF TECHNOLOGY The City University of New York
NEW YORK CITY COLLEGE OF TECHNOLOGY The City University of New York DEPARTMENT: SUBJECT CODE AND TITLE: COURSE DESCRIPTION: REQUIRED: Electrical and Telecommunications Engineering Technology TCET 3122/TC
More informationWELCOME. ECE 2030: Introduction to Computer Engineering* Richard M. Dansereau Copyright by R.M. Dansereau,
CHAPTER I- CHAPTER I WELCOME TO ECE 23: Introduction to Computer Engineering* Richard M. Dansereau rdanse@pobox.com Copyright by R.M. Dansereau, 2-2 * ELEMENTS OF NOTES AFTER W. KINSNER, UNIVERSITY OF
More informationFPGA and CPLD Architectures: A Tutorial
F I E L D - P R O G R A M M A B L E D E V I C E S FPGA and CPLD Architectures: A Tutorial RECENTLY, the development of new types of sophisticated fieldprogrammable devices (FPDs) has dramatically changed
More informationSolution to Digital Logic )What is the magnitude comparator? Design a logic circuit for 4 bit magnitude comparator and explain it,
Solution to Digital Logic -2067 Solution to digital logic 2067 1.)What is the magnitude comparator? Design a logic circuit for 4 bit magnitude comparator and explain it, A Magnitude comparator is a combinational
More informationDEPARTMENT OF COMPUTER SCIENCE & ENGINEERING
DRONACHARYA GROUP OF INSTITUTIONS, GREATER NOIDA Affiliated to Mahamaya Technical University, Noida Approved by AICTE DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING Lab Manual for Computer Organization Lab
More informationGood Evening! Welcome!
Page 1/11 Instructions: urn off all cell phones, beepers and other noise making devices. Show all work on the front of the test papers. Box each answer. If you need more room, make a clearly indicated
More informationACS College of Engineering. Department of Biomedical Engineering. HDL pre lab questions ( ) Cycle-1
ACS College of Engineering Department of Biomedical Engineering HDL pre lab questions (2015-2016) Cycle-1 1. What is truth table? 2. Which gates are called universal gates? 3. Define HDL? 4. What is the
More informationCollections of flip-flops with similar controls and logic
Ensembles of flip-flops Registers Shift registers Counters Autumn 2010 CSE370 - XV - Registers and Counters 1 Registers Collections of flip-flops with similar controls and logic stored values somehow related
More informationStatic Timing Analysis for Nanometer Designs
J. Bhasker Rakesh Chadha Static Timing Analysis for Nanometer Designs A Practical Approach 4y Spri ringer Contents Preface xv CHAPTER 1: Introduction / 1.1 Nanometer Designs 1 1.2 What is Static Timing
More informationispmach 4000 Timing Model Design and Usage Guidelines
September 2001 Introduction Technical Note TN1004 When implementing a design into an ispmach 4000 family device, it is often critical to understand how the placement of the design will affect the timing.
More informationImplementation of Dynamic RAMs with clock gating circuits using Verilog HDL
Implementation of Dynamic RAMs with clock gating circuits using Verilog HDL B.Sanjay 1 SK.M.Javid 2 K.V.VenkateswaraRao 3 Asst.Professor B.E Student B.E Student SRKR Engg. College SRKR Engg. College SRKR
More informationWINTER 15 EXAMINATION Model Answer
Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in the model answer scheme. 2) The model answer and the answer written by candidate
More informationDesign and Implementation of an AHB VGA Peripheral
Design and Implementation of an AHB VGA Peripheral 1 Module Overview Learn about VGA interface; Design and implement an AHB VGA peripheral; Program the peripheral using assembly; Lab Demonstration. System
More informationModeling Latches and Flip-flops
Lab Workbook Introduction Sequential circuits are digital circuits in which the output depends not only on the present input (like combinatorial circuits), but also on the past sequence of inputs. In effect,
More informationVHDL Design and Implementation of FPGA Based Logic Analyzer: Work in Progress
VHDL Design and Implementation of FPGA Based Logic Analyzer: Work in Progress Nor Zaidi Haron Ayer Keroh +606-5552086 zaidi@utem.edu.my Masrullizam Mat Ibrahim Ayer Keroh +606-5552081 masrullizam@utem.edu.my
More information