VHDL -standardni jezik za opis digitalnih kola i sistema.
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1 Uvd u VHDL
2 VHDL VHDL -standardni jezik za pis digitalnih kla i sistema. VHDL standard usvjen 987. gd. (IEEE 076). Revidiran i trenutn aktuelni VHDL standard, IEEE 64, usvjen 993. gdine. Skraćenica d VHSICHardware Descriptin Language. VHSIC skraćenica d Very High Speed Integrated Circuits (Integrisana kla vema velike brzine rada) Arhitektura mikrsistema
3 VHDL Osnvna namena: Jezik za dkumentaciju Jezik za simulaciju Savremena primena: Sinteza hardvera Naš cilj: Sinteza kmbinacinih i sekvencijalnih kla i sistema niske i srednje slžensti u VHDL-u Obiman i slžen jezik Dbra vest: za sintezu, bitan je sam jedan manji de mgućnsti VHDL jezika. Arhitektura mikrsistema
4 Prgramski jezik vs. jezik za pis hardvera Prgramski jezik: Opis algritma Sekvencijalni mdel izračunavanja Kmpajlira se u mašinski prgram radi izvršenja na računaru Jezik za pis hardvera: Opis algritma Opis strukture digitalng sistema Knkurentni mdel izračunavanja Kmpajlira se radi simulacije u RTL simulatru Sintetiše se radi implementacije u hardveru Termini: Prgram -pis algritma u prgramskm jeziku Kôd pis algritma ili strukture u jeziku za pis hardvera Arhitektura mikrsistema
5 Organizacija VHDL kôda Svaki celvit VHDL kôd, tj. naj kji se mže simulirati ili sintetizvati, sastji se iz tri sekcije: Arhitektura mikrsistema
6 LIBRARY LIBRARY (bibliteka) Klekcija čest krišćenih delva VHDL kôda. Jednm se piše više puta kristi Sadrži pakete (PACKAGE), a paketi sadrže: Funkcije (FUNCTION) Prcedure (PROCEDURE) Kmpnente (COMPONENT) Knstante (CONSTANT) Tipve pdataka (TYPE) Arhitektura mikrsistema
7 LIBRARY Bibliteka se uključuje u prjekat pmću dve naredbe: LIBRARY ime_bibliteke; USE ime_bibliteke.ime_paketa.delvi_paketa; LIBRARY -definiše ime bibliteke USE definiše delve bibliteke kje želim da kristim Bar tri paketa iz tri različite bibliteke su nephdna u svakm prjektu: std_lgic_64 (iz bibliteke ieee) standard (iz bibliteke std) i wrk (iz bibliteke wrk) LIBRARY ieee; USE ieee.std_lgic_64.all; LIBRARY std; USE std.sdandard.all; LIBRARY wrk; USE wrk.all; --tačka-zarez (;) značava --kraj naredbe ili deklaracije --dupla crta (--) značava kmentar Arhitektura mikrsistema
8 LIBRARY Standardne bibliteke: std je bibliteka resursa (standardni tipvi pdataka i sl.). wrk je prjektna bibliteka (za smeštanje fajlva prjekata) IEEE bibliteka za sintezu, paketi : std_lgic_64: definiše višenivvske lgičke sisteme numeric_std: pdrška za aritmetiku Bibliteke std i wrk p autmatizmu uključene u svaki prjekat. VHDL kôd za sintezu bičn pčinje linijama: LIBRARY ieee; USE ieee.std_lgic_64.all; Arhitektura mikrsistema
9 ENTITY Entitet (ENTITY): definiše interfejs (ulaze i izlaze, tj. prtve kla) ENTITY ime_entiteta IS PORT ( ime_prta : smer_signala tip_signala; ime_prta : smer_signala tip_signala;... ); END ime_entiteta; Prt (PORT): izlazni ili izlazni signal kla Smer signala IN ulaz, OUT izlaz, INOUT dvsmerni prt (ulaz/izlaz), BUFFER - izlaz kji se mže kristiti ka interni signal. Tip signala: BIT, STD_LOGIC, INTEGER... Arhitektura mikrsistema
10 ENTITY ENTITY ni_kl IS PORT (a, b : IN BIT; c : OUT BIT); END ni_kl; Opisuje spljni pgled na kl, a ne funkciju kla Više prtva istg smera i tipa mgu biti deklarisani u istj liniji Linije PORT knstrukcije završavaju se znakm ;, sim pslednje, nakn kje sledi zatvrena zagrada Ime entiteta mže da sadrži slva, cifre i crtu za pdvlačenje. Ograničenja: ne mže pčeti cifrm, ne mže biti ključna reč VHDL ne pravi razliku između velikih i malih slva Arhitektura mikrsistema
11 ARCHITECTURE Arhitektura (ARCHITECTURE) sadržati pis funkcinisanja (pnašanja) ili pis unutrašnje strukture kla ARCHITECTURE ime_arhitekture OF ime_entiteta IS [deklaracije] BEGIN [kôd] END ime_arhitekture; Uvek pridružena jednm entitetu (ime_entiteta) [deklaracije]: definiše interne signale i knstante [kôd]: kôd arhitekture Arhitektura mikrsistema
12 ARCHITECTURE ARCHITECTURE ni_funkcija OF ni_kl IS BEGIN c <= a NAND b; END ni_funkcija; Kl bavlja NI peraciju (NAND) nad dva ulazna signala, a i b, i rezultat ddeljuje ( <= ) izlaznm pinu c. Naredba ddele se izvršava uvek kad se na nekm d signala a ili b desi dgađaj. Dgađaj na signalu -prmene vrednsti signala. Naredba ddele je senzitivna na prmenu vrednsti bil kg signala s leve strane znaka <=. Arhitektura mikrsistema
13 Stilvi prjektvanja u VHDL-u Funkcinalni (ili bihejviralni) Knkurentne naredbe (dataflw, tj. mdel tka pdataka) Sekvencijalne naredbe (sekvencijalni mdel, ka kd prgramskih jezika) Strukturni (ekvivalentn blk dijagramu) Mešvit (kmbinacija knkurentnih/ sekvencijalnih naredbi i strukturng pisa) Arhitektura mikrsistema
14 Knkurentn izvršenje naredbi ENTITY primer IS PORT(a, b, c: IN BIT; y : OUT BIT); END primer; ARCHITECTURE dataflw OF primer IS SIGNAL x : BIT; BEGIN y <= x NAND c; x <= a NAND b; END dataflw; Arhitektura sadrži knkurentni kd Naredbe se iniciraju prmenama signala Redsled naredbi nije d značaja (isti efekat ima sledeći kd): x <= a NAND b; y <= x NAND c; Deklaracija interng signala Knkurentne naredbe Arhitektura mikrsistema
15 Mdeliranje prpagacing kašnjenja Naredba ddele prširena klauzulm after: x <= a NAND b after 20 ns; δ -kašnjenje: besknačn mal kašnjenje x <= a NAND b; ist št i x <= a NAND b after 0 ns; ENTITY primer IS PORT(a, b, c: IN BIT; y : OUT BIT); END primer; ARCHITECTURE dataflw OF primer IS SIGNAL x : BIT; BEGIN y <= x NAND c after 20 ns; x <= a NAND b after 20 ns; END dataflw; Navđenje prpagacing kašnjenja nije dzvljen u kdu za sintezu! 20 ns 20 ns Arhitektura mikrsistema
16 Prt smera OUT se ne mže kristiti ka ulazni signal! Neispravn LIBRARY ieee; 3 USE ieee.std-lgic-64.all; ENTITY mde-dem IS 6 PORT (a,b: IN STD_LOGIC; 7 x,y: OUT STD_LOGIC); 8 END mde-dem; ARHITECTURE pgresn OF mde-dem IS BEGIN 2 x <= a AND b; 3 y <= NOT x; 4 END pgresn; x je izlazni prt! (a) Arhitektura mikrsistema Ispravn ARHITECTURE ispravn OF mde-dem IS SIGNAL ab : STD_LOGIC; 2 BEGIN 3 ab <= a AND b; 4 x <= ab; 5 y <= NOT ab; 6 END ispravn; Interni signali se mgu kristiti i ka ulazi i ka izlazi
17 Opis tabele istinitsti Omgućava mdeliranje (pisivanje) funkcije ili pnašanja kla bez ulaženja u strukturne detalje a b I v je knkurentan kd c y ARCHITECTURE dataflw OF primer IS BEGIN WITH (a & b & c) SELECT y <= '' WHEN "000", '0' WHEN "00", '' WHEN "00", '0' WHEN "0", '' WHEN "00", '0' WHEN "0", '' WHEN "0", '' WHEN ""; END dataflw; Arhitektura mikrsistema
18 Sekvencijalne naredbe Prces: sekvencijalna sekcija kôda (naredbe u prcesu se izvršavaju jedna za drugm) LIBRARY ieee; USE ieee.std_lgic_64.all; ENTITY dff IS PORT (d, clk, rst: IN STD_LOGIC; q: OUT STD_LOGIC); END dff; ARCHITECTURE behavir OF dff IS BEGIN PROCESS (rst,clk) BEGIN IF(rst='') THEN q <= '0'; ELSIF (clk'event AND clk='') THEN q <= d; END IF; END PROCESS; END behavir; Desi se dgađaj na signalu lista senzitivnsti (prmena bil kg signala iz liste pkreće prces) Arhitektura mikrsistema d clk rst DFF Detektuje rastuću ivicu takta q
19 Mešvit pis- Knkurentni/sekvencijalni kd Arhitektura je kvir za knkurentni, a prces za sekvencijalni kd ARCHITECTURE primer OF primer IS SIGNAL x : BIT; BEGIN x <= d NAND d2; PROCESS(clk) BEGIN IF(clk'EVENT AND clk='') THEN q <= x; END IF; END PROCESS; END primer; Prces se izvršava knkurentn sa stalim naredbama iz arhitekture Arhitektura mikrsistema
20 Strukturni pis Opisuje slženije kl ka skup pvezanih kla manje slžensti Zasnvan na knceptu kmpnenti Kmpnenta: Celviti VHDL pisi (entitet plus arhitektura) kji se jednm piše, a nda kristi za knstrukciju slženijih mdela Pakuju se u pakete Arhitektura mikrsistema
21 Strukturni pis -primer Primer Micrsft Wrd Dcument Kmpnente Sistem se pisuje ka skup pvezanih kla manje slžensti. U suštini, tekstualni pis blk dijagrama Arhitektura mikrsistema
22 Mešvit pis - knkurentni/strukturni kd ARCHITECTURE struct OF pr9 IS -- kmpnenta dff COMPONENT dff IS PORT (d, clk: IN STD_LOGIC; q: OUT STD_LOGIC); END COMPONENT; SIGNAL x : STD_LOGIC; BEGIN x <= d NAND d2; K2: dff PORT MAP(x, clk, q); END struct; Naredba za instanciranje kmpnente Arhitektura mikrsistema Knkurentna naredba ddele
23 Prjektne jedinice Nedeljiva sekcija VHDL kôda U ptpunsti sadržana u jednj prjektnj datteci (prjektna datteka mže sadržati prizvljan brj prjektnih jedinica) T su: Entitet Primarna Arhitektura Deklaracija paketa Sekundarna Tel paketa Knfiguracija Jedna primarna, više sekundarnih Definiše spj primarne Arhitektura mikrsistema i sekundarne jedinice
24 Prcesiranje VHDL kda Faze u prcesiranju kda:. Analiza (psebn svaka prjektana jedinca) Sintaksna analiza i kmpilacija. Rezultat je međukd prjektinih jedinica kji se smešta u bibliteku wrk. 2. Elabracija 3. Izvršenje Hijerarhijski kd u ravanski kd. Zamena instanci kmpnenti njihvim arhitekturama Simulacija ili sinteza Arhitektura mikrsistema
25 Simulacija VHDL kda d clk DFF q rst stimulansi dziv Arhitektura mikrsistema
26 Testbenč Micrsft Wrd Dcument Ddatni kd kji generiše stimulanse Kd kji se testira Ddatni kd kji analizira dziv testbenč Arhitektura mikrsistema
27 CONFIGURATION Jedan entitet više arhitektura. Knfiguracija -spj entiteta i arhitekture Kak arhitekturu pvezati sa entitetm? Štampana plča Odgvara entitetu Kućište Analgija IC IC2 IC3 (a) (b) Arhitektura mikrsistema Odgvaraju arhitekturama
28 CONFIGURATION -- Instanciranje kla kje se testira uut: simple_circuit PORT MAP(a=>test_in(2),b=>test_in(),c=>test_in(0),y=>test_ut); Definiše arhitekturu kmpnenta simple_circuit kja se kristi CONFIGURATION dem_cnfig OF simple_circuit_testbench IS FOR tb_arch FOR uut : simple_circuit USE ENTITY wrk.simple_circuit(behavir); END FOR; END FOR; END dem_cnfig; Ak pstji sam jedna arhitektura, CONFIGURATION nije nephdn! Arhitektura mikrsistema
29 Sinteza VHDL kda Preslikavanje jezičkih knstrukcija iz VHDL kôda na hardverske elemente identičng pnašanja (funkcije) Nije mguće sintetizvati prizvljan VHDL pis! Pjedine jezičke knstrukcije se ne mgu sintetizvati. Pjedine se mgu sintetizvati uz dređena graničenja Pjedine se mgu sintetizvati Arhitektura mikrsistema
30 Primer sinteze. krak... f <= x AND y; f2 <= x AND NOT y; f <= f OR (f2 AND z) OR (f2 AND w); krak 3. krak Funkcinalna mreža Optimizvana funkcinalna mreža Arhitektura mikrsistema Lgička mreža - knačni rezultat sinteze
31 Slženiji primer sinteze Aktivnsti prjektanta Aktivnsti sftvera za sintezu Knceptualni dijagram Funkcinalna mreža... f <= a + b WHEN ctrl= 0 ELSE a b:... VHDL kd Arhitektura mikrsistema Optimizvana funkcinalna mreža
32 Ulga VHDL-a u prcesu prjektvanja Funkcinalna simulacija Vremenska simulacija nakn sinteze Vremenska simulacija nakn fizičkg prjektvanja Arhitektura mikrsistema
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