Level and edge-sensitive behaviour

Transcription

1 Level and edge-sensitive behaviour Asynchronous set/reset is level-sensitive Include set/reset in sensitivity list Put level-sensitive behaviour first: process (clock, reset) is begin if reset = '0' then Q <= '0'; elsif rising_edge (clock) then Q <= D; end if; end process;

2 Combinational Logic If a process is not edge-sensitive and it's not a latch (all executions of a process have an assignment to a signal or variable), it must be combinational logic Process sensitivity list must include all signals on the RHS of assignments or referenced in if or case statements But many synthesis tools correct this Can cause differences between simulated and synthesised behaviour Tristate logic generated by explicit assignments of 'Z'

3 Concurrent Statements Combinational logic can be modelled with concurrent statements: y <= '0' when x = '1' else '1'; Particularly useful for tristates: y <= '0' when x = '1' else 'Z'; What does this model? Q <= D when E = '1'; Or this? Q <= D when E = '1' else Q; Why is this a bad idea?

4 Synthesis Constraints Specify Design Objectives in terms of e.g. Area Clock speed Delay Constraints are (usually) not part of VHDL but are vendor-specific Use separate constraints file

5 Constraints All optimisation, in terms of meeting constraints, assumes that there is more than one way to implement a function: A B C D E C D A B D E Smaller, slower Faster, larger

6 Area Constraints Primary constraint is choice of device! Can define overall objective of synthesis to be area minimisation. This can also be done per module: define_sharing full_adder on The compiler would attempt to share resources (e.g. gates) in the full_adder.

7 State Encoding The state encoding can be specified in the VHDL: type state is (s0, s1, s2, s3); attribute enum_encoding of state: type is " "; Or as an attribute passed to the synthesis tool

8 Predefined Modules We might wish to leave parts of a design untouched by synthesis, because they are predefined modules. We can do this with: define_black_box full_adder true I/O buffers can be similarly defined

9 Clock Speed The maximum clock speed is defined by the choice of device. The desired clock speed can be set as a design objective: define_clock CLK1 -freq 20.0 Defines 20 MHz clock Objective for Synthesis AND Place and Route

10 Timing Constraints Delay 1 ns D Q Q Comb Logic Setup 1 ns D Q Q Clock Frequency is 20 MHz, Clock period is 50 ns, Max delay through Comb Logic is 48 ns

11 Timing Constraints D Q D Q Input logic Q Q Output logic External Input and Output delays can be specified: define_input_delay In Thus the maximum delay through the input logic is 39 ns

12 Delay Constraints In this (Synplify) example, the external delay of the sum signal is modelled to have a delay of 8 ns. entity four_bit_adder is port (sum: out std_logic_vector (0 to 3); co : out std_logic; a, b : in std_logic_vector (0 to 3); ci : in std_logic); end four_bit_adder; We state an objective of trying to improve this by 2 ns by optimising the input logic. define_output_delay sum 8.0 -improve 2.0 This objective is not passed to the place and route tool

13 Routing Delays Optimisation by the synthesis tool is based on statistics After place and route, design may not meet timing objectives Resynthesise to improve by 3.8 ns: define_output_delay sum route 3.8

14 Multiple Clock Cycles The specification of a clock speed assumes that in a synchronous design all combinational operations are completed within the clock period If an operation takes more than one cycle, this can be flagged: define_multicycle_path q true

15 Technology FPGAs vs ASICs FPGAs have fixed resources, ASICs are more flexible Mapping to cells is different, therefore the backend of synthesis tools is different FPGAs have a limited number (maybe none) of tristate buffers Synthesis tool may need to map tristate assignments to "standard" logic Each gate has a limited fanout May need to insert buffers

16 State Assignment Design has 10 states - how many flipflops? "One Hot" assignment (e.g. Synplify) One flip-flop per state. Exactly one flip-flop is asserted in each state: s s s etc Good for FPGAs (that have lots of flipflops) as next state logic is simple

17 Clock trees, DfT etc ASICs may need complex clock trees Generated separately Scan paths, BIST in ASICs Inserted pre- or post-layout Not necessarily part of the standard synthesis process Physical synthesis Estimate delays due to layout prior to full place and route "State of the Art" in ASIC synthesis